Am Samstag, den 26.11.2005, 12:25 -0500 schrieb Timothy Miller: > Thank you, Victor, for pointing out the race condition in the sync > fifo. What I did was add an additional cycle delay on tail0 (calling > it tail4). This way, the data will change before the tail pointer. > This may be overkill, but what I decided to do was first add a delay > in in_clock so as to ensure that the delay is sufficient (if I did it > only in out_clock, the edge could arrive too soon), and then add > another delay in out_clock so as to eliminate race conditions in the > logic of the comparators. Tell me what you think:
Is the delay in out_clock really necessary? All pointers are gray-coded, so the race condition is supposed to occur between the single changing bit and... what? The FIFO has way too many states to examine them manually, so while it was useful for proving the existence of a race condition, it's useless for proving their absence. A testbench for the FIFO would really help here. - Viktor Pracht _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
