Timothy Miller wrote: > On 11/29/05, Peter TB Brett <[EMAIL PROTECTED]> wrote: >> Timothy Miller <theosib <at> gmail.com> writes: >> >> > Also, in dealing with domain crossing, I have seen other people use a >> > chain of two registers in the receiving domain as a means to "deal >> > with metastability", although I'm not entirely sure how that all >> > works. >> >> Metastability is an unstable state, and getting a register to be >> metastable is >> akin to balancing a marble on the peak of a sombrero. ;) >> >> So basically, if the first register manages to become metastable, the >> probability that the second will become metastable is very low -- so the >> probability of the pair becoming metastable is close to infinitesmal. >> >> I've used this technique in asynchronous buses before, and it seems to >> work >> really well... *shrug* > > That makes sense.
Well, it was a bit of a simplification -- it just reduces the MTBF. But hopefully far enough. > Taking that a step further, the comparison between tail and head0 > could have problems too, so we should register head0 twice just to be > safe. > > What do you think? I'm afraid I'm not well-versed enough in Verilog or high-speed design to help you out, I'm afraid. Ideally you should keep the probability of timing violations low enough that you never need double-registering within your synchronous logic, but at the clock speeds you're designing for that may not be practical or even realistic. Peter -- Quake II build tools: http://peter-b.co.uk/ Latest QuArK: http://quark.sourceforge.net/LatestVersion v2sw6YShw7ln5pr6ck3ma8u7Lw3+2m0l7CFi6e4+8t4Eb8Aen4g6Pa2Xs5MSr5p4 hackerkey.com _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
