On 4/14/06, Timothy Baldridge <[EMAIL PROTECTED]> wrote: > So what benifits are you going to have in using CISC over RISC? > Smaller code sizes I guess, at the the expense of complexity. > > I'm thinking for a GPU wider is going to be better than deeper. With > FPGAs were are going to be limited by the clock. Why make it worse by > going to CISC that relys on higher clock speeds? Why not make a simple > core so that we can pack 16-24 of them in one FPGA instead of one that > will take up half the CPU? >
Actually, deeper is always better unless you have control and dependency hazards. We can easily enough avoid the dependency hazards, so all we have to worry about are loops in shader code. When the shader loop is done with a pixel it can just toss it down the pipeline. We can unload a lot of computation from the microcode stage by doing it later in the pipeline. It doesn't matter how many stages don't do any useful work. The only time a GPU's pipeline becomes a real problem is when you have to read from something you've just written to, like if you've drawn to a texture and then want to use it as a texture. Then you have to flush the pipeline. You also have to worry about bitblts to and from the same surface (we can use some intelligence to avoid it sometimes). _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
