On 4/13/06, Timothy Baldridge <[EMAIL PROTECTED]> wrote: > On the discussion about GPUs for OGP: > > Here is an off the wall idea a friend and I were talking about a while > back. I think that it would be of great use in a GPU. The idea is to > create a "modularized" RISC processor. Here is a basic rundown: > > The CPU accepts 3 instructions: > load > store > mov >
This reminds me of a design someone was calling "MISC". (Minimal Instruction Set Computer) Basically, the only instructions were "moves". If you want to perform some computation, you move the source operands into special purpose registers and then move the result out of its special purpose register. Results queue up, so you can pop them out any time you like. I didn't go anywhere with this idea because it makes context switches hell, but for an embedded design with no interrupts, it would work fine. Before we get into implementation details, however, we really need to figure out what our requirements are. Based on what little I know about shaders, I don't know enough to decide between what you describe, a stack architecture, a 3-operand load/store machine, a 2-operand load/store, etc. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
