On 8/19/07, Mark <[EMAIL PROTECTED]> wrote: > It doesn't appear as though Synplify for Lattice will do so. I get the > same timing with 1, 2, or 3 stages of registers after the multiplier and > the number of registers in the map report goes up as expected.
Ok. That's fine. We can manually pipeline things as necessary. > Is it possible Xilinx doesn't automatically pipeline multipliers in > general, only hard multipliers? My guess is that they push those > registers during mapping, not during synthesis. Yeah. Somehow, it must mark the registers as movable. Obviously, it can't affect hard multipliers, but the soft ones can be manipulated. Separate from that, there's automatic register balancing. This is done during synthesis (that's when all the messages come out about them being moved). I find this a bit odd because until P&R is done, timings are only gross estimates. This didn't used to be the case when transistors dominated circuit delays; but ever since wire delay became dominant, physical synthesis has become progressively more necessary. I would LOVE to be involved in a project that was developing a good Free Software physical synthesis tool. I have the background in AI, so I could help develop the algorithms for P&R (on top of the other stuff I know about chip design). I would be amazed if we couldn't get enough info out of Xilinx and Lattice to be able to target their devices. Obviously, they'd hold some stuff back, but it would come out eventually. The ideal situation would be if we could officially replace their commercial tools because ours turned out to be better. That would take years, but we could manage it. Stephen Williams would probably be interested in this. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
