I think a lot of these messages (I could also reply to "VGA Decode on
PCI" or "Interested Hacker" -- it all boils down to the same thing)
are because of two things;
1) There's little documentation on where we're coming from.
2) There's little documentation on where we're going to.
I'm taking my own project here as an example (www.wacco.mveas.com)
because I think I'm doing a few things right which the OGP is doing
wrong. I'm deliberately writing down on a weekly basis everything
I've done for the project regarding why I've made certain decisions,
how things like data buses are layed out, what resistors I'm using,
how the project is coming along and what the next step is. It might
not be the most interesting story, but if you at some crazy point in
the future want to know why a resistor is 68R instead of 1K, or why a
data bus has 38 lines instead of 39, you can find it easily. And for
me it's not a big deal to spend an hour a week making a coherent
story out of my notes.
OGP has nothing like that, all we know for example (until about a
week ago, when the schematic came online) is that there's a
'connection' between the CPLD and the FPGA. However, if I want to
know how the two communicate, all I can find (with difficulty) is how
many data lines there are drawn. Not helpful.
On the other hand I don't know if the communication between the two
is already working. If I'm going to spit through the version control
I'll probably dig up something, but why am I supposed to dig in the
first place? Isn't there a place where it says how this works? I
can't even find anything that says wether or not this piece of code
is written yet and how/what it's supposed to do.
A very big part of this information must be available *somewhere* in
some form already because the schematic and the PCB are already
designed and a presentation with the card working (including earlier
mentioned interface) has been given. I don't think it's up to the
community to start thinking of where we want to go or how things are
currently working before the original designers of these components
spit out some details. If people in the community have to figure out
(dare I say, reverse engineer) the amount of datalines between
components, we're just wasting resources bigtime.
Mike
On 31 Oct 2007, at 09:04, Petter Urkedal wrote:
- snip -
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