On 10/31/07, Michael Meeuwisse <[EMAIL PROTECTED]> wrote: [snip] > A very big part of this information must be available *somewhere* in > some form already because the schematic and the PCB are already > designed and a presentation with the card working (including earlier > mentioned interface) has been given. I don't think it's up to the > community to start thinking of where we want to go or how things are > currently working before the original designers of these components > spit out some details. If people in the community have to figure out > (dare I say, reverse engineer) the amount of datalines between > components, we're just wasting resources bigtime.
I don't disagree with anything you said. The problem is that since Andy, Howard and I are the "most qualified" to document this stuff, people leave it up to us to do it. But we're overextended, so we don't have time to do it. So it doesn't get done. Soon enough, we'll publish things like padrings for the FPGAs that will give names to the pins, and that'll explain the connections. But in the mean time, although I'm weak with schematics, I'd be happy to try to help someone document this for the wiki, based on the schematic. (Note that for Howard, the documention IS the schematic. He wrote it and is used to thinking about boards this way. It's like reading German for someone who lives in Berlin.) -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
