Hi Abdulrahman,
I read your email and thought I would throw in my two cents worth. The following
comments are meant more for educational purposes, and not to flame your email. The
technology in our field is rapidly changing, and we need to help each other keep
abreast of these changes. After all, isn't that what this forum is all about?
Anyhow, read on......
-----Original Message-----
From: [EMAIL PROTECTED]
Sent: Wednesday, March 14, 2001 7:44 PM
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Subject: Re: [PEDA] Use Pad Stack
It's important to realize that CAD programs may be thoroughly checked for
bugs, but when they hit the real world, they may be fed data that was not
anticipated and therefore the behavior of the program has not been tested.
Further, whenever we attempt to do something non standard, we are not only
entering an area which may not have been anticipated in testing or explored
even in beta test, but we may also have expectations regarding the behavior
of the program that are personal and not necessary what everyone would expect.
In this case, remember that surface pads were conceived as surfaces for
mounting SMT components. Conceptually, they don't have holes, period.
Probably the dialog box should suppress the hole attribute when the pad is
assigned to top or bottom. In my opinion, that is the real oversight, that
such holes are allowed at all.
[Bruce:] This will create problems for people trying to do HDI designs. This is the
wave of the future with respect to SMD layouts that need to be compressed into smaller
spaces (better than 50% space savings with HDI over conventional SMT designs). Many
Japanese designs have been using HDI for some time now. I suggest that you read up on
this topic to gain some insight into where the technology is heading.
Otherwise, if a pad has a hole, it is a through hole: i.e., it's a hole
through the board. That's exactly what multilayer pads are, if they have holes.
[Bruce:] Not quite true anymore... HDI requires a laser drilled hole, often only the
first two layers (incredibly small by the way 0.003" to 0.010"). This is essentially
a blind via, but should be defined as part of the pad as all interconnects to the
surface mount pad will be made through these micro vias. Another issue is raised with
this technology though.... It is important for some of the emerging technology to
have a "window" on the surface mount pad for the laser to burn through the outer
layers (otherwise the laser beam is reflected, etc.). As far as I know, it isn't
possible yet to define this "copperless window" in Protel yet.
If one wants to put a via in a surface pad, then put a via or free pad in a
surface pad!
[Bruce:] Not really an option for HDI. How difficult do you think it would be to
make the placement of those HDI micro vias on a fine pitched board? I suppose it
would work, but personally I would rather define that in the decal library.
Some of us want the program to have more flexibility and some of us want
the program to be more secure, foolproof. I don't think that both criteria
are easy to maximize at the same time.
It is probably more often an error than not that a hole exists in a surface
pad. It's easy to do: one is making a footprint, and places a pad, and
because the last pad placed was a through pad, one changes the layer to the
surface and forgets to remove the hole. Depending on display settings, this
may not be obvious.
Since everything desireable about surface pads with holes can be attained
with padstacks (or alternatively with pad combinations), I'd vote for
locking out holes in surface pads. Existing designs would still allow such
primitives, that's necessary for legacy designs, but it would become
impossible to create them through the normal interface. (If a pad already
had a hole, it should still be possible to edit the hole size. There would
thus be a workaround if someone really finds a necessity for surface pads
with holes in their center.)
(Note that we'd love to put vias in pads for bypass capacitors, so that the
loop area would be minimized. But the ideal location for such a via would
not be the pad center, but would be shifted toward the cap centroid. In
fact, the ideal location might not be in the pad at all, but underneath the
part even farther toward the centroid. Note that this is not a license for
via in pad, which can create serious assembly problems!)
[Bruce:] Assembly problems are eliminated in HDI (I'm assuming you are referring to
the solder paste drain problem) because the holes are so small that the surface
tension will hold the solder on the SMD pad (rather than flowing through the micro
via). This is well tested and proven in Japan (you know how important quality is to
the Japanese).
[Bruce:] Anyone interested in HDI can send me an email and I would be happy to point
them in the right direction to learn more about it.
[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433
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