<snip>
> As was noted already, it sounds like Luo wants a bottom pad with nothing
> on the other layers. To accomplish this, simply set the pad attribute to
> "Bottom." There will then be no pad or soldermask geometry on any other
> layer, assuming that the hole size is zero; and I do not recommend setting
> a non-zero hole size with a surface pad (Top or Bottom). Pad stacks are
> not appropriate for this kind of application.
>
> Abdulrahman Lomax
Out of curiosity, what do you suggest should be done in a situation where
someone wants an unplated hole through a PCB, and this hole is to pass
through the middle of a pad on the bottom (copper) layer?
My understanding is that whenever a hole in a PCB *is* through-plated, then
it is always advisable to have a minimal width of copper surrounding the
hole on each copper layer. As an example, if there should be at least 5mil
of copper surrounding each hole, and a hole's diameter is 20mil, then the
minimum width and height of the associated pad on any layer (Top, Bottom, or
(intermediate) Middle) is 30mil (allowing 20mil for the hole and 5mil on
*each* side of this).
If you do not want *any* copper surrounding a hole on any layer except for
the bottom layer (or in the case of a through-hole component mounted on the
*bottom* side of a PCB, you do not want any copper surrounding a hole on any
layer except for the top layer), then that suggests that you should set the
pad's Layer (property) to Bottom (signal/copper) (or to Top (signal/copper)
if the associated component is fitted on the PCB's bottom side instead), and
the pad's plated property should be set false.
However, I seem to recall past discussions on this forum in which it was
claimed that tracks can not be wired to unplated pads. I haven't checked
that aspect recently, but I seem to recall that unplated pads could not be
wired to in at least some circumstances.
I do not use such types of pads myself. Ideally, all holes in a PCB should
be plated through, as it costs more to use a mix of plated through holes and
unplated holes. That said, many of the PCBs which I design *do* use a mix of
hole types. However, *all* unplated holes within these PCBs are holes only;
they are *not* surrounded by copper on *any* layer, including *both*
external copper layers.
If I am using a device like a through-hole crystal, where large pads on the
top copper layer could short with the body of the crystal, I use the
padstacks feature with *plated* holes. The pads on the internal (Middle) and
bottom layers are "meaty", but I set the pads on the top layer to be as
"skimpy" as possible. (The associated pads are on the MultiLayer layer.)
However, some users might prefer to totally forsake pads on the top layer
*and* internal layers, and use pads *solely* on the bottom layer. In such
cases, the associated holes should not be plated through. In other words,
each pad is on the bottom copper layer, with a hole of non-zero diameter,
and the pad/hole is not plated.
Can this be regarded as a shortcoming of Protel?
I'd like to talk more about pads (e.g. should the padstacks feature be
disabled *unless* the pad is on the MultiLayer layer?; should the padstacks
feature be enhanced in certain ways?; how should totally "copper-less" holes
be handled?; and others), but I have other things to do at this stage. But
others are welcome and even invited to comment on such matters.
Regards,
Geoff Harland.
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