Brad:

Thank you for your advice. I have done exactly what you have suggested in
other cases and lived with the junction that appears. This still is not
adequate though, for it appears to be an error of some kind on the
schematic. Perhaps it is the best for now. I am hoping Protel will recognize
and address this problem.

Thanks,
Daniel


-----Original Message-----
From: Brad Shea [mailto:[EMAIL PROTECTED]]
Sent: Monday, October 22, 2001 11:26 PM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] TO-3 footprint question


Daniel,

We have had this exact problem on a TO-3 device as well as a couple of
similar devices.
The easiest way we found to get around it was on the schematic symbol to
place the pins (in your case pins 3 and 4) on top of each other. What this
does is place a junction on your schematic, this is visually not ideal but
it removes any errors as well as the need for manually changing the nets of
free pads.

Brad

____________________________________________

Brad Shea
Senior PCB Designer

PowerSearch Ltd

121 Ewing St
Welshpool WA 6106
Australia

email:[EMAIL PROTECTED]
Phone:  (08) 9358 3633
Fax:          (08) 9358 3644
____________________________________________


-----Original Message-----
From: Daniel Webster [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, 23 October 2001 7:01 AM
To: Protel EDA Forum
Subject: [PEDA] TO-3 footprint question



Hello everyone:

I have created a footprint for a TO-3 NPN transistor. The TO-3 can as you
may be aware has two mounting holes, in my case these two mounting holes are
attached to the collector of the transistor. I have a pad for each mounting
hole which I have labelled pad 3 and pad 4. Now when I create my schematic
symbol for this part, I am supposed to use the standard NPN transistor
symbol, which only has 3 pins (E-1,B-2,C-3). If I want to display a 4th pin
and connect it to the collector on my symbol, I end up with an odd looking
transistor symbol, that know one will understand or appreciate. If I hide
pin 4, as someone suggests, then I can not hook it up to the desired net. If
I omit pin 4 from the schematic and reload the netlist into the pcb, the
program will attempt to disconnect pin 4 from it's net, and if I manually
connect it I will get a DRC error. I would like the schematic and pcb to
match with no netlist hickups. I do not see anyway around this problem,
other than to live with the DRC error, or create an additional pin on the
schematic symbol, neither of which seem a very elegant solution. Perhaps I
should suggest to Protel that with their new version, they allow a single
pin to be assigned to more than one pad. In fact it would be very useful to
have a single pad assigned to different nets with no DRC error, in order to
form a star point gnd. Any comments or suggests would be appreciated.

Thanks,
Daniel Webster
PCB Designer
Northern Airborne Technology
Kelowna, BC, Canada
Email: [EMAIL PROTECTED]



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