At 03:12 PM 12/17/01 -0800, Leonard Fischer wrote: >If they don't, or don't quickly enough to do what you need, could you work >at some multiplication/magnification of the final scale, say 10x, then >just "photographically" reduce the Gerbers? I'm assuming there is some >way to do that (Camtastic?), not that I know how.
The gerbers will be provided to a fabricator who could certainly scale them down. It's really only a matter of manipulating an RS-274X parameter. >This could help with the precision issue in Protel and the magnification >in Camtastic. > >Just like working with 4x decals and tape! Yes, though I always worked at 2X. I did do some magnified designs with Tango years ago. I wrote a little routine that would magnify a board, it is not a difficult problem. It gets a bit more complicated with Protel, what with design rules, etc., etc. But still doable. I think it could be done in the spreadsheets. >I'm also assuming that the ceramic module is relatively small compared to >a PC Board - I'd be interested in hearing more about the ceramic module, >like how big it is and what kind of components you put on it, if that's >not proprietary. Some of it is quite proprietary, NDA and all that. But the process is not proprietary. There are a number of fabs, among them National Semiconductor: http://www.national.com/appinfo/ltcc/0,2583,364,00.html This particular module has flip-chip ASICs on one side and the other side will have micro-machinery added, yes, moving parts.... The design requires using vias at closest spacing, so no tracks between vias in substantial areas of the module. Because the module must be designed for more than one fab, the design must meet worst-case design rules, which in this case are 2 mil track and space and 4 mil vias, with 12 mil space between vias (the via sizes do not include catchpad, otherwise it would seem that you could put track between them. No.) Because the ASICS are basically BGAs at spacings inadequate for track between vias, routing is severely constrained and reassignment of gates and drivers was necessary to create a routable design, even with 21 layers. The module is 34 mm wide by 127 mm long maximum, i.e., 5 inches. So I could work, if necessary, at 10X scale. There were certain aspects of this job which show the power of the Protel spreadsheet for creating complex patterns, I've thought of writing an article about it. However, the design also made very blatant a major bug with blind and buried vias, that they display on layers where they do not exist. Fortunately, this design turns out to be conceptually easy to understand; otherwise it would have been a nightmare and I would have had to move it to another CAD system that properly handles blind/buried vias. Right now I consider the blind/buried via display problem the worst outstanding issue.... A workaround would be to create a pad stack using pads co-incident with the via, then suppress the via display. But in this case the database would become truly huge, it is already a bit cumbersome to work with, one reason I am now assembling a faster computer. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://email@example.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *