I just ran into this, Michael. What worked for me was to use the "Place Track" command to create a tag trace with no net name, then dropped a Via on it. Apparently the DRC sees it as copper with No Net, connected to a via with No Net. Expansions and Spacing rules continue to be observed.
Hope it works for you.... Brian At 05:47 PM 4/25/02 -0500, you wrote: >I am working with a design that has a large FBGA and each pad on this part >has a via fanout from it. Not all the pads are assigned a net name on this >FBGA. The pins that are not used have no net name and therefore the pad has >no net name but I am still giving it a fan out with a small connection to >it, incase I ever need to use it. The problem is the design rules flags all >these. My question is there any way around this or a design rule I can set >up that will not show these no net name fanouts/connections as a violation? >Thanks for anyones comments, >Michael Biggs > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
