> -----Original Message-----
> From: Ian Wilson [mailto:[EMAIL PROTECTED]]
> Sent: Sunday, 11 August 2002 8:24 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] P99SE lockups
>
>
> On 07:48 PM 11/08/2002 +0800, Katinka Mills said:
> >Hi all,
> >
> >I am just starting to have problems with P99SE, I have a design, it is a
> >simple 2 layer board, but it is having problems :
> >
> >#1 Auto Routing crashes protel on this design. (Access violation)
> >
> >#2 Routing one net at a time, causes the entire board to be routed and
> >crashes protel. (Acess violation) Not sure why it does the whole
> board when
> >all I asked it to do was one board.
> >
> >Also does anyone know how to panalise in P99SE (not a gerber as
> the fab shop
> >wants it in P99SE format, but I have to panalise the 2 designs)
> I tried to
> >make an outine of the panel and then cut and paste the PCB's in
> the panel,
> >but all my component ID's change eg R4 may be come R4_3_1 etc.
> >
> >Regards,
> >
> >Kat.
>
>
> #2 There is a problem with P99SE router it only seems to do
> Autoroute-All,
> in my experience anyway. I have never seen it or heard of it routing any
> single net or region or anything but Autoroute-All.
>
> #1 - Is there a contiguous outline on the keepout layer, made only from
> straight lines (no arcs). This keepout outline should have the
> ends of the
> line segments exactly coincident at the vertices. There is some help in
> the Protel KB dealing with the fussiness of the autorouter. Not sure it
> deals with crashes but there may be something there.
Yeap. checked that :o)
> Panelising in P99SE is possible - I have done it heaps of time but these
> days I try not to do it anymore.
>
> To overcome the designators changing you use Paste-Special and then check
> the desired options (there is one that allows you to keep the designators
> unchanged - forgotten the exact wording).
>
> But this is only the first of the things you have to consider:
> 1) Once panelised DRC is not hugely useful
> 2) The design is harder to change
> 3) ...
Not a problem as I have the two seperate Jobs in their own ddb's just made a
temp ddb for the panel :o)
> What I now tend to do is lay up the panel (on Mechanical Layer 1) in full
> detail including breakoff strips and production strips, showing the
> locations of all the boards in the panel. I include step-and-repeat
> dimensions on another mech layer.
>
> I design the board in one of the board outlines and then supply
> the design
> to the PCB maker, in that form, with clear instructions on
> step-and-repeat.
>
> I leave the actual step-and-repeat (sometimes including a rotation for
> packing odd-shaped boards) to be done by the board house.
They have specifically asked us to do it (cheap skates lol)
> When I am providing Gerbers I may do the actual step-and-repeat
> myself but
> more often than not I also leave it to the board house.
>
> Ian Wilson
Thanks for the prompt reply will try it shortly :o)
Regards,
Kat.
**********************************************
K.A.Q. Electronics.
Electronic and Software Engineering.
Perth, Western Australia.
Ph +61 (0) 419 923 731
**********************************************
---
Outgoing mail is certified Virus Free.
Checked by AVG anti-virus system (http://www.grisoft.com).
Version: 6.0.381 / Virus Database: 214 - Release Date: 2/08/2002
************************************************************************
* Tracking #: C0A2552DC6DA0044831E21F8F331DA5667E94A3D
*
************************************************************************
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave this list visit:
* http://www.techservinc.com/protelusers/leave.html
*
* Contact the list manager:
* mailto:[EMAIL PROTECTED]
*
* Forum Guidelines Rules:
* http://www.techservinc.com/protelusers/forumrules.html
*
* Browse or Search previous postings:
* http://www.mail-archive.com/proteledaforum@techservinc.com
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
