Kat, one method that has worked well for me is to make a main schematic
sheet that includes a sub-sheet block for each of the panels.  then create
the first subsheet from the original circuit, and each of the additional
panels as copy/paste from the first.  Now the designators for each part of
the original have to have added to them _1 for the first copy, _2 for the
second and so on.  That is the only tedious part and quite easy to do if you
put the _1 in the keyboard past buffer, for example and just drop it onto
the ends of the designators.  With this complete you can create a netlist
that is valid for the DRC and for the IMPORTANT "update primitives from
connected copper" operation you will do on the PCB later.

Now starting with you original PCB layout, expand the mech layer and keepout
to the desired size.  Then lasso select the original circuit, copy it and
the paste it (step and repeat fashion) as many times as you need.  You will
notice that the designators on the new copies are automatically being
changed to have the _1, _2, _3 suffixes.  thank goodness something is

Now go to "Design/Netlist Manager/Menu/update primitives from connected
copper".  this will adjust the nets for all of the traces to match the new
designators of each of the panelized circuits.

The hardest part of this is mastering the arcane way of duplicating the
schematic sub sheets in the first place.  the key there is the mysterious
operation that "Flattens" the hierarchy".  that's the "Complex to Simple"
command from the Schematic Tools menu.  If you get the filenames matched up
correctly in your sub-sheet references on the main sheet, the sub sheets
will hop onto the Explorer list correctly under the main sheet.  I can only
say to experiment with this until it works - it actually does work.

I know this is a vague off the top of head description but I hope it gets
the general idea across.

Tim Hutcheson.

-----Original Message-----
From: Katinka Mills [mailto:[EMAIL PROTECTED]]
Sent: Sunday, August 11, 2002 6:48 AM
To: Protel EDA Forum
Subject: [PEDA] P99SE lockups

Hi all,

I am just starting to have problems with P99SE, I have a design, it is a
simple 2 layer board, but it is having problems :

#1 Auto Routing crashes protel on this design. (Access violation)

#2 Routing one net at a time, causes the entire board to be routed and
crashes protel. (Acess violation) Not sure why it does the whole board when
all I asked it to do was one board.

Also does anyone know how to panalise in P99SE (not a gerber as the fab shop
wants it in P99SE format, but I have to panalise the 2 designs) I tried to
make an outine of the panel and then cut and paste the PCB's in the panel,
but all my component ID's change eg R4 may be come R4_3_1 etc.



K.A.Q. Electronics.
Electronic and Software Engineering.
Perth, Western Australia.
Ph +61 (0) 419 923 731
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