Clive,
I gave up after about ten tries on the matched length,
just figured it did not work. It did add some
serpentine, but again after about ten tries the lenghts
were still not even close to being matched.
Seems kind of rediculous to have to run it
multiple times? It should do it in one shot in my mind.
Bob Wolfe
----- Original Message -----
From: <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Tuesday, August 13, 2002 6:36 PM
Subject: Re: [PEDA] Matched Lenghth Constraint


>
>
> Matched length works very well.
> To implement the equalize netlengths feature, you have to define a
netclass with
> the nets you want to equalize.
> Then go to Design Rules/High Speed/Matched Length and set the attributes.
> Depending
> on how much room on the board you have, set the amplitude and gap for the
> largest that
> can be fitted.
> Then run Tools/Equalize Net Length a couple of times to progressivly add
> sections.
>
> Usually a couple of runs are required as Protel only 'adds' 1 section at a
time.
> It works out which net in the netclass is the longest and adds sections to
the
> other
> nets to bring them up. The amplitude and gap can be reduced in later runs
to
> have
> a finer tolarence.
> You can then do a DRC to check the lengths. DRC takes the shortest
track/net in
> the netclass
> and compares the other nets to it
>
>
>
>
>
>
>
> "Robert M. Wolfe" <[EMAIL PROTECTED]> on 08/13/2002 10:55:53 PM
>
> Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]>
>
> To:   "Protel EDA Forum" <[EMAIL PROTECTED]>
> cc:    (bcc: Clive Broome/sdc)
>
> Subject:  Re: [PEDA] Matched Lenghth Constraint
>
>
>
> Well ADEEL,
> I am afraid that to actually have the system (99SE, don't
> know about DXP) match these leghts it will not do it,
> I was told any auto-router function, and this is one
> will not ahere to these rules. I tried it a few times where
> there was plenty of room to match the lengths
> of a delay loop and they were not even close
> so eneded up having to manually route these.
> I would also love to hear if there was a way in 99SE
> to get the system to match these lengths.
> Bob Wolfe
> ----- Original Message -----
> From: "Adeel Malik" <[EMAIL PROTECTED]>
> To: "Protel EDA Forum" <[EMAIL PROTECTED]>
> Sent: Tuesday, August 13, 2002 9:36 AM
> Subject: [PEDA] Matched Lenghth Constraint
>
>
> > Hi All,
> >          I want to apply a matched-length constraint to the signals
> > connected to the bus. In the Protel Design Rule dialog, there are mainly
2
> > parameters to specify, one is Tolerance (whose purpose is obvious) and
the
> > other is Connection style. In connection style there are three options
1)
> 90
> > degree 2) 45 degree and 3) Rounded. Alongwith them there are also
options
> of
> > Amplitude and Gap.I couldn't understand these options so Can someone
tell
> me
> > how these options are utilized effectively while routing a bus running
at
> > 66MHz.
> >
> > Regards,
> > ADEEL MALIK
> >
> >
> >
> > ************************************************************************
> > * Tracking #: 0E65D282D6969F409D601E4E0E422F8499FF2F09
> > *
> > ************************************************************************
> >
> >
>
>
>
>
>
>
>
>


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