It was through-hole.
> -----Original Message----- > From: Rob Young [mailto:[EMAIL PROTECTED]] > Sent: Saturday, August 31, 2002 12:47 AM > To: Protel EDA Forum > Subject: Re: [PEDA] Service Pack 7 vs DXP issues > > > Tony, > I meant to add to my last post that my observations on the > sample boards were from the Altium SMT versions. One is a > rather mediocre board that was done with 8 layers and no > planes so the power and ground were routed in with the > signals. This could account for the poor power and ground > routes. The other board was the benchmark board and while it > did look better, it still had some problems as well. I have > copied my previous post to the DXP forum below for reference. > As more people who have used Situs post their comments on > their experiences as you did, it will be helpful in > understanding if Situs is better or not on large SMT boards. > You mentioned that your board was a simple two layer board. > Was it surface mount or through hole? My autorouting > experience with through-hole designs has always been good, > but that is not where the majority of the work is these days > for me. Most of the boards I get these days are double sided > surface mount designs that are fairly dense. The autorouter > just doesn't do a good enough job for me on such projects. > With all the fanfare from Altium about Situs, I was looking > forward to something better than what I saw. > ------------------------------- > Previous message posted to DXP forum: > I admit I have only tried the autorouter with minimal > training with disastrous results but I thought that was > probably my ignorance in setting it up properly. I then went > to load the demo boards that came with DXP and viewed the > surface mount designs autorouted by Altium to see what > someone who knows how to use Situs could produce. > > Rather than describe what I found, I will just point to a few > areas out of > several: > Project: C:\Program Files\Altium\Examples\PCB > Auto-Routing\PCB Auto-Routing.PrjPCB (open the SMT board) 1. > GND routing on bottom layer between R288 & R31 2. VDD > routing on bottom layer at C140 3. 8 layers and no power > planes? 4. GND routing near U2 pin 34 5. U94 pin 27 takes > an unnecessarily long path to it's destination. 6. VDD > routing near C60 7. Numerous acid traps throughout the design. > > Project: C:\Program Files\Altium\Examples\PCB Benchmark\PCB > Benchmark.pcbdoc 8. routing of R435 pin 2 9. routing of U16 > pins 38 & 40 to R336 pin 2. 10. U59 pin 13 & pin 12. In > general "PCB Benchmark.pcbdoc" is better than the "PCB > Auto-Routing.PrjPCB" but there are still several areas that > need improvement. > > If this is the best that a trained Situs user can produce, I > am not impressed at all. I wonder what the yields of these > designs would be in a real production environment. ************************************************************************ * Tracking #: 722E03AFE9B4FA43BD256DCCA2CE5DC3B297AE18 * ************************************************************************ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
