Re: [PEDA] Altium preps topological autorouter

Mike You are right. But does this "Integrated" library sound like a "copy" of Pads? You know the "all-in-one library", that can"t be used. Of course the "Manager" concept comes from Accel, oh yeah. Sounds like a staight marketing scheme. Bob Fearon

Re: [PEDA] Database Repair

nt back to old copies of the pcb file until I found the culprit. It was a copper pour. The settings were too small a track size. Hope this helps, Bob Fearon Jeff Adolphs wrote: > Hello! I'm the one having Protel Crashes with the message 'Access > violation I have read the Prote

Re: [PEDA] Exporting a schematic as a simple jpg, bmp, gif, etc.

Hi Ray I have had some success writing these (schematics) out as PDF's. I have not tried to put them back into a word or text document. I have also used various other "paint" programs to capture the schematics to use as partials in rework drawings. It can be done. B

Re: [PEDA] Pricing

Brad Now where have I heard that before? Bob Brad Velander wrote: > Rob, > try my quandry, 5 licenses and a bunch of rogue engineers who care > not about licenses, support or anything else as long as they can get a > design out the door. If they can't get the design out the door the

Re: [PEDA] keepoutlayer and planes ??

Guts Sorry to mislead, the additional cost came from routing the boards out of the panels and then plating. Mindful that edgr plating is not a "linear" or accurate as standard thru hole plating. Bob Fearon Brad Velander wrote: > My 2 cents worth, since we do th

Re: [PEDA] Chip & Wire

Sean I have used Protel for "Chip and Wire", but it was Ver 2.8. If you can use that out date info, contact me off-forum. Bob Fearon Sean James wrote: > Has anybody attempted to do chip & wire (hybrid layouts) with Protel? > > Sean James > PCB Designer >

Re: [PEDA] keepoutlayer and planes ??

. This was a nightmare to build and cost "extra". The same performance was achieved by placing a row of vias 100 mils from the edge on a "regular" board, at a much lower cost. Bob Fearon Abd ul-Rahman Lomax wrote: > At 05:32 PM 11/8/01 -0500, Mike Reagan wrote:

[PEDA] Pcb jobs

Hi Just got the word, I have been set adrift again. ( enemployed) If any one knows of a warm place, that needs a body, please notify. Thanks Bob Fearon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto

Re: [PEDA] More help

you use the solder side if you have holes in the board, or the drill files will not generate without extra work. Bob Fearon Ben Uytenhaak wrote: > >Hi again, how can i create a PCB WIZARD with only one layer?? I've > >Protel 99 SE > > Mariano, > > As far as I know

Re: [PEDA] Pad with multiple holes surrounding it.

layers are planes connected to different screw terminals, scrap the board. I use this a lot on switch mode power supplies. Bob Fearon Brad Velander wrote: > Abd ul-Rahman or others, > if I read his description correctly he is trying to do a plated > mounting hole with a

Re: [PEDA] SV: Unplated SMD-pads??

They should show up on the screen as a different color ( multilayer color) instead of top layer or bottom layer. Tommy kesson wrote: > Okej, perhaps... But how do I find them? > > Tommy > > -Ursprungligt meddelande----- > Fr n: Bob Fearon [mailto:[EMAIL PROTECTED]]

Re: [PEDA] Unplated SMD-pads??

Tommy Do you have any of your SMD pads set as multilayer? I have only seen this message when I made that mistake. Bob Tommy kesson wrote: > Sometime then I do DRC I get an error message. > "Broken-nets contraint" > Net GND > Warning nets constain unpladet pads. > > How do I find this u

Re: [PEDA] Drawing polygons that contain arcs, is more control possible?

Brad I have tried "keepout arcs" on the same layer as the polygon. Bob Brad Velander wrote: > Hi all, > one of our engineers just stumped me with a question regarding using > arcs in a polygon outline. Has anybody ever found a method to better control > arcs when drawing polygon outl

[PEDA] [PROTEL EDA USERS]: To ERC Or Not To ERC (an aside to"newbie can't get power...")

let's try to be done in 40 hours. " It took 25 hours to make his netlist come out right. A proper ERC would have caught this for the engineer. And saved his "face". ( proper body part ) Bob Fearon PS With today's speed of computers, it just take a minute. * *

Re: [PEDA] [PROTEL EDA USERS]: Relief on Vias

have high current concerns. Just a thought to get you thinking in a new direction. Bob Fearon Kirk Haderlie wrote: > I should clarify the issue. The problem is that we are using two GND planes > and GND polygon fills top and bottom. Soldering GND pads is very > difficult(soldering i

[PEDA] [PROTEL EDA USERS]: Problems with Access Jet engine

we get that all the time, but I don't know what it is." Thanks in advance for any ideas. Bob Fearon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the "reply" command in your email p