[gem5-dev] Change in gem5/gem5[master]: testlib: No catch of custom exceptions in sandbox

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/12167 )


Change subject: testlib: No catch of custom exceptions in sandbox
..

testlib: No catch of custom exceptions in sandbox

Custom exceptions are not always properly pickled which could lead to
the sandbox test executor to crash when it tries to re __init__ pickled
exceptions thrown from the failed test.

Change-Id: I4e2ffe5802dda668b5d61c5a16e0989717121a04
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/12167
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M ext/testlib/sandbox.py
1 file changed, 6 insertions(+), 8 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/ext/testlib/sandbox.py b/ext/testlib/sandbox.py
index 7f8fe2d..49fe133 100644
--- a/ext/testlib/sandbox.py
+++ b/ext/testlib/sandbox.py
@@ -133,18 +133,16 @@


 class SubprocessException(Exception):
-def __init__(self, exception, trace):
+def __init__(self, trace):
 super(SubprocessException, self).__init__(trace)

 class ExceptionProcess(multiprocessing.Process):
-class Status():
+class Status(object):
 def __init__(self, exitcode, exception_tuple):
 self.exitcode = exitcode
 if exception_tuple is not None:
-self.trace = exception_tuple[1]
-self.exception = exception_tuple[0]
+self.trace = exception_tuple[0]
 else:
-self.exception = None
 self.trace = None

 def __init__(self, *args, **kwargs):
@@ -156,9 +154,9 @@
 try:
 super(ExceptionProcess, self).run()
 self._cconn.send(None)
-except Exception as e:
+except Exception:
 tb = traceback.format_exc()
-self._cconn.send((e, tb))
+self._cconn.send((tb, ))
 raise

 @property
@@ -186,7 +184,7 @@

 status = self.p.status
 if status.exitcode:
-raise SubprocessException(status.exception, status.trace)
+raise SubprocessException(status.trace)

 def entrypoint(self):
 self.io_manager.setup()

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I4e2ffe5802dda668b5d61c5a16e0989717121a04
Gerrit-Change-Number: 12167
Gerrit-PatchSet: 2
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sean Wilson 
Gerrit-Reviewer: Sean Wilson 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: testlib: No catch of custom exceptions in sandbox

[Sean Wilson (Gerrit)]

Hello Sean Wilson,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/12167

to review the following change.


Change subject: testlib: No catch of custom exceptions in sandbox
..

testlib: No catch of custom exceptions in sandbox

Custom exceptions are not always properly pickled which could lead to
the sandbox test executor to crash when it tries to re __init__ pickled
exceptions thrown from the failed test.

Change-Id: I4e2ffe5802dda668b5d61c5a16e0989717121a04
Signed-off-by: Sean Wilson 
---
M ext/testlib/sandbox.py
1 file changed, 6 insertions(+), 8 deletions(-)



diff --git a/ext/testlib/sandbox.py b/ext/testlib/sandbox.py
index 7f8fe2d..49fe133 100644
--- a/ext/testlib/sandbox.py
+++ b/ext/testlib/sandbox.py
@@ -133,18 +133,16 @@


 class SubprocessException(Exception):
-def __init__(self, exception, trace):
+def __init__(self, trace):
 super(SubprocessException, self).__init__(trace)

 class ExceptionProcess(multiprocessing.Process):
-class Status():
+class Status(object):
 def __init__(self, exitcode, exception_tuple):
 self.exitcode = exitcode
 if exception_tuple is not None:
-self.trace = exception_tuple[1]
-self.exception = exception_tuple[0]
+self.trace = exception_tuple[0]
 else:
-self.exception = None
 self.trace = None

 def __init__(self, *args, **kwargs):
@@ -156,9 +154,9 @@
 try:
 super(ExceptionProcess, self).run()
 self._cconn.send(None)
-except Exception as e:
+except Exception:
 tb = traceback.format_exc()
-self._cconn.send((e, tb))
+self._cconn.send((tb, ))
 raise

 @property
@@ -186,7 +184,7 @@

 status = self.p.status
 if status.exitcode:
-raise SubprocessException(status.exception, status.trace)
+raise SubprocessException(status.trace)

 def entrypoint(self):
 self.io_manager.setup()

--
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Gerrit-Change-Id: I4e2ffe5802dda668b5d61c5a16e0989717121a04
Gerrit-Change-Number: 12167
Gerrit-PatchSet: 1
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Sean Wilson 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: tests: Add explicit build test

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded a new patch set (#8) to the change originally  
created by Jason Lowe-Power. (  
https://gem5-review.googlesource.com/c/public/gem5/+/10121 )


Change subject: tests: Add explicit build test
..

tests: Add explicit build test

Change-Id: Ia613ab580b880a463c9cf0dd63f61497db31fe75
Signed-off-by: Jason Lowe-Power 
---
A tests/gem5/test_build/test_build.py
1 file changed, 55 insertions(+), 0 deletions(-)


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Gerrit-Branch: master
Gerrit-Change-Id: Ia613ab580b880a463c9cf0dd63f61497db31fe75
Gerrit-Change-Number: 10121
Gerrit-PatchSet: 8
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sean Wilson 
Gerrit-CC: Brandon Potter 
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[gem5-dev] Change in gem5/gem5[master]: tests: Add a simple example test

[Sean Wilson (Gerrit)]

Hello Anthony Gutierrez, Jason Lowe-Power, Brandon Potter,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/4422

to look at the new patch set (#17).

Change subject: tests: Add a simple example test
..

tests: Add a simple example test

Change-Id: I0753db61d6344b9ed95c0d90a1ab097de7e2af12
Signed-off-by: Sean Wilson 
---
A tests/gem5/hello_se/ref/simerr
A tests/gem5/hello_se/ref/simout
A tests/gem5/hello_se/test_hello_se.py
3 files changed, 65 insertions(+), 0 deletions(-)


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Gerrit-Change-Id: I0753db61d6344b9ed95c0d90a1ab097de7e2af12
Gerrit-Change-Number: 4422
Gerrit-PatchSet: 17
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Brandon Potter 
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[gem5-dev] Change in gem5/gem5[master]: tests: Add documentation for new testing code

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded a new patch set (#17) to the change originally  
created by Jason Lowe-Power. (  
https://gem5-review.googlesource.com/c/public/gem5/+/4882 )


Change subject: tests: Add documentation for new testing code
..

tests: Add documentation for new testing code

Change-Id: Id62ad8e452e640073079e76c9ce5898cedee
Signed-off-by: Jason Lowe-Power 
Signed-off-by: Sean Wilson 
---
M CONTRIBUTING.md
A TESTING.md
2 files changed, 218 insertions(+), 7 deletions(-)


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Gerrit-Project: public/gem5
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Gerrit-Change-Id: Id62ad8e452e640073079e76c9ce5898cedee
Gerrit-Change-Number: 4882
Gerrit-PatchSet: 17
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[master]: tests, ext: Add a new testing library proposal

[Sean Wilson (Gerrit)]

Hello Gabe Black, Anthony Gutierrez, Jason Lowe-Power, Giacomo Travaglini,  
Andreas Sandberg,


I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/4421

to look at the new patch set (#16).

Change subject: tests,ext: Add a new testing library proposal
..

tests,ext: Add a new testing library proposal

The new test library is split into two parts: The framework which resides
in ext/, and the gem5 helping components in /tests/gem5.

Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9
Signed-off-by: Sean Wilson 
---
A ext/testlib/__init__.py
A ext/testlib/config.py
A ext/testlib/fixture.py
A ext/testlib/handlers.py
A ext/testlib/helper.py
A ext/testlib/loader.py
A ext/testlib/log.py
A ext/testlib/main.py
A ext/testlib/query.py
A ext/testlib/result.py
A ext/testlib/runner.py
A ext/testlib/sandbox.py
A ext/testlib/state.py
A ext/testlib/suite.py
A ext/testlib/terminal.py
A ext/testlib/test.py
A ext/testlib/uid.py
A ext/testlib/wrappers.py
A tests/.gitignore
A tests/gem5/__init__.py
A tests/gem5/fixture.py
A tests/gem5/suite.py
A tests/gem5/verifier.py
A tests/legacy-configs/run.py
A tests/main.py
25 files changed, 4,937 insertions(+), 0 deletions(-)


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Gerrit-Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9
Gerrit-Change-Number: 4421
Gerrit-PatchSet: 16
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[master]: tests: Add test for the m5-exit instruction.

[Sean Wilson (Gerrit)]

Hello Anthony Gutierrez, Jason Lowe-Power, Brandon Potter,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/4423

to look at the new patch set (#17).

Change subject: tests: Add test for the m5-exit instruction.
..

tests: Add test for the m5-exit instruction.

Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63
Signed-off-by: Sean Wilson 
---
A tests/gem5/m5_util/test_exit.py
A tests/test-progs/m5-exit/.gitignore
A tests/test-progs/m5-exit/src/Makefile.x86
A tests/test-progs/m5-exit/src/m5-exit.c
M util/m5/Makefile.x86
5 files changed, 99 insertions(+), 1 deletion(-)


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Gerrit-Branch: master
Gerrit-Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63
Gerrit-Change-Number: 4423
Gerrit-PatchSet: 17
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: tests/ext: Add a new testing library proposal

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4421

to look at the new patch set (#9).

Change subject: tests/ext: Add a new testing library proposal
..

tests/ext: Add a new testing library proposal

The new test library is split into two parts: The framework which resides
in ext/, and the gem5 helping components in /tests/gem5.

Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9
Signed-off-by: Sean Wilson 
---
A ext/testlib/FILES.rst
A ext/testlib/__init__.py
A ext/testlib/config.py
A ext/testlib/fixture.py
A ext/testlib/helper.py
A ext/testlib/loader.py
A ext/testlib/logger.py
A ext/testlib/main.py
A ext/testlib/query.py
A ext/testlib/result.py
A ext/testlib/runner/__init__.py
A ext/testlib/runner/parallel.py
A ext/testlib/runner/runner.py
A ext/testlib/suite.py
A ext/testlib/tee.py
A ext/testlib/terminal.py
A ext/testlib/test.py
A ext/testlib/uid.py
A ext/testlib/util.py
A tests/.gitignore
A tests/credentials.ini
A tests/gem5/__init__.py
A tests/gem5/fixture.py
A tests/gem5/suite.py
A tests/gem5/verifier.py
A tests/legacy-configs/run.py
A tests/main.py
27 files changed, 4,903 insertions(+), 0 deletions(-)


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Gerrit-Change-Number: 4421
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Gerrit-CC: Rahul Thakur 
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[gem5-dev] Change in public/gem5[master]: tests: Add a simple example test

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4422

to look at the new patch set (#8).

Change subject: tests: Add a simple example test
..

tests: Add a simple example test

Change-Id: I0753db61d6344b9ed95c0d90a1ab097de7e2af12
Signed-off-by: Sean Wilson 
---
A tests/gem5/hello_se/ref/simerr
A tests/gem5/hello_se/ref/simout
A tests/gem5/hello_se/test_hello_se.py
3 files changed, 37 insertions(+), 0 deletions(-)


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[gem5-dev] Change in public/gem5[master]: tests/ext: Add a new testing library proposal

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4421

to look at the new patch set (#8).

Change subject: tests/ext: Add a new testing library proposal
..

tests/ext: Add a new testing library proposal

The new test library is split into two parts: The framework which resides
in ext/, and the gem5 helping components in /tests/gem5.

Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9
Signed-off-by: Sean Wilson 
---
A ext/testlib/FILES.rst
A ext/testlib/__init__.py
A ext/testlib/config.py
A ext/testlib/fixture.py
A ext/testlib/helper.py
A ext/testlib/loader.py
A ext/testlib/logger.py
A ext/testlib/main.py
A ext/testlib/query.py
A ext/testlib/result.py
A ext/testlib/runner/__init__.py
A ext/testlib/runner/parallel.py
A ext/testlib/runner/runner.py
A ext/testlib/suite.py
A ext/testlib/tee.py
A ext/testlib/terminal.py
A ext/testlib/test.py
A ext/testlib/uid.py
A ext/testlib/util.py
A tests/.gitignore
A tests/credentials.ini
A tests/gem5/__init__.py
A tests/gem5/fixture.py
A tests/gem5/suite.py
A tests/gem5/verifier.py
A tests/legacy-configs/run.py
A tests/main.py
27 files changed, 4,905 insertions(+), 0 deletions(-)


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[gem5-dev] Change in public/gem5[master]: tests: Add Makefiles for hello

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded a new patch set (#8) to the change originally  
created by Jason Lowe-Power. ( https://gem5-review.googlesource.com/4883 )


Change subject: tests: Add Makefiles for hello
..

tests: Add Makefiles for hello

This adds Makefiles for hello for ARM and x86 by leveraging docker and
dockcross. See https://github.com/dockcross/dockcross for more
information.

These Makefiles also allow for automatic uploading to the correct location
for users to download when running the new tests.

Change-Id: I7085000393cd5283502a7af362c85befda749181
Signed-off-by: Jason Lowe-Power 
---
A tests/test-progs/hello/.gitignore
D tests/test-progs/hello/bin/arm/linux/hello
D tests/test-progs/hello/bin/x86/linux/hello
D tests/test-progs/hello/bin/x86/linux/hello32
A tests/test-progs/hello/src/Makefile.arm
A tests/test-progs/hello/src/Makefile.x86
6 files changed, 59 insertions(+), 0 deletions(-)


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Gerrit-Change-Number: 4883
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[gem5-dev] Change in public/gem5[master]: tests/ext: Add a new testing library proposal

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4421

to look at the new patch set (#7).

Change subject: tests/ext: Add a new testing library proposal
..

tests/ext: Add a new testing library proposal

The new test library is split into two parts: The framework which resides
in ext/, and the gem5 helping components in /tests/gem5.

Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9
Signed-off-by: Sean Wilson 
---
A ext/testlib/FILES.rst
A ext/testlib/__init__.py
A ext/testlib/config.py
A ext/testlib/fixture.py
A ext/testlib/helper.py
A ext/testlib/loader.py
A ext/testlib/logger.py
A ext/testlib/main.py
A ext/testlib/query.py
A ext/testlib/result.py
A ext/testlib/runner/__init__.py
A ext/testlib/runner/parallel.py
A ext/testlib/runner/runner.py
A ext/testlib/suite.py
A ext/testlib/tee.py
A ext/testlib/terminal.py
A ext/testlib/test.py
A ext/testlib/uid.py
A ext/testlib/util.py
A tests/.gitignore
A tests/credentials.ini
A tests/gem5/__init__.py
A tests/gem5/fixture.py
A tests/gem5/suite.py
A tests/gem5/verifier.py
A tests/legacy-configs/run.py
A tests/main.py
27 files changed, 4,905 insertions(+), 0 deletions(-)


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[gem5-dev] Change in public/gem5[master]: tests: Add Makefiles for hello

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded a new patch set (#7) to the change originally  
created by Jason Lowe-Power. ( https://gem5-review.googlesource.com/4883 )


Change subject: tests: Add Makefiles for hello
..

tests: Add Makefiles for hello

This adds Makefiles for hello for ARM and x86 by leveraging docker and
dockcross. See https://github.com/dockcross/dockcross for more
information.

These Makefiles also allow for automatic uploading to the correct location
for users to download when running the new tests.

Change-Id: I7085000393cd5283502a7af362c85befda749181
Signed-off-by: Jason Lowe-Power 
---
A tests/test-progs/hello/.gitignore
D tests/test-progs/hello/bin/arm/linux/hello
D tests/test-progs/hello/bin/x86/linux/hello
D tests/test-progs/hello/bin/x86/linux/hello32
A tests/test-progs/hello/src/Makefile.arm
A tests/test-progs/hello/src/Makefile.x86
6 files changed, 56 insertions(+), 0 deletions(-)


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Gerrit-Change-Id: I7085000393cd5283502a7af362c85befda749181
Gerrit-Change-Number: 4883
Gerrit-PatchSet: 7
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sean Wilson 
Gerrit-CC: Gabe Black 
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[gem5-dev] Change in public/gem5[master]: tests: Add a simple example test

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4422

to look at the new patch set (#7).

Change subject: tests: Add a simple example test
..

tests: Add a simple example test

Change-Id: I0753db61d6344b9ed95c0d90a1ab097de7e2af12
Signed-off-by: Sean Wilson 
---
A tests/gem5/example/ref/simerr
A tests/gem5/example/ref/simout
A tests/gem5/example/test_basic_example.py
3 files changed, 37 insertions(+), 0 deletions(-)


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Gerrit-Change-Id: I0753db61d6344b9ed95c0d90a1ab097de7e2af12
Gerrit-Change-Number: 4422
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Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: tests/ext: Add a new testing library proposal

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4421

to look at the new patch set (#5).

Change subject: tests/ext: Add a new testing library proposal
..

tests/ext: Add a new testing library proposal

The new test library is split into two parts: The framework which resides
in ext/, and the gem5 helping components in /tests/gem5.

Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9
Signed-off-by: Sean Wilson 
---
A ext/testlib/FILES.rst
A ext/testlib/__init__.py
A ext/testlib/_util.py
A ext/testlib/config.py
A ext/testlib/fixture.py
A ext/testlib/helper.py
A ext/testlib/loader.py
A ext/testlib/logger.py
A ext/testlib/main.py
A ext/testlib/query.py
A ext/testlib/result.py
A ext/testlib/runner/__init__.py
A ext/testlib/runner/parallel.py
A ext/testlib/runner/runner.py
A ext/testlib/suite.py
A ext/testlib/tee.py
A ext/testlib/terminal.py
A ext/testlib/test.py
A ext/testlib/uid.py
A tests/.gitignore
A tests/credentials.ini
A tests/gem5/__init__.py
A tests/gem5/fixture.py
A tests/gem5/suite.py
A tests/gem5/verifier.py
A tests/legacy-configs/run.py
A tests/main.py
27 files changed, 4,869 insertions(+), 0 deletions(-)


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Gerrit-Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9
Gerrit-Change-Number: 4421
Gerrit-PatchSet: 5
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Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-CC: Rahul Thakur 
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[gem5-dev] Change in public/gem5[master]: tests: Add documentation for new testing code

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded a new patch set (#5) to the change originally  
created by Jason Lowe-Power. ( https://gem5-review.googlesource.com/4882 )


Change subject: tests: Add documentation for new testing code
..

tests: Add documentation for new testing code

Change-Id: Id62ad8e452e640073079e76c9ce5898cedee
Signed-off-by: Jason Lowe-Power 
---
M CONTRIBUTING.md
A TESTING.md
2 files changed, 193 insertions(+), 7 deletions(-)


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Gerrit-Change-Id: Id62ad8e452e640073079e76c9ce5898cedee
Gerrit-Change-Number: 4882
Gerrit-PatchSet: 5
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sean Wilson 
Gerrit-CC: adsf asdf 
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[gem5-dev] Change in public/gem5[master]: tests: Add a simple example test

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/4422



Change subject: tests: Add a simple example test
..

tests: Add a simple example test

Change-Id: I0753db61d6344b9ed95c0d90a1ab097de7e2af12
Signed-off-by: Sean Wilson 
---
A tests/gem5/example/ref/X86/linux/se-default/simout
A tests/gem5/example/test_basic_example.py
2 files changed, 32 insertions(+), 0 deletions(-)



diff --git a/tests/gem5/example/ref/X86/linux/se-default/simout  
b/tests/gem5/example/ref/X86/linux/se-default/simout

new file mode 100644
index 000..109b754
--- /dev/null
+++ b/tests/gem5/example/ref/X86/linux/se-default/simout
@@ -0,0 +1,8 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+
+Global frequency set at 1 ticks per second
+ REAL SIMULATION 
+Hello world!
+Exiting @ tick 5891000 because exiting with last active thread context
diff --git a/tests/gem5/example/test_basic_example.py  
b/tests/gem5/example/test_basic_example.py

new file mode 100644
index 000..ae88378
--- /dev/null
+++ b/tests/gem5/example/test_basic_example.py
@@ -0,0 +1,24 @@
+'''
+Test file for the util m5 exit assembly instruction.
+'''
+from testlib import *
+
+ref_path = joinpath(getcwd(), 'ref', 'X86', 'linux', 'se-default')
+
+verifiers = (
+verifier.MatchStdout(joinpath(ref_path, 'simout')),
+
+# The se.py script is dumb and sets a strange return code on  
success.

+verifier.VerifyReturncode(1),
+)
+
+hello_program = TestProgram('hello', 'X86', 'linux')
+
+gem5_verify_config(
+name='test_hello',
+fixtures=(hello_program,),
+verifiers=verifiers,
+config=joinpath(config.base_dir, 'configs', 'example','se.py'),
+config_args=['--cmd', hello_program.path],
+valid_isas=('X86',)
+)

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Gerrit-Change-Id: I0753db61d6344b9ed95c0d90a1ab097de7e2af12
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[gem5-dev] Change in public/gem5[master]: tests: Add test for the m5-exit instruction.

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/4423



Change subject: tests: Add test for the m5-exit instruction.
..

tests: Add test for the m5-exit instruction.

Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63
Signed-off-by: Sean Wilson 
---
A tests/gem5/m5_util/test_exit.py
A tests/test-progs/m5-exit/Makefile
A tests/test-progs/m5-exit/bin/X86/linux/.gitignore
A tests/test-progs/m5-exit/src/.gitignore
A tests/test-progs/m5-exit/src/m5-exit.c
M util/m5/Makefile.x86
6 files changed, 60 insertions(+), 1 deletion(-)



diff --git a/tests/gem5/m5_util/test_exit.py  
b/tests/gem5/m5_util/test_exit.py

new file mode 100644
index 000..d34a7c1
--- /dev/null
+++ b/tests/gem5/m5_util/test_exit.py
@@ -0,0 +1,22 @@
+'''
+Test file for the util m5 exit assembly instruction.
+'''
+import re
+import os
+from testlib import *
+
+m5_exit_regex = re.compile(
+r'Exiting @ tick \d* because m5_exit instruction encountered'
+)
+
+test_program = TestProgram('m5-exit', 'X86', 'linux')
+
+a = verifier.MatchRegex(m5_exit_regex)
+gem5_verify_config(
+name='m5_exit_test',
+verifiers=[a],
+fixtures=(test_program,),
+config=os.path.join(config.base_dir, 'configs', 'example','se.py'),
+config_args=['--cmd', test_program.path],
+valid_isas=('X86',)
+)
diff --git a/tests/test-progs/m5-exit/Makefile  
b/tests/test-progs/m5-exit/Makefile

new file mode 100644
index 000..b5264e9
--- /dev/null
+++ b/tests/test-progs/m5-exit/Makefile
@@ -0,0 +1,16 @@
+M5_UTIL:=${CURDIR}/../../../util/m5
+M5_INCLUDE:=${CURDIR}/../../../include/
+
+# Export CFLAGS so that subMAKEs don't define any flags we don't want.
+CFLAGS=-I ${M5_INCLUDE} -O2
+export CFLAGS
+
+bin/X86/linux/m5-exit: src/m5-exit.c ${M5_UTIL}/m5op_x86.o
+   gcc -DM5 $< ${M5_UTIL}/m5op_x86.o ${CFLAGS} -o $@
+
+${M5_UTIL}/m5op_x86.o:
+   $(MAKE) -C ${M5_UTIL} -f Makefile.x86 m5op_x86.o
+
+clean:
+   rm -f m5-exit m5op.h
+   $(MAKE) -C ${M5_UTIL} -f Makefile.x86 clean
diff --git a/tests/test-progs/m5-exit/bin/X86/linux/.gitignore  
b/tests/test-progs/m5-exit/bin/X86/linux/.gitignore

new file mode 100644
index 000..1bcdf2d
--- /dev/null
+++ b/tests/test-progs/m5-exit/bin/X86/linux/.gitignore
@@ -0,0 +1 @@
+m5-exit
diff --git a/tests/test-progs/m5-exit/src/.gitignore  
b/tests/test-progs/m5-exit/src/.gitignore

new file mode 100644
index 000..65c4e2f
--- /dev/null
+++ b/tests/test-progs/m5-exit/src/.gitignore
@@ -0,0 +1 @@
+m5op.h
\ No newline at end of file
diff --git a/tests/test-progs/m5-exit/src/m5-exit.c  
b/tests/test-progs/m5-exit/src/m5-exit.c

new file mode 100644
index 000..8d8a2b7
--- /dev/null
+++ b/tests/test-progs/m5-exit/src/m5-exit.c
@@ -0,0 +1,19 @@
+#include 
+
+#ifdef M5
+#include "m5op.h"
+
+// If you need to define this, you should have removed the -DM5OP_ADDR
+// when compiling the m5op_x86.o
+//void *m5_mem = (void*)0xCAFEBABE;
+#endif
+
+int main() {
+#ifdef M5
+m5_exit(0);
+#endif
+printf("FAIL!\n");
+printf("Program should have exited due to the magic m5_exit"
+   " instruction!\n");
+return -1;
+}
diff --git a/util/m5/Makefile.x86 b/util/m5/Makefile.x86
index 5ea29cc..e1388c2 100644
--- a/util/m5/Makefile.x86
+++ b/util/m5/Makefile.x86
@@ -31,7 +31,7 @@
 AS=as
 LD=ld

-CFLAGS=-O2 -DM5OP_ADDR=0x -I$(PWD)/../../include
+CFLAGS?=-O2 -DM5OP_ADDR=0x -I$(PWD)/../../include
 OBJS=m5.o m5op_x86.o

 all: m5

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Gerrit-Change-Number: 4423
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[gem5-dev] Change in public/gem5[master]: tests: Restore a legacy atomic test.

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/4424



Change subject: tests: Restore a legacy atomic test.
..

tests: Restore a legacy atomic test.

This commit acts as an example for the process of keeping a legacy
test in this framework.

Change-Id: Ifce9b2ced5bf2984387f48725d827744cbcf2f4d
Signed-off-by: Sean Wilson 
---
A tests/gem5/se/00.hello/ARM/simple-atomic-dummychecker/config.ini
A tests/gem5/se/00.hello/ARM/simple-atomic-dummychecker/simerr
A tests/gem5/se/00.hello/ARM/simple-atomic-dummychecker/simout
A tests/gem5/se/00.hello/ARM/simple-atomic-dummychecker/stats.txt
A tests/gem5/se/00.hello/config.py
A tests/gem5/se/00.hello/test-hello.py
6 files changed, 965 insertions(+), 0 deletions(-)



diff --git  
a/tests/gem5/se/00.hello/ARM/simple-atomic-dummychecker/config.ini  
b/tests/gem5/se/00.hello/ARM/simple-atomic-dummychecker/config.ini

new file mode 100644
index 000..3b9285a
--- /dev/null
+++ b/tests/gem5/se/00.hello/ARM/simple-atomic-dummychecker/config.ini
@@ -0,0 +1,502 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=1000
+time_sync_spin_threshold=1
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem  
voltage_domain

+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+exit_on_work_items=false
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=atomic
+mem_ranges=
+memories=system.physmem
+mmap_using_noreserve=false
+multi_thread=false
+num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1
+p_state_clk_gate_min=1000
+power_model=Null
+readfile=
+symbolfile=
+thermal_components=
+thermal_model=Null
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=checker dstage2_mmu dtb interrupts isa istage2_mmu itb tracer  
workload

+branchPred=Null
+checker=system.cpu.checker
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+default_p_state=UNDEFINED
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1
+p_state_clk_gate_min=1000
+power_model=Null
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+syscallRetryLatency=1
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.checker]
+type=DummyChecker
+children=dstage2_mmu dtb isa istage2_mmu itb tracer
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=-1
+default_p_state=UNDEFINED
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.checker.dstage2_mmu
+dtb=system.cpu.checker.dtb
+eventq_index=0
+exitOnError=false
+function_trace=false
+function_trace_start=0
+interrupts=
+isa=system.cpu.checker.isa
+istage2_mmu=system.cpu.checker.istage2_mmu
+itb=system.cpu.checker.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1
+p_state_clk_gate_min=1000
+power_model=Null
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+syscallRetryLatency=1
+system=system
+tracer=system.cpu.checker.tracer
+updateOnError=false
+warnOnlyOnLoadError=true
+workload=system.cpu.workload
+
+[system.cpu.checker.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu.checker.dtb
+
+[system.cpu.checker.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.checker.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1

[gem5-dev] Change in public/gem5[master]: tests: Remove the old testing system and all tests

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/4420



Change subject: tests: Remove the old testing system and all tests
..

tests: Remove the old testing system and all tests

Change-Id: Iabb24cf8fbada518f6e90f40e644f53f5674be2d
Signed-off-by: Sean Wilson 
---
D tests/SConscript
D tests/configs/alpha_generic.py
D tests/configs/arm_generic.py
D tests/configs/checkpoint.py
D tests/configs/gpu-randomtest-ruby.py
D tests/configs/gpu-ruby.py
D tests/configs/learning-gem5-p1-simple.py
D tests/configs/learning-gem5-p1-two-level.py
D tests/configs/memcheck.py
D tests/configs/memtest-filter.py
D tests/configs/memtest-ruby.py
D tests/configs/memtest.py
D tests/configs/minor-timing-mp.py
D tests/configs/minor-timing.py
D tests/configs/o3-timing-checker.py
D tests/configs/o3-timing-mp-ruby.py
D tests/configs/o3-timing-mp.py
D tests/configs/o3-timing-mt.py
D tests/configs/o3-timing-ruby.py
D tests/configs/o3-timing.py
D tests/configs/pc-o3-timing.py
D tests/configs/pc-simple-atomic.py
D tests/configs/pc-simple-timing-ruby.py
D tests/configs/pc-simple-timing.py
D tests/configs/pc-switcheroo-full.py
D tests/configs/realview-minor-dual.py
D tests/configs/realview-minor.py
D tests/configs/realview-o3-checker.py
D tests/configs/realview-o3-dual.py
D tests/configs/realview-o3.py
D tests/configs/realview-simple-atomic-checkpoint.py
D tests/configs/realview-simple-atomic-dual.py
D tests/configs/realview-simple-atomic.py
D tests/configs/realview-simple-timing-dual-ruby.py
D tests/configs/realview-simple-timing-dual.py
D tests/configs/realview-simple-timing-ruby.py
D tests/configs/realview-simple-timing.py
D tests/configs/realview-switcheroo-atomic.py
D tests/configs/realview-switcheroo-full.py
D tests/configs/realview-switcheroo-o3.py
D tests/configs/realview-switcheroo-timing.py
D tests/configs/realview64-minor-dual.py
D tests/configs/realview64-minor.py
D tests/configs/realview64-o3-checker.py
D tests/configs/realview64-o3-dual.py
D tests/configs/realview64-o3.py
D tests/configs/realview64-simple-atomic-checkpoint.py
D tests/configs/realview64-simple-atomic-dual.py
D tests/configs/realview64-simple-atomic.py
D tests/configs/realview64-simple-timing-dual-ruby.py
D tests/configs/realview64-simple-timing-dual.py
D tests/configs/realview64-simple-timing-ruby.py
D tests/configs/realview64-simple-timing.py
D tests/configs/realview64-switcheroo-atomic.py
D tests/configs/realview64-switcheroo-full.py
D tests/configs/realview64-switcheroo-o3.py
D tests/configs/realview64-switcheroo-timing.py
D tests/configs/rubytest-ruby.py
D tests/configs/simple-atomic-mp-ruby.py
D tests/configs/simple-atomic-mp.py
D tests/configs/simple-atomic.py
D tests/configs/simple-timing-mp-ruby.py
D tests/configs/simple-timing-mp.py
D tests/configs/simple-timing-ruby.py
D tests/configs/simple-timing.py
D tests/configs/switcheroo.py
D tests/configs/t1000-simple-atomic.py
D tests/configs/tgen-dram-ctrl.py
D tests/configs/tgen-simple-mem.py
D tests/configs/tsunami-minor-dual.py
D tests/configs/tsunami-minor.py
D tests/configs/tsunami-o3-dual.py
D tests/configs/tsunami-o3.py
D tests/configs/tsunami-simple-atomic-dual.py
D tests/configs/tsunami-simple-atomic.py
D tests/configs/tsunami-simple-timing-dual.py
D tests/configs/tsunami-simple-timing.py
D tests/configs/tsunami-switcheroo-full.py
D tests/configs/twosys-tsunami-simple-atomic.py
D tests/configs/x86_generic.py
D tests/diff-out
D tests/halt.sh
R tests/legacy-configs/base_config.py
R tests/legacy-configs/simple-atomic-dummychecker.py
D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr
D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout
D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
D  
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal

D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
D tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/EMPTY
D tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
D tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr
D tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
D 

[gem5-dev] Change in public/gem5[master]: cpu, config: Add setFutureCPU to BaseCPU

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4001

to look at the new patch set (#10).

Change subject: cpu, config: Add setFutureCPU to BaseCPU
..

cpu, config: Add setFutureCPU to BaseCPU

To facilitate taking over from a CPU in the future, force users to first
call setFutureCPU before gem5 instantiation. This allows us to be sure
the CPU instantiation that is taken over by the "more_detailed_cpu" has
pointers to the right objects.

Change-Id: I3a3c39a46380e32e2cb18dc8e8304bbc3716f723
Signed-off-by: Jason Lowe-Power 
Signed-off-by: Sean Wilson 
---
M configs/common/Simulation.py
M configs/example/apu_se.py
M src/cpu/BaseCPU.py
M src/python/m5/simulate.py
M tests/configs/base_config.py
M tests/configs/switcheroo.py
6 files changed, 115 insertions(+), 26 deletions(-)


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[gem5-dev] Change in public/gem5[master]: python: Add a function to delete references to a SimObject

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4400

to review the following change.


Change subject: python: Add a function to delete references to a SimObject
..

python: Add a function to delete references to a SimObject

There are times (e.g., in the new TLB switching logic) where you may
want to delete a SimObject. This patch adds a deleteRefs(simobj)
function that ensures that 'simobj' is not referenced by its parent or
by any ports. Additionally, all of the children of simobj will have
their ports cleared as well.

Change-Id: I0e7e3fb9ad2fa9daddb5c63ccca22e43d2e33ad4
Signed-off-by: Jason Lowe-Power 
---
M src/python/m5/SimObject.py
M src/python/m5/params.py
2 files changed, 52 insertions(+), 0 deletions(-)



diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index baeef73..f2dca97 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -1228,6 +1228,20 @@
 child.set_parent(self, name)
 self._children[name] = child

+def removePorts(self):
+"""Iterate through children and make sure there are no ports that  
are
+   going to be connected to this object later. This is used as a  
step

+   in deleting a SimObject that may have been partially setup.
+"""
+for obj in self.descendants():
+if obj != self:
+obj.removePorts()
+
+for port_name in sorted(self._ports.keys()):
+port = self._port_refs.get(port_name, None)
+if port != None:
+port.disconnect()
+
 # Take SimObject-valued parameters that haven't been explicitly
 # assigned as children and make them children of the object that
 # they were assigned to as a parameter value.  This guarantees
@@ -1540,6 +1554,17 @@
 raise TypeError, "SimObject or SimObjectVector expected"
 return value

+def deleteRefs(obj):
+"""Delete references to obj.
+   This function deletes obj from its parent's children and makes sure
+   to remove any dangling port connections.
+"""
+if obj == NULL:
+return
+if obj._parent:
+obj._parent.clear_child(obj.get_name())
+obj.removePorts()
+
 baseClasses = allClasses.copy()
 baseInstances = instanceDict.copy()

@@ -1558,4 +1583,5 @@
 'cxxMethod',
 'PyBindMethod',
 'PyBindProperty',
+'deleteRefs',
 ]
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 776fbe2..3932a12 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -1748,6 +1748,7 @@
 self.name = name
 self.role = role
 self.peer = None   # not associated with another port yet
+self.peerVector = None # Save the vector ref in case it's needed
 self.ccConnected = False # C++ port connection done?
 self.index = -1  # always -1 for non-vector ports

@@ -1781,6 +1782,7 @@
 def connect(self, other):
 if isinstance(other, VectorPortRef):
 # reference to plain VectorPort is implicit append
+self.peerVector = other
 other = other._get_next()
 if self.peer and not proxy.isproxy(self.peer):
 fatal("Port %s is already connected to %s, cannot  
connect %s\n",

@@ -1826,6 +1828,23 @@
 else:
 fatal("Port %s not connected, cannot splice in new peers\n",  
self)


+def disconnect(self):
+"""The opposite of connect. Called from removePorts in SimObject.
+   This will only work if the ports have not been connected via  
C++ and

+   nothing happens if this port is not connected.
+"""
+if self.ccConnected:
+fatal("Cannot disconnect %s. Already connected in C++!" %  
(self))

+if self.peer and not proxy.isproxy(self.peer):
+if isinstance(self.peer, VectorPortElementRef):
+assert(self.peerVector != None)
+# Remove the peer port from the vector its in
+del self.peerVector[self.peer.index]
+# Clear ourselves from the peer vector
+self.peer.peer = None
+# Clear our peer
+self.peer = None
+
 def clone(self, simobj, memo):
 if memo.has_key(self):
 return memo[self]
@@ -1910,6 +1929,13 @@
 # length of the elements.
 return len(self.elements)

+def __delitem__(self, idx):
+"""Delete a port from this port vector."""
+del self.elements[idx]
+# Fix up the indicies
+for i,el in enumerate(self.elements):
+el.index = i
+
 # for config.ini, print peer's name (not ours)
 def ini_str(self):
 return ' '.join([el.ini_str() for el in self.elements])

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[gem5-dev] Change in public/gem5[master]: cpu, config: Add setFutureCPU to BaseCPU

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4001

to look at the new patch set (#9).

Change subject: cpu, config: Add setFutureCPU to BaseCPU
..

cpu, config: Add setFutureCPU to BaseCPU

To facilitate taking over from a CPU in the future, force users to first
call setFutureCPU before gem5 instantiation. This allows us to be sure
the CPU instantiation that is taken over by the "more_detailed_cppu" has
pointers to the right objects.

Change-Id: I3a3c39a46380e32e2cb18dc8e8304bbc3716f723
Signed-off-by: Jason Lowe-Power 
Signed-off-by: Sean Wilson 
---
M configs/common/Simulation.py
M configs/example/apu_se.py
M src/cpu/BaseCPU.py
M src/python/m5/simulate.py
4 files changed, 69 insertions(+), 12 deletions(-)


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Gerrit-Change-Number: 4001
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[gem5-dev] Change in public/gem5[master]: cpu, config: Add setFutureCPU to BaseCPU

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4001

to look at the new patch set (#8).

Change subject: cpu, config: Add setFutureCPU to BaseCPU
..

cpu, config: Add setFutureCPU to BaseCPU

To facilitate taking over from a CPU in the future, force users to first
call setFutureCPU before gem5 instantiation. This allows us to be sure
the CPU instantiation that is taken over by the "more_detailed_cppu" has
pointers to the right objects.

Change-Id: I3a3c39a46380e32e2cb18dc8e8304bbc3716f723
Signed-off-by: Jason Lowe-Power 
Signed-off-by: Sean Wilson 
---
M configs/common/Simulation.py
M configs/example/apu_se.py
M src/cpu/BaseCPU.py
M src/python/m5/simulate.py
4 files changed, 65 insertions(+), 12 deletions(-)


--
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[gem5-dev] Change in public/gem5[master]: cpu, config: Add setFutureCPU to BaseCPU

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4001

to look at the new patch set (#7).

Change subject: cpu, config: Add setFutureCPU to BaseCPU
..

cpu, config: Add setFutureCPU to BaseCPU

To facilitate taking over from a CPU in the future, force users to first
call setFutureCPU before gem5 instantiation. This allows us to be sure
the CPU instantiation that is taken over by the "more_detailed_cppu" has
pointers to the right objects.

Change-Id: I3a3c39a46380e32e2cb18dc8e8304bbc3716f723
Signed-off-by: Jason Lowe-Power 
Signed-off-by: Sean Wilson 
---
M configs/common/Simulation.py
M configs/example/apu_se.py
M src/cpu/BaseCPU.py
M src/python/m5/simulate.py
4 files changed, 62 insertions(+), 12 deletions(-)


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[gem5-dev] Change in public/gem5[master]: cpu, config: Add setFutureCPU to BaseCPU

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4001

to look at the new patch set (#6).

Change subject: cpu, config: Add setFutureCPU to BaseCPU
..

cpu, config: Add setFutureCPU to BaseCPU

To facilitate taking over from a CPU in the future, force users to first
call setFutureCPU before gem5 instantiation. This allows us to be sure
the CPU instantiation that is taken over by the "more_detailed_cppu" has
pointers to the right objects.

Change-Id: I3a3c39a46380e32e2cb18dc8e8304bbc3716f723
Signed-off-by: Jason Lowe-Power 
Signed-off-by: Sean Wilson 
---
M configs/common/Simulation.py
M configs/example/apu_se.py
M src/cpu/BaseCPU.py
3 files changed, 59 insertions(+), 12 deletions(-)


--
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[gem5-dev] Change in public/gem5[master]: cpu, config: Add setFutureCPU to BaseCPU

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4001

to look at the new patch set (#5).

Change subject: cpu, config: Add setFutureCPU to BaseCPU
..

cpu, config: Add setFutureCPU to BaseCPU

To facilitate taking over from a CPU in the future, force users to first
call setFutureCPU before gem5 instantiation. This allows us to be sure
the CPU instantiation that is taken over by the "more_detailed_cppu" has
pointers to the right objects.

Change-Id: I3a3c39a46380e32e2cb18dc8e8304bbc3716f723
Signed-off-by: Jason Lowe-Power 
Signed-off-by: Sean Wilson 
---
M configs/common/Simulation.py
M configs/example/apu_se.py
M src/cpu/BaseCPU.py
3 files changed, 62 insertions(+), 12 deletions(-)


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[gem5-dev] Change in public/gem5[master]: cpu, config: Add setFutureCPU to BaseCPU

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4001

to look at the new patch set (#4).

Change subject: cpu, config: Add setFutureCPU to BaseCPU
..

cpu, config: Add setFutureCPU to BaseCPU

To facilitate taking over from a CPU in the future, force users to first  
call

setFutureCPU before gem5 instantiation. This allows us to be sure the CPU
instantiation that is taken over by the "more_detailed_cppu" has pointers to
the right objects.

Change-Id: I3a3c39a46380e32e2cb18dc8e8304bbc3716f723
Signed-off-by: Jason Lowe-Power 
Signed-off-by: Sean Wilson 
---
M configs/common/Simulation.py
M configs/example/apu_se.py
M src/cpu/BaseCPU.py
3 files changed, 62 insertions(+), 12 deletions(-)


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[gem5-dev] Change in public/gem5[master]: cpu: Use the same TLB pointer for all switching CPUs.

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4002

to look at the new patch set (#4).

Change subject: cpu: Use the same TLB pointer for all switching CPUs.
..

cpu: Use the same TLB pointer for all switching CPUs.

Previously, before a CPU was switched out, the TLB was always flushed.
With this changeset, when you switch from atomic to timing mode the
TLB is warm.

Change-Id: I8413e059d4b75d68f3577512fd7231cfccf461f4
Signed-off-by: Sean Wilson 
---
M src/cpu/base.cc
1 file changed, 0 insertions(+), 67 deletions(-)


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[gem5-dev] Change in public/gem5[master]: cpu: Share branch predictors between swapped CPUs

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/4100 )


Change subject: cpu: Share branch predictors between swapped CPUs
..

cpu: Share branch predictors between swapped CPUs

Change-Id: I0b2f0a3dc0e73f6276ddc75af2051c914f60cae6
---
M src/cpu/BaseCPU.py
1 file changed, 1 insertion(+), 0 deletions(-)


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[gem5-dev] Change in public/gem5[master]: cpu: Share branch predictors between swapped CPUs

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/4100



Change subject: cpu: Share branch predictors between swapped CPUs
..

cpu: Share branch predictors between swapped CPUs

Change-Id: I0b2f0a3dc0e73f6276ddc75af2051c914f60cae6
---
M src/cpu/BaseCPU.py
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 86388aa..2c172c9 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -161,6 +161,7 @@

 self.itb = more_detailed_cpu.itb
 self.dtb = more_detailed_cpu.dtb
+self.branchPred = more_detailed_cpu.branchPred

 def takeOverFrom(self, old_cpu):
 if not self._readyToTakeOver:

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[gem5-dev] Change in public/gem5[master]: sim, x86: Move tlb flush from copyRegs to clone emulation.

[Sean Wilson (Gerrit)]

Hello Gabe Black, Brandon Potter,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4000

to look at the new patch set (#2).

Change subject: sim, x86: Move tlb flush from copyRegs to clone emulation.
..

sim, x86: Move tlb flush from copyRegs to clone emulation.

copyRegs should be idempotent so it can be used for swapping CPUs.
However, clone needs to flush the TLBs since there are no ASIDs in
X86 TLBs, this change moves the flush into the clone system call.

Change-Id: Ic069ca02994436b36246403f9faef80c3aede55a
Signed-off-by: Sean Wilson 
---
M src/arch/x86/utility.cc
M src/sim/syscall_emul.hh
2 files changed, 2 insertions(+), 6 deletions(-)


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[gem5-dev] Change in public/gem5[master]: cpu, config: Add setMainCPU to BaseCPU

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4001

to look at the new patch set (#3).

Change subject: cpu, config: Add setMainCPU to BaseCPU
..

cpu, config: Add setMainCPU to BaseCPU

To facilitate taking over from a CPU in the future, force users to first
call setMainCPU before gem5 instantiation. This allows us to be sure the
CPU instantiation that is taking over from the "main" CPU has pointers to
the right objects.

Change-Id: I3a3c39a46380e32e2cb18dc8e8304bbc3716f723
Signed-off-by: Jason Lowe-Power 
Signed-off-by: Sean Wilson 
---
M configs/common/Simulation.py
M configs/example/apu_se.py
M src/cpu/BaseCPU.py
3 files changed, 62 insertions(+), 12 deletions(-)


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Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I3a3c39a46380e32e2cb18dc8e8304bbc3716f723
Gerrit-Change-Number: 4001
Gerrit-PatchSet: 3
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sean Wilson 
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[gem5-dev] Change in public/gem5[master]: sim, x86: Make clone a virtual function

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3902 )


Change subject: sim, x86: Make clone a virtual function
..

sim, x86: Make clone a virtual function

This fixes the function call to clone in syscall_emul.hh where
the x86 version should be called before the base implementation
of clone.

Change-Id: Iccd2f680ff6e3a5536037d688a80ab3f236bbd98
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3902
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/x86/process.hh
M src/sim/process.hh
2 files changed, 5 insertions(+), 5 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/x86/process.hh b/src/arch/x86/process.hh
index 9cd5378..3eb9620 100644
--- a/src/arch/x86/process.hh
+++ b/src/arch/x86/process.hh
@@ -84,7 +84,7 @@
 void setSyscallReturn(ThreadContext *tc,
   SyscallReturn return_value) override;
 void clone(ThreadContext *old_tc, ThreadContext *new_tc,
-   Process *process, TheISA::IntReg flags);
+   Process *process, TheISA::IntReg flags) override;

 X86Process &
 operator=(const X86Process )
@@ -140,7 +140,7 @@
 void setSyscallArg(ThreadContext *tc, int i,
X86ISA::IntReg val) override;
 void clone(ThreadContext *old_tc, ThreadContext *new_tc,
-   Process *process, TheISA::IntReg flags);
+   Process *process, TheISA::IntReg flags) override;
 };

 class I386Process : public X86Process
@@ -186,7 +186,7 @@
 void setSyscallArg(ThreadContext *tc, int i,
X86ISA::IntReg val) override;
 void clone(ThreadContext *old_tc, ThreadContext *new_tc,
-   Process *process, TheISA::IntReg flags);
+   Process *process, TheISA::IntReg flags) override;
 };

 /**
diff --git a/src/sim/process.hh b/src/sim/process.hh
index 5da30a4..e4a52e3 100644
--- a/src/sim/process.hh
+++ b/src/sim/process.hh
@@ -161,8 +161,8 @@
 void replicatePage(Addr vaddr, Addr new_paddr, ThreadContext *old_tc,
ThreadContext *new_tc, bool alloc_page);

-void clone(ThreadContext *old_tc, ThreadContext *new_tc, Process  
*new_p,

-   TheISA::IntReg flags);
+virtual void clone(ThreadContext *old_tc, ThreadContext *new_tc,
+   Process *new_p, TheISA::IntReg flags);

 // thread contexts associated with this process
 std::vector contextIds;

--
To view, visit https://gem5-review.googlesource.com/3902
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Iccd2f680ff6e3a5536037d688a80ab3f236bbd98
Gerrit-Change-Number: 3902
Gerrit-PatchSet: 2
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sean Wilson 
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[gem5-dev] Change in public/gem5[master]: x86: Add stats to X86 TLB

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3980 )


Change subject: x86: Add stats to X86 TLB
..

x86: Add stats to X86 TLB

Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3980
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
2 files changed, 47 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 191e91a..e954c9c 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -332,7 +332,20 @@
 DPRINTF(TLB, "Paging enabled.\n");
 // The vaddr already has the segment base applied.
 TlbEntry *entry = lookup(vaddr);
+if (mode == Read) {
+rdAccesses++;
+} else {
+wrAccesses++;
+}
 if (!entry) {
+DPRINTF(TLB, "Handling a TLB miss for "
+"address %#x at pc %#x.\n",
+vaddr, tc->instAddr());
+if (mode == Read) {
+rdMisses++;
+} else {
+wrMisses++;
+}
 if (FullSystem) {
 Fault fault = walker->start(tc, translation, req,  
mode);

 if (timing || fault != NoFault) {
@@ -343,10 +356,6 @@
 entry = lookup(vaddr);
 assert(entry);
 } else {
-DPRINTF(TLB, "Handling a TLB miss for "
-"address %#x at pc %#x.\n",
-vaddr, tc->instAddr());
-
 Process *p = tc->getProcessPtr();
 TlbEntry newEntry;
 bool success = p->pTable->lookup(vaddr, newEntry);
@@ -445,6 +454,29 @@
 }

 void
+TLB::regStats()
+{
+using namespace Stats;
+
+rdAccesses
+.name(name() + ".rdAccesses")
+.desc("TLB accesses on read requests");
+
+wrAccesses
+.name(name() + ".wrAccesses")
+.desc("TLB accesses on write requests");
+
+rdMisses
+.name(name() + ".rdMisses")
+.desc("TLB misses on read requests");
+
+wrMisses
+.name(name() + ".wrMisses")
+.desc("TLB misses on write requests");
+
+}
+
+void
 TLB::serialize(CheckpointOut ) const
 {
 // Only store the entries in use.
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index a134ad4..09cd6ed 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -100,6 +100,12 @@
 TlbEntryTrie trie;
 uint64_t lruSeq;

+// Statistics
+Stats::Scalar rdAccesses;
+Stats::Scalar wrAccesses;
+Stats::Scalar rdMisses;
+Stats::Scalar wrMisses;
+
 Fault translateInt(RequestPtr req, ThreadContext *tc);

 Fault translate(RequestPtr req, ThreadContext *tc,
@@ -142,6 +148,11 @@

 TlbEntry * insert(Addr vpn, TlbEntry );

+/*
+ * Function to register Stats
+ */
+void regStats();
+
 // Checkpointing
 void serialize(CheckpointOut ) const override;
 void unserialize(CheckpointIn ) override;

--
To view, visit https://gem5-review.googlesource.com/3980
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4
Gerrit-Change-Number: 3980
Gerrit-PatchSet: 3
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sean Wilson 
Gerrit-Reviewer: Swapnil Haria 
Gerrit-CC: Anthony Gutierrez 
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[gem5-dev] Change in public/gem5[master]: testers: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3926 )


Change subject: testers: Refactor some Event subclasses to lambdas
..

testers: Refactor some Event subclasses to lambdas

Change-Id: I897b6162a827216b7bad74d955c0e50e06a5a3ec
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3926
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
---
M src/cpu/testers/directedtest/RubyDirectedTester.cc
M src/cpu/testers/directedtest/RubyDirectedTester.hh
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/rubytest/RubyTester.hh
6 files changed, 11 insertions(+), 49 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc  
b/src/cpu/testers/directedtest/RubyDirectedTester.cc

index 667d50f..ef13337 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.cc
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc
@@ -47,7 +47,9 @@
 #include "sim/sim_exit.hh"

 RubyDirectedTester::RubyDirectedTester(const Params *p)
-  : MemObject(p), directedStartEvent(this),
+  : MemObject(p),
+directedStartEvent([this]{ wakeup(); }, "Directed tick",
+   false, Event::CPU_Tick_Pri),
 m_requests_to_complete(p->requests_to_complete),
 generator(p->generator)
 {
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh  
b/src/cpu/testers/directedtest/RubyDirectedTester.hh

index 74a8911..00278a6 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.hh
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh
@@ -85,20 +85,7 @@
 void print(std::ostream& out) const;

   protected:
-class DirectedStartEvent : public Event
-{
-  private:
-RubyDirectedTester *tester;
-
-  public:
-DirectedStartEvent(RubyDirectedTester *_tester)
-: Event(CPU_Tick_Pri), tester(_tester)
-{}
-void process() { tester->wakeup(); }
-virtual const char *description() const { return "Directed tick"; }
-};
-
-DirectedStartEvent directedStartEvent;
+EventFunctionWrapper directedStartEvent;

   private:
 void hitCallback(NodeID proc, Addr addr);
diff --git  
a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc  
b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc

index 0f8c877..1345fe9 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
@@ -76,7 +76,8 @@

 GarnetSyntheticTraffic::GarnetSyntheticTraffic(const Params *p)
 : MemObject(p),
-  tickEvent(this),
+  tickEvent([this]{ tick(); }, "GarnetSyntheticTraffic tick",
+false, Event::CPU_Tick_Pri),
   cachePort("GarnetSyntheticTraffic", this),
   retryPkt(NULL),
   size(p->memory_size),
diff --git  
a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh  
b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh

index 94eee44..3da7e27 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
@@ -74,21 +74,7 @@
 void printAddr(Addr a);

   protected:
-class TickEvent : public Event
-{
-  private:
-GarnetSyntheticTraffic *cpu;
-
-  public:
-TickEvent(GarnetSyntheticTraffic *c) : Event(CPU_Tick_Pri), cpu(c)  
{}

-void process() { cpu->tick(); }
-virtual const char *description() const
-{
-return "GarnetSyntheticTraffic tick";
-}
-};
-
-TickEvent tickEvent;
+EventFunctionWrapper tickEvent;

 class CpuPort : public MasterPort
 {
@@ -160,6 +146,3 @@
 };

 #endif // __CPU_GARNET_SYNTHETIC_TRAFFIC_HH__
-
-
-
diff --git a/src/cpu/testers/rubytest/RubyTester.cc  
b/src/cpu/testers/rubytest/RubyTester.cc

index baf2b7e..712d15d 100644
--- a/src/cpu/testers/rubytest/RubyTester.cc
+++ b/src/cpu/testers/rubytest/RubyTester.cc
@@ -50,7 +50,9 @@
 #include "sim/system.hh"

 RubyTester::RubyTester(const Params *p)
-  : MemObject(p), checkStartEvent(this),
+  : MemObject(p),
+checkStartEvent([this]{ wakeup(); }, "RubyTester tick",
+false, Event::CPU_Tick_Pri),
 _masterId(p->system->getMasterId(name())),
 m_checkTable_ptr(nullptr),
 m_num_cpus(p->num_cpus),
diff --git a/src/cpu/testers/rubytest/RubyTester.hh  
b/src/cpu/testers/rubytest/RubyTester.hh

index 39e6d78..0070359 100644
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/testers/rubytest/RubyTester.hh
@@ -118,20 +118,7 @@

 MasterID masterId() 

[gem5-dev] Change in public/gem5[master]: cpu: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3923 )


Change subject: cpu: Refactor some Event subclasses to lambdas
..

cpu: Refactor some Event subclasses to lambdas

Change-Id: If765c6100d67556f157e4e61aa33c2b7eeb8d2f0
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3923
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
---
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
10 files changed, 30 insertions(+), 138 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 78b25ca..6f76b8c 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -248,7 +248,9 @@

 if (FullSystem) {
 if (params()->profile)
-profileEvent = new ProfileEvent(this, params()->profile);
+profileEvent = new EventFunctionWrapper(
+[this]{ processProfileEvent(); },
+name());
 }
 tracer = params()->tracer;

@@ -658,21 +660,15 @@
 }
 }

-
-BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
-: cpu(_cpu), interval(_interval)
-{ }
-
 void
-BaseCPU::ProfileEvent::process()
+BaseCPU::processProfileEvent()
 {
-ThreadID size = cpu->threadContexts.size();
-for (ThreadID i = 0; i < size; ++i) {
-ThreadContext *tc = cpu->threadContexts[i];
-tc->profileSample();
-}
+ThreadID size = threadContexts.size();

-cpu->schedule(this, curTick() + interval);
+for (ThreadID i = 0; i < size; ++i)
+threadContexts[i]->profileSample();
+
+schedule(profileEvent, curTick() + params()->profile);
 }

 void
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index b49f302..79a4bf1 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -248,17 +248,8 @@
 return FullSystem &&  
interrupts[tc->threadId()]->checkInterrupts(tc);

 }

-class ProfileEvent : public Event
-{
-  private:
-BaseCPU *cpu;
-Tick interval;
-
-  public:
-ProfileEvent(BaseCPU *cpu, Tick interval);
-void process();
-};
-ProfileEvent *profileEvent;
+void processProfileEvent();
+EventFunctionWrapper * profileEvent;

   protected:
 std::vector threadContexts;
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index 3b70c53..bf26120 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -321,7 +321,8 @@
 LSQ::SplitDataRequest::SplitDataRequest(LSQ _, MinorDynInstPtr inst_,
 bool isLoad_, PacketDataPtr data_, uint64_t *res_) :
 LSQRequest(port_, inst_, isLoad_, data_, res_),
-translationEvent(*this),
+translationEvent([this]{ sendNextFragmentToTranslation(); },
+ "translationEvent"),
 numFragments(0),
 numInTranslationFragments(0),
 numTranslatedFragments(0),
diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh
index 1a90948..d4973f5 100644
--- a/src/cpu/minor/lsq.hh
+++ b/src/cpu/minor/lsq.hh
@@ -377,20 +377,7 @@
 {
   protected:
 /** Event to step between translations */
-class TranslationEvent : public Event
-{
-  protected:
-SplitDataRequest 
-
-  public:
-TranslationEvent(SplitDataRequest _)
-: owner(owner_) { }
-
-void process()
-{ owner.sendNextFragmentToTranslation(); }
-};
-
-TranslationEvent translationEvent;
+EventFunctionWrapper translationEvent;
   protected:
 /** Number of fragments this request is split into */
 unsigned int numFragments;
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 5977f94..f508a37 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -101,21 +101,6 @@

 typedef O3ThreadState Thread;

-/** Event class used to schedule a squash due to a trap (fault or
- * interrupt) to happen on a specific cycle.
- */
-class TrapEvent : public Event {
-  private:
-DefaultCommit *commit;
-ThreadID tid;
-
-  public:
-TrapEvent(DefaultCommit *_commit, ThreadID _tid);
-
-void process();
-const char *description() const;
-};
-
 /** Overall commit status. Used to determine if the CPU can deschedule
  * itself due to a lack of activity.
  */
@@ -157,6 +142,9 @@
 /** To probe when an instruction is squashed */
 ProbePointArg *ppSquash;

+/** Mark the thread as processing a trap. */
+void processTrapEvent(ThreadID tid);
+
   public:
 /** 

[gem5-dev] Change in public/gem5[master]: gpu-compute: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3922 )


Change subject: gpu-compute: Refactor some Event subclasses to lambdas
..

gpu-compute: Refactor some Event subclasses to lambdas

Change-Id: Ic1332b8e8ba0afacbe591c80f4d06afbf5f04bd9
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3922
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Anthony Gutierrez 
Maintainer: Anthony Gutierrez 
---
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/dispatcher.cc
M src/gpu-compute/dispatcher.hh
M src/gpu-compute/shader.cc
M src/gpu-compute/shader.hh
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/tlb_coalescer.hh
8 files changed, 95 insertions(+), 199 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved



diff --git a/src/gpu-compute/compute_unit.cc  
b/src/gpu-compute/compute_unit.cc

index ffa5243..87f29eb 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -669,9 +669,8 @@
 return true;
 }

-ComputeUnit::DataPort::MemRespEvent *mem_resp_event =
-new  
ComputeUnit::DataPort::MemRespEvent(computeUnit->memPort[index],

-pkt);
+EventFunctionWrapper *mem_resp_event =
+computeUnit->memPort[index]->createMemRespEvent(pkt);

 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x received!\n",
 computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
@@ -845,8 +844,8 @@

 // translation is done. Schedule the mem_req_event at the
 // appropriate cycle to send the timing memory request to ruby
-ComputeUnit::DataPort::MemReqEvent *mem_req_event =
-new ComputeUnit::DataPort::MemReqEvent(memPort[index],  
pkt);

+EventFunctionWrapper *mem_req_event =
+memPort[index]->createMemReqEvent(pkt);

 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x data "
 "scheduled\n", cu_id, gpuDynInst->simdId,
@@ -923,8 +922,8 @@
 void
 ComputeUnit::sendSyncRequest(GPUDynInstPtr gpuDynInst, int index,  
PacketPtr pkt)

 {
-ComputeUnit::DataPort::MemReqEvent *mem_req_event =
-new ComputeUnit::DataPort::MemReqEvent(memPort[index], pkt);
+EventFunctionWrapper *mem_req_event =
+memPort[index]->createMemReqEvent(pkt);


 // New SenderState for the memory access
@@ -972,26 +971,20 @@
 sendSyncRequest(gpuDynInst, 0, pkt);
 }

-const char*
-ComputeUnit::DataPort::MemRespEvent::description() const
-{
-return "ComputeUnit memory response event";
-}
-
 void
-ComputeUnit::DataPort::MemRespEvent::process()
+ComputeUnit::DataPort::processMemRespEvent(PacketPtr pkt)
 {
 DataPort::SenderState *sender_state =
 safe_cast(pkt->senderState);

 GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst;
-ComputeUnit *compute_unit = dataPort->computeUnit;
+ComputeUnit *compute_unit = computeUnit;

 assert(gpuDynInst);

 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: Response for addr %#x, index %d\n",
 compute_unit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
-pkt->req->getPaddr(), dataPort->index);
+pkt->req->getPaddr(), index);

 Addr paddr = pkt->req->getPaddr();

@@ -1045,8 +1038,9 @@
 // this memory request
 if (gpuDynInst->useContinuation) {
 assert(!gpuDynInst->isNoScope());
- 
gpuDynInst->execContinuation(gpuDynInst->staticInstruction(),

- gpuDynInst);
+gpuDynInst->execContinuation(
+gpuDynInst->staticInstruction(),
+gpuDynInst);
 }
 }
 }
@@ -1230,9 +1224,8 @@

 // translation is done. Schedule the mem_req_event at the appropriate
 // cycle to send the timing memory request to ruby
-ComputeUnit::DataPort::MemReqEvent *mem_req_event =
-new  
ComputeUnit::DataPort::MemReqEvent(computeUnit->memPort[mp_index],

-   new_pkt);
+EventFunctionWrapper *mem_req_event =
+computeUnit->memPort[mp_index]->createMemReqEvent(new_pkt);

 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x data  
scheduled\n",

 computeUnit->cu_id, gpuDynInst->simdId,
@@ -1244,32 +1237,42 @@
 return true;
 }

-const char*
-ComputeUnit::DataPort::MemReqEvent::description() const
+EventFunctionWrapper*
+ComputeUnit::DataPort::createMemReqEvent(PacketPtr pkt)
 {
-return "ComputeUnit memory request event";
+

[gem5-dev] Change in public/gem5[master]: sim, gdb: Refactor some Event subclasses into lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3921 )


Change subject: sim, gdb: Refactor some Event subclasses into lambdas
..

sim, gdb: Refactor some Event subclasses into lambdas

Change-Id: If3e4329204f27eda96b50ec6ac279ebc6ef23d99
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3921
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
M src/sim/ticked_object.cc
M src/sim/ticked_object.hh
4 files changed, 26 insertions(+), 53 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 3b436cc..6ed5957 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -289,17 +289,18 @@
 }

 void
-BaseRemoteGDB::SingleStepEvent::process()
+BaseRemoteGDB::processSingleStepEvent()
 {
-if (!gdb->singleStepEvent.scheduled())
-gdb->scheduleInstCommitEvent(>singleStepEvent, 1);
-gdb->trap(SIGTRAP);
+if (!singleStepEvent.scheduled())
+scheduleInstCommitEvent(, 1);
+trap(SIGTRAP);
 }

 BaseRemoteGDB::BaseRemoteGDB(System *_system, ThreadContext *c) :
-inputEvent(NULL), trapEvent(this), listener(NULL),
-number(-1), fd(-1), active(false), attached(false),  
system(_system),

-context(c), singleStepEvent(this)
+inputEvent(NULL), trapEvent(this), listener(NULL), number(-1),
+fd(-1), active(false), attached(false), system(_system),
+context(c),
+singleStepEvent([this]{ processSingleStepEvent(); }, name())
 {
 }

@@ -1123,4 +1124,3 @@
 *srcp = src;
 return r;
 }
-
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index b7de0ae..121faaf 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -260,20 +260,8 @@
 return trap(SIGTRAP);
 }

-  protected:
-class SingleStepEvent : public Event
-{
-  protected:
-BaseRemoteGDB *gdb;
-
-  public:
-SingleStepEvent(BaseRemoteGDB *g) : gdb(g)
-{}
-
-void process();
-};
-
-SingleStepEvent singleStepEvent;
+void processSingleStepEvent();
+EventFunctionWrapper singleStepEvent;

 void clearSingleStep();
 void setSingleStep();
diff --git a/src/sim/ticked_object.cc b/src/sim/ticked_object.cc
index a9f3ace..1a04dc1 100644
--- a/src/sim/ticked_object.cc
+++ b/src/sim/ticked_object.cc
@@ -46,7 +46,7 @@
 Stats::Scalar *imported_num_cycles,
 Event::Priority priority) :
 object(object_),
-event(*this, priority),
+event([this]{ processClockEvent(); }, name(), false, priority),
 running(false),
 lastStopped(0),
 /* Allocate numCycles if an external stat wasn't passed in */
@@ -56,6 +56,16 @@
 { }

 void
+Ticked::processClockEvent() {
+++tickCycles;
+++numCycles;
+countCycles(Cycles(1));
+evaluate();
+if (running)
+object.schedule(event, object.clockEdge(Cycles(1)));
+}
+
+void
 Ticked::regStats()
 {
 if (numCyclesLocal) {
diff --git a/src/sim/ticked_object.hh b/src/sim/ticked_object.hh
index 3ba0045..ad7d6e9 100644
--- a/src/sim/ticked_object.hh
+++ b/src/sim/ticked_object.hh
@@ -60,39 +60,14 @@
 class Ticked : public Serializable
 {
   protected:
-/** An event to call process periodically */
-class ClockEvent : public Event
-{
-  public:
-Ticked 
-
-ClockEvent(Ticked _, Priority priority) :
-Event(priority),
-owner(owner_)
-{ }
-
-/** Evaluate and reschedule */
-void
-process()
-{
-++owner.tickCycles;
-++owner.numCycles;
-owner.countCycles(Cycles(1));
-owner.evaluate();
-if (owner.running) {
-owner.object.schedule(this,
-owner.object.clockEdge(Cycles(1)));
-}
-}
-};
-
-friend class ClockEvent;
-
 /** ClockedObject who is responsible for this Ticked's actions/stats */
 ClockedObject 

-/** The single instance of ClockEvent used */
-ClockEvent event;
+/** The wrapper for processClockEvent */
+EventFunctionWrapper event;
+
+/** Evaluate and reschedule */
+void processClockEvent();

 /** Have I been started? and am not stopped */
 bool running;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: If3e4329204f27eda96b50ec6ac279ebc6ef23d99
Gerrit-Change-Number: 3921
Gerrit-PatchSet: 4
Gerrit-Owner: Sean Wilson 

[gem5-dev] Change in public/gem5[master]: arm: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3929 )


Change subject: arm: Refactor some Event subclasses to lambdas
..

arm: Refactor some Event subclasses to lambdas

Change-Id: Ic59add8afee1d49633634272d9687a4b1558537e
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3929
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/dev/arm/gic_pl390.cc
M src/dev/arm/gic_pl390.hh
M src/dev/arm/vgic.cc
M src/dev/arm/vgic.hh
4 files changed, 17 insertions(+), 32 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc
index 126431f..d2ec1d7 100644
--- a/src/dev/arm/gic_pl390.cc
+++ b/src/dev/arm/gic_pl390.cc
@@ -87,7 +87,9 @@
 cpuBpr[x] = GICC_BPR_MINIMUM;
 // Initialize cpu highest int
 cpuHighestInt[x] = SPURIOUS_INT;
-postIntEvent[x] = new PostIntEvent(*this, x);
+postIntEvent[x] =
+new EventFunctionWrapper([this, x]{ postDelayedInt(x); },
+ "Post Interrupt to CPU");
 }
 DPRINTF(Interrupt, "cpuEnabled[0]=%d cpuEnabled[1]=%d\n",  
cpuEnabled[0],

 cpuEnabled[1]);
diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh
index 60d9ae3..58d8434 100644
--- a/src/dev/arm/gic_pl390.hh
+++ b/src/dev/arm/gic_pl390.hh
@@ -353,21 +353,7 @@
  */
 void postDelayedInt(uint32_t cpu);

-/** Event definition to post interrupt to CPU after a delay
-*/
-class PostIntEvent : public Event
-{
-  private:
-Pl390 
-uint32_t cpu;
-  public:
-PostIntEvent(Pl390 &_parent, uint32_t _cpu)
-: parent(_parent), cpu(_cpu)
-{ }
-void process() { parent.postDelayedInt(cpu); }
-const char *description() const { return "Post Interrupt to CPU"; }
-};
-PostIntEvent *postIntEvent[CPU_MAX];
+EventFunctionWrapper *postIntEvent[CPU_MAX];
 int pendingDelayedInterrupts;

   public:
diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc
index 6744ad5..cc8ad77 100644
--- a/src/dev/arm/vgic.cc
+++ b/src/dev/arm/vgic.cc
@@ -53,7 +53,9 @@
   maintInt(p->ppint)
 {
 for (int x = 0; x < VGIC_CPU_MAX; x++) {
-postVIntEvent[x] = new PostVIntEvent(x, p->platform);
+postVIntEvent[x] = new EventFunctionWrapper(
+[this, x]{ processPostVIntEvent(x); },
+"Post VInterrupt to CPU");
 maintIntPosted[x] = false;
 vIntPosted[x] = false;
 }
@@ -369,6 +371,13 @@
 }

 void
+VGic::processPostVIntEvent(uint32_t cpu)
+{
+ platform->intrctrl->post(cpu, ArmISA::INT_VIRT_IRQ, 0);
+}
+
+
+void
 VGic::postMaintInt(uint32_t cpu)
 {
 DPRINTF(VGIC, "Posting maintenance PPI to GIC/cpu%d\n", cpu);
diff --git a/src/dev/arm/vgic.hh b/src/dev/arm/vgic.hh
index e9bc29c..40e42d4 100644
--- a/src/dev/arm/vgic.hh
+++ b/src/dev/arm/vgic.hh
@@ -104,22 +104,10 @@
 static const uint32_t LR_PENDING= 1;
 static const uint32_t LR_ACTIVE = 2;

-/** Event definition to post interrupt to CPU after a delay
-*/
-class PostVIntEvent : public Event
-{
-  private:
-uint32_t cpu;
-Platform *platform;
-  public:
-PostVIntEvent( uint32_t c, Platform* p)
-: cpu(c), platform(p)
-{ }
-void process() { platform->intrctrl->post(cpu,  
ArmISA::INT_VIRT_IRQ, 0);}
-const char *description() const { return "Post VInterrupt to CPU";  
}

-};
+/** Post interrupt to CPU */
+void processPostVIntEvent(uint32_t cpu);

-PostVIntEvent *postVIntEvent[VGIC_CPU_MAX];
+EventFunctionWrapper *postVIntEvent[VGIC_CPU_MAX];
 boolmaintIntPosted[VGIC_CPU_MAX];
 boolvIntPosted[VGIC_CPU_MAX];


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ic59add8afee1d49633634272d9687a4b1558537e
Gerrit-Change-Number: 3929
Gerrit-PatchSet: 6
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sean Wilson 
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[gem5-dev] Change in public/gem5[master]: ruby: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3930 )


Change subject: ruby: Refactor some Event subclasses to lambdas
..

ruby: Refactor some Event subclasses to lambdas

Change-Id: I9f47a20a869553515a759d9a29c05f6ce4b42d64
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3930
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
---
M src/mem/ruby/common/Consumer.cc
M src/mem/ruby/common/Consumer.hh
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/RubySystem.cc
M src/mem/ruby/system/RubySystem.hh
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
8 files changed, 20 insertions(+), 96 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/ruby/common/Consumer.cc  
b/src/mem/ruby/common/Consumer.cc

index 59605d5..f68ee14 100644
--- a/src/mem/ruby/common/Consumer.cc
+++ b/src/mem/ruby/common/Consumer.cc
@@ -41,7 +41,9 @@
 {
 if (!alreadyScheduled(evt_time)) {
 // This wakeup is not redundant
-ConsumerEvent *evt = new ConsumerEvent(this);
+auto *evt = new EventFunctionWrapper(
+[this]{ wakeup(); }, "Consumer Event", true);
+
 em->schedule(evt, evt_time);
 insertScheduledWakeupTime(evt_time);
 }
diff --git a/src/mem/ruby/common/Consumer.hh  
b/src/mem/ruby/common/Consumer.hh

index 20f2bdd..b0d35bf 100644
--- a/src/mem/ruby/common/Consumer.hh
+++ b/src/mem/ruby/common/Consumer.hh
@@ -76,20 +76,6 @@
   private:
 std::set m_scheduled_wakeups;
 ClockedObject *em;
-
-class ConsumerEvent : public Event
-{
-  public:
-  ConsumerEvent(Consumer* _consumer)
-  : Event(Default_Pri, AutoDelete), m_consumer_ptr(_consumer)
-  {
-  }
-
-  void process() { m_consumer_ptr->wakeup(); }
-
-  private:
-  Consumer* m_consumer_ptr;
-};
 };

 inline std::ostream&
diff --git a/src/mem/ruby/system/GPUCoalescer.cc  
b/src/mem/ruby/system/GPUCoalescer.cc

index 991b217..a615c40 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -116,7 +116,10 @@
 }

 GPUCoalescer::GPUCoalescer(const Params *p)
-: RubyPort(p), issueEvent(this), deadlockCheckEvent(this)
+: RubyPort(p),
+  issueEvent([this]{ completeIssue(); }, "Issue coalesced request",
+ false, Event::Progress_Event_Pri),
+  deadlockCheckEvent([this]{ wakeup(); }, "GPUCoalescer deadlock  
check")

 {
 m_store_waiting_on_load_cycles = 0;
 m_store_waiting_on_store_cycles = 0;
@@ -996,11 +999,6 @@
 SequencerRequestType_to_string(requestType));
 }

-GPUCoalescer::IssueEvent::IssueEvent(GPUCoalescer* _seq)
-: Event(Progress_Event_Pri), seq(_seq)
-{
-}
-

 void
 GPUCoalescer::completeIssue()
@@ -1042,18 +1040,6 @@
 }

 void
-GPUCoalescer::IssueEvent::process()
-{
-seq->completeIssue();
-}
-
-const char *
-GPUCoalescer::IssueEvent::description() const
-{
-return "Issue coalesced request";
-}
-
-void
 GPUCoalescer::evictionCallback(Addr address)
 {
 ruby_eviction_callback(address);
diff --git a/src/mem/ruby/system/GPUCoalescer.hh  
b/src/mem/ruby/system/GPUCoalescer.hh

index 2b42e19..8946838 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -255,17 +255,7 @@

 bool handleLlsc(Addr address, GPUCoalescerRequest* request);

-class IssueEvent : public Event
-{
-  private:
-GPUCoalescer *seq;
-  public:
-IssueEvent(GPUCoalescer *_seq);
-void process();
-const char *description() const;
-};
-
-IssueEvent issueEvent;
+EventFunctionWrapper issueEvent;


   // Changed to protected to enable inheritance by VIPER Coalescer
@@ -305,22 +295,7 @@

 bool m_runningGarnetStandalone;

-class GPUCoalescerWakeupEvent : public Event
-{
-  private:
-GPUCoalescer *m_GPUCoalescer_ptr;
-
-  public:
-GPUCoalescerWakeupEvent(GPUCoalescer *_seq) :
-m_GPUCoalescer_ptr(_seq) {}
-void process() { m_GPUCoalescer_ptr->wakeup(); }
-const char *description() const
-{
-return "GPUCoalescer deadlock check";
-}
-};
-
-GPUCoalescerWakeupEvent deadlockCheckEvent;
+EventFunctionWrapper deadlockCheckEvent;
 bool assumingRfOCoherence;

 // m5 style stats for TCP hit/miss counts
@@ -382,4 +357,3 @@
 }

 #endif // __MEM_RUBY_SYSTEM_GPU_COALESCER_HH__
-
diff --git a/src/mem/ruby/system/RubySystem.cc  
b/src/mem/ruby/system/RubySystem.cc

index e1717e5..3d0470c 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -380,12 +380,12 @@
 }

 void
-RubySystem::RubyEvent::process()

[gem5-dev] Change in public/gem5[master]: net: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3927 )


Change subject: net: Refactor some Event subclasses to lambdas
..

net: Refactor some Event subclasses to lambdas

Change-Id: I0e23f1529b26c36d749bf5211ee8623744d0b10f
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3927
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
---
M src/dev/net/etherbus.cc
M src/dev/net/etherbus.hh
M src/dev/net/ethertap.cc
M src/dev/net/ethertap.hh
4 files changed, 6 insertions(+), 30 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/dev/net/etherbus.cc b/src/dev/net/etherbus.cc
index 7ccb8a4..243e27b 100644
--- a/src/dev/net/etherbus.cc
+++ b/src/dev/net/etherbus.cc
@@ -52,7 +52,8 @@

 EtherBus::EtherBus(const Params *p)
 : EtherObject(p), ticksPerByte(p->speed), loopback(p->loopback),
-  event(this), sender(0), dump(p->dump)
+  event([this]{ txDone(); }, "ethernet bus completion"),
+  sender(0), dump(p->dump)
 {
 }

diff --git a/src/dev/net/etherbus.hh b/src/dev/net/etherbus.hh
index 7395c28..1b26453 100644
--- a/src/dev/net/etherbus.hh
+++ b/src/dev/net/etherbus.hh
@@ -52,19 +52,7 @@
 bool loopback;

   protected:
-class DoneEvent : public Event
-{
-  protected:
-EtherBus *bus;
-
-  public:
-DoneEvent(EtherBus *b) : bus(b) {}
-virtual void process() { bus->txDone(); }
-virtual const char *description() const
-{ return "ethernet bus completion"; }
-};
-
-DoneEvent event;
+EventFunctionWrapper event;
 EthPacketPtr packet;
 EtherInt *sender;
 EtherDump *dump;
diff --git a/src/dev/net/ethertap.cc b/src/dev/net/ethertap.cc
index 0c027b6..59314e5 100644
--- a/src/dev/net/ethertap.cc
+++ b/src/dev/net/ethertap.cc
@@ -84,7 +84,8 @@

 EtherTapBase::EtherTapBase(const Params *p)
 : EtherObject(p), buflen(p->bufsz), dump(p->dump), event(NULL),
-  interface(NULL), txEvent(this)
+  interface(NULL),
+  txEvent([this]{ retransmit(); }, "EtherTapBase retransmit")
 {
 buffer = new uint8_t[buflen];
 interface = new EtherTapInt(name() + ".interface", this);
diff --git a/src/dev/net/ethertap.hh b/src/dev/net/ethertap.hh
index 96cc471..9b4e175 100644
--- a/src/dev/net/ethertap.hh
+++ b/src/dev/net/ethertap.hh
@@ -109,21 +109,7 @@
   protected:
 std::queue packetBuffer;
 void retransmit();
-
-class TxEvent : public Event
-{
-  protected:
-EtherTapBase *tap;
-
-  public:
-TxEvent(EtherTapBase *_tap) : tap(_tap) {}
-void process() { tap->retransmit(); }
-virtual const char *description() const
-{ return "EtherTapBase retransmit"; }
-};
-
-friend class TxEvent;
-TxEvent txEvent;
+EventFunctionWrapper txEvent;
 };

 class EtherTapInt : public EtherInt

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I0e23f1529b26c36d749bf5211ee8623744d0b10f
Gerrit-Change-Number: 3927
Gerrit-PatchSet: 6
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sean Wilson 
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[gem5-dev] Change in public/gem5[master]: dev: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3928 )


Change subject: dev: Refactor some Event subclasses to lambdas
..

dev: Refactor some Event subclasses to lambdas

Change-Id: I965d31ff8ad1658b03a902bf4244d7d0977b0466
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3928
Maintainer: Andreas Sandberg 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
---
M src/dev/dma_device.hh
M src/dev/uart8250.cc
M src/dev/uart8250.hh
3 files changed, 23 insertions(+), 59 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index f354d38..0dc79df 100644
--- a/src/dev/dma_device.hh
+++ b/src/dev/dma_device.hh
@@ -240,22 +240,6 @@
 }
 }

-/**
- * Event invoked by DmaDevice on completion of each chunk.
- */
-class DmaChunkEvent : public Event
-{
-  private:
-DmaCallback *callback;
-
-  public:
-DmaChunkEvent(DmaCallback *cb)
-  : Event(Default_Pri, AutoDelete), callback(cb)
-{ }
-
-void process() { callback->chunkComplete(); }
-};
-
   public:

 /**
@@ -265,7 +249,8 @@
 Event *getChunkEvent()
 {
 ++count;
-return new DmaChunkEvent(this);
+return new EventFunctionWrapper([this]{ chunkComplete(); }, name(),
+true);
 }
 };

diff --git a/src/dev/uart8250.cc b/src/dev/uart8250.cc
index 3c97604..482135c 100644
--- a/src/dev/uart8250.cc
+++ b/src/dev/uart8250.cc
@@ -49,27 +49,14 @@
 using namespace std;
 using namespace TheISA;

-Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
-: uart(u)
-{
-DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
-intrBit = bit;
-}
-
-const char *
-Uart8250::IntrEvent::description() const
-{
-return "uart interrupt delay";
-}
-
 void
-Uart8250::IntrEvent::process()
+Uart8250::processIntrEvent(int intrBit)
 {
-if (intrBit & uart->IER) {
+if (intrBit & IER) {
DPRINTF(Uart, "UART InterEvent, interrupting\n");
-   uart->platform->postConsoleInt();
-   uart->status |= intrBit;
-   uart->lastTxInt = curTick();
+   platform->postConsoleInt();
+   status |= intrBit;
+   lastTxInt = curTick();
 }
 else
DPRINTF(Uart, "UART InterEvent, not interrupting\n");
@@ -89,21 +76,22 @@
  * character to send to alleviate this problem. --Ali
  */
 void
-Uart8250::IntrEvent::scheduleIntr()
+Uart8250::scheduleIntr(Event *event)
 {
 static const Tick interval = 225 * SimClock::Int::ns;
-DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n",  
intrBit,

-curTick() + interval);
-if (!scheduled())
-uart->schedule(this, curTick() + interval);
+DPRINTF(Uart, "Scheduling IER interrupt for %s, at cycle %lld\n",
+event->name(), curTick() + interval);
+if (!event->scheduled())
+schedule(event, curTick() + interval);
 else
-uart->reschedule(this, curTick() + interval);
+reschedule(event, curTick() + interval);
 }


 Uart8250::Uart8250(const Params *p)
 : Uart(p, 8), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
-  txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
+  txIntrEvent([this]{ processIntrEvent(TX_INT); }, "TX"),
+  rxIntrEvent([this]{ processIntrEvent(RX_INT); }, "RX")
 {
 }

@@ -131,7 +119,7 @@
 platform->clearConsoleInt();

 if (term->dataAvailable() && (IER & UART_IER_RDI))
-rxIntrEvent.scheduleIntr();
+scheduleIntr();
 } else { // dll divisor latch
;
 }
@@ -206,7 +194,7 @@
 platform->clearConsoleInt();
 status &= ~TX_INT;
 if (UART_IER_THRI & IER)
-txIntrEvent.scheduleIntr();
+scheduleIntr();
 } else { // dll divisor latch
;
 }
@@ -224,7 +212,7 @@
 } else {
 DPRINTF(Uart, "-- Delaying interrupt... %d,%d\n",
 curTick(), lastTxInt);
-txIntrEvent.scheduleIntr();
+scheduleIntr();
 }
 }
 else
@@ -239,7 +227,7 @@

 if ((UART_IER_RDI & IER) && term->dataAvailable()) {
 DPRINTF(Uart, "IER: IER_RDI set, scheduling RX  
intrrupt\n");

-rxIntrEvent.scheduleIntr();
+scheduleIntr();
 } else {
 DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX  
intrrupt\n");

 

[gem5-dev] Change in public/gem5[master]: mips, x86: Refactor some Event subclasses into lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3920 )


Change subject: mips, x86: Refactor some Event subclasses into lambdas
..

mips, x86: Refactor some Event subclasses into lambdas

Change-Id: I09570e569efe55f5502bc201e03456738999e714
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3920
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/x86/interrupts.cc
M src/arch/x86/interrupts.hh
4 files changed, 16 insertions(+), 75 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 6310f67..df70bac 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -523,7 +523,9 @@
 cp0Updated = true;

 //schedule UPDATE
-CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
+auto cp0_event = new EventFunctionWrapper(
+[this, cpu]{ processCP0Event(cpu, UpdateCP0); },
+"Coprocessor-0 event", true, Event::CPU_Tick_Pri);
 cpu->schedule(cp0_event, cpu->clockEdge(delay));
 }
 }
@@ -557,40 +559,17 @@
 cp0Updated = false;
 }

-ISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type)
-: Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type)
-{  }
-
 void
-ISA::CP0Event::process()
+ISA::processCP0Event(BaseCPU *cpu, CP0EventType cp0EventType)
 {
 switch (cp0EventType)
 {
   case UpdateCP0:
-cp0->updateCPU(cpu);
+updateCPU(cpu);
 break;
 }
 }

-const char *
-ISA::CP0Event::description() const
-{
-return "Coprocessor-0 event";
-}
-
-void
-ISA::CP0Event::scheduleEvent(Cycles delay)
-{
-cpu->reschedule(this, cpu->clockEdge(delay), true);
-}
-
-void
-ISA::CP0Event::unscheduleEvent()
-{
-if (scheduled())
-squash();
-}
-
 }

 MipsISA::ISA *
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index c38b7ce..885ca2f 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -118,31 +118,8 @@
 UpdateCP0
 };

-// Declare A CP0Event Class for scheduling
-class CP0Event : public Event
-{
-  protected:
-ISA::CP0 *cp0;
-BaseCPU *cpu;
-CP0EventType cp0EventType;
-Fault fault;
-
-  public:
-/** Constructs a CP0 event. */
-CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type);
-
-/** Process this event. */
-virtual void process();
-
-/** Returns the description of this event. */
-const char *description() const;
-
-/** Schedule This Event */
-void scheduleEvent(Cycles delay);
-
-/** Unschedule This Event */
-void unscheduleEvent();
-};
+/** Process a CP0 event */
+void processCP0Event(BaseCPU *cpu, CP0EventType);

 // Schedule a CP0 Update Event
 void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
@@ -151,9 +128,6 @@
 // and if necessary alert the CPU
 void updateCPU(BaseCPU *cpu);

-// Keep a List of CPU Events that need to be deallocated
-std::queue cp0EventRemoveList;
-
 static std::string miscRegNames[NumMiscRegs];

   public:
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index b869a92..0ef79a4 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -588,7 +588,7 @@

 X86ISA::Interrupts::Interrupts(Params * p)
 : BasicPioDevice(p, PageBytes), IntDevice(this, p->int_latency),
-  apicTimerEvent(this),
+  apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
   pendingSmi(false), smiVector(0),
   pendingNmi(false), nmiVector(0),
   pendingExtInt(false), extIntVector(0),
@@ -767,3 +767,9 @@
 {
 return new X86ISA::Interrupts(this);
 }
+
+void
+X86ISA::Interrupts::processApicTimerEvent() {
+if (triggerTimerInterrupt())
+setReg(APIC_INITIAL_COUNT, readReg(APIC_INITIAL_COUNT));
+}
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 26699b0..bfd1889 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -92,26 +92,8 @@
 /*
  * Timing related stuff.
  */
-class ApicTimerEvent : public Event
-{
-  private:
-Interrupts *localApic;
-  public:
-ApicTimerEvent(Interrupts *_localApic) :
-Event(), localApic(_localApic)
-{}
-
-void process()
-{
-assert(localApic);
-if (localApic->triggerTimerInterrupt()) {
-localApic->setReg(APIC_INITIAL_COUNT,
-localApic->readReg(APIC_INITIAL_COUNT));
- 

[gem5-dev] Change in public/gem5[master]: kvm, mem: Refactor some Event subclasses into lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3924 )


Change subject: kvm, mem: Refactor some Event subclasses into lambdas
..

kvm, mem: Refactor some Event subclasses into lambdas

Change-Id: Ifafdcf4692d58a17f90e66ff8de8fa3e146c34bb
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3924
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/cpu/kvm/base.cc
M src/cpu/kvm/base.hh
M src/mem/external_slave.cc
3 files changed, 16 insertions(+), 36 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index 23a4080..250c6a2 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -74,7 +74,8 @@
   vcpuID(vm.allocVCPUID()), vcpuFD(-1), vcpuMMapSize(0),
   _kvmRun(NULL), mmioRing(NULL),
   pageSize(sysconf(_SC_PAGE_SIZE)),
-  tickEvent(*this),
+  tickEvent([this]{ tick(); }, "BaseKvmCPU tick",
+false, Event::CPU_Tick_Pri),
   activeInstPeriod(0),
   perfControlledByTimer(params->usePerfOverflow),
   hostFactor(params->hostFactor),
diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index 6f30c55..29872e7 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -630,20 +630,6 @@
 pthread_t vcpuThread;

   private:
-struct TickEvent : public Event
-{
-BaseKvmCPU 
-
-TickEvent(BaseKvmCPU )
-: Event(CPU_Tick_Pri), cpu(c) {}
-
-void process() { cpu.tick(); }
-
-const char *description() const {
-return "BaseKvmCPU tick";
-}
-};
-
 /**
  * Service MMIO requests in the mmioRing.
  *
@@ -708,7 +694,7 @@
 /** Cached page size of the host */
 const long pageSize;

-TickEvent tickEvent;
+EventFunctionWrapper tickEvent;

 /**
  * Setup an instruction break if there is one pending.
diff --git a/src/mem/external_slave.cc b/src/mem/external_slave.cc
index 990e356..ac93e66 100644
--- a/src/mem/external_slave.cc
+++ b/src/mem/external_slave.cc
@@ -52,17 +52,9 @@
 class StubSlavePort : public ExternalSlave::Port
 {
   public:
-class ResponseEvent : public Event
-{
-  public:
-StubSlavePort 
+void processResponseEvent();

-ResponseEvent(StubSlavePort _) : owner(owner_) { }
-
-void process();
-};
-
-ResponseEvent responseEvent;
+EventFunctionWrapper responseEvent;

 /** Stub can handle a single request at a time.  This will be
  *  NULL when no packet is in flight */
@@ -75,7 +67,8 @@
 StubSlavePort(const std::string _,
 ExternalSlave _) :
 ExternalSlave::Port(name_, owner_),
-responseEvent(*this), responsePacket(NULL), mustRetry(false)
+responseEvent([this]{ processResponseEvent(); }, name()),
+responsePacket(NULL), mustRetry(false)
 { }

 Tick recvAtomic(PacketPtr packet);
@@ -123,18 +116,18 @@
 }

 void
-StubSlavePort::ResponseEvent::process()
+StubSlavePort::processResponseEvent()
 {
-owner.responsePacket->makeResponse();
-owner.responsePacket->headerDelay = 0;
-owner.responsePacket->payloadDelay = 0;
+responsePacket->makeResponse();
+responsePacket->headerDelay = 0;
+responsePacket->payloadDelay = 0;

-if (owner.sendTimingResp(owner.responsePacket)) {
-owner.responsePacket = NULL;
+if (sendTimingResp(responsePacket)) {
+responsePacket = NULL;

-if (owner.mustRetry)
-owner.sendRetryReq();
-owner.mustRetry = false;
+if (mustRetry)
+sendRetryReq();
+mustRetry = false;
 }
 }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ifafdcf4692d58a17f90e66ff8de8fa3e146c34bb
Gerrit-Change-Number: 3924
Gerrit-PatchSet: 5
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sean Wilson 
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[gem5-dev] Change in public/gem5[master]: x86: Add stats to X86 TLB

[Sean Wilson (Gerrit)]

Hello Swapnil Haria, Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/3980

to look at the new patch set (#2).

Change subject: x86: Add stats to X86 TLB
..

x86: Add stats to X86 TLB

Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4
Signed-off-by: Sean Wilson 
---
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
2 files changed, 47 insertions(+), 4 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4
Gerrit-Change-Number: 3980
Gerrit-PatchSet: 2
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Swapnil Haria 
Gerrit-CC: Anthony Gutierrez 
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[gem5-dev] Change in public/gem5[master]: cpu, config: Add setMainCPU to BaseCPU

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4001

to look at the new patch set (#2).

Change subject: cpu, config: Add setMainCPU to BaseCPU
..

cpu, config: Add setMainCPU to BaseCPU

To facilitate taking over from a CPU in the future, force users to first
call setMainCPU before gem5 instantiation. This allows us to be sure the
CPU instantiation that is taking over from the "main" CPU has pointers to
the right objects.

Change-Id: I3a3c39a46380e32e2cb18dc8e8304bbc3716f723
Signed-off-by: Jason Lowe-Power 
Signed-off-by: Sean Wilson 
---
M configs/common/Simulation.py
M configs/example/apu_se.py
M src/cpu/BaseCPU.py
3 files changed, 30 insertions(+), 8 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
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Gerrit-Change-Id: I3a3c39a46380e32e2cb18dc8e8304bbc3716f723
Gerrit-Change-Number: 4001
Gerrit-PatchSet: 2
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sean Wilson 
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[gem5-dev] Change in public/gem5[master]: cpu, config: Add setMainCPU to BaseCPU

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4001

to review the following change.


Change subject: cpu, config: Add setMainCPU to BaseCPU
..

cpu, config: Add setMainCPU to BaseCPU

To facilitate taking over from a CPU in the future, force users to first
call setMainCPU before gem5 instantiation. This allows us to be sure the
CPU instantiation that is taking over from the "main" CPU has pointers to
the right objects.

Change-Id: I3a3c39a46380e32e2cb18dc8e8304bbc3716f723
Signed-off-by: Jason Lowe-Power 
Signed-off-by: Sean Wilson 
---
M configs/common/Simulation.py
M configs/example/apu_se.py
M src/cpu/BaseCPU.py
3 files changed, 30 insertions(+), 8 deletions(-)



diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index c4d5c96..3c74e00 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -453,7 +453,7 @@
 testsys.cpu[i].max_insts_any_thread = options.maxinsts

 if cpu_class:
-switch_cpus = [cpu_class(switched_out=True, cpu_id=(i))
+switch_cpus = [cpu_class(main_cpu=testsys.cpu[i])
for i in xrange(np)]

 for i in xrange(np):
@@ -489,8 +489,8 @@
 print "%s: CPU switching not supported" % str(switch_class)
 sys.exit(1)

-repeat_switch_cpus = [switch_class(switched_out=True, \
-   cpu_id=(i)) for i in  
xrange(np)]

+repeat_switch_cpus = [switch_class(main_cpu=testsys.cpu[i])
+  for i in xrange(np)]

 for i in xrange(np):
 repeat_switch_cpus[i].system = testsys
@@ -513,9 +513,9 @@
   for i in xrange(np)]

 if options.standard_switch:
-switch_cpus = [TimingSimpleCPU(switched_out=True, cpu_id=(i))
+switch_cpus = [TimingSimpleCPU(main_cpu=testsys.cpu[i])
for i in xrange(np)]
-switch_cpus_1 = [DerivO3CPU(switched_out=True, cpu_id=(i))
+switch_cpus_1 = [DerivO3CPU(main_cpu=testsys.cpu[i])
 for i in xrange(np)]

 for i in xrange(np):
diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index f93442d..aaafd88 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -344,7 +344,6 @@
voltage_domain = VoltageDomain(
voltage = options.cpu_voltage)))
 if fast_forward:
-cpu.switched_out = True
 future_cpu_list.append(cpu)
 else:
 cpu_list.append(cpu)
@@ -405,8 +404,10 @@
 ## Create the overall system  


 # List of CPUs that must be switched when moving between KVM and simulation
 if fast_forward:
-switch_cpu_list = \
-[(cpu_list[i], future_cpu_list[i]) for i in  
xrange(options.num_cpus)]

+switch_cpu_list = zip(cpu_list, future_cpu_list)
+for (start_cpu, future_cpu) in switch_cpu_list:
+future_cpu.setMainCPU(start_cpu)
+

 # Full list of processing cores in the system. Note that
 # dispatcher is also added to cpu_list although it is
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 550ba62..bef195a 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -47,6 +47,7 @@
 from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
+from m5.util import panic

 from XBar import L2XBar
 from InstTracer import InstTracer
@@ -97,6 +98,12 @@
 abstract = True
 cxx_header = "cpu/base.hh"

+def __init__(self, main_cpu=None, **kwargs):
+self._readyToTakeOver = False
+super(BaseCPU, self).__init__(**kwargs)
+if main_cpu:
+self.setMainCPU(main_cpu)
+
 cxx_exports = [
 PyBindMethod("switchOut"),
 PyBindMethod("takeOverFrom"),
@@ -127,7 +134,21 @@
 """Does the CPU model support CPU takeOverFrom?"""
 return False

+def setMainCPU(self, other_cpu):
+"""This CPU will take over from the other_cpu at some point in the
+   future. This function *must* be called before taking over from
+   another CPU. Sets this CPU to switched out and replaces this  
CPUs

+   TLBs with the other_cpu's. Also sets the cpu_id to the same.
+"""
+self._readyToTakeOver = True
+self.switched_out = True
+self.itb = other_cpu.itb
+self.dtb = other_cpu.dtb
+self.cpu_id = other_cpu.cpu_id
+
 def takeOverFrom(self, old_cpu):
+if not self._readyToTakeOver:
+panic("Must call setMainCPU before takeOverFrom!")
 self._ccObject.takeOverFrom(old_cpu._ccObject)



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[gem5-dev] Change in public/gem5[master]: sim, x86: Move tlb flush from copyRegs to clone emulation.

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/4000



Change subject: sim, x86: Move tlb flush from copyRegs to clone emulation.
..

sim, x86: Move tlb flush from copyRegs to clone emulation.

copyRegs should be idempotent so it can be used for swapping CPUs.
However, clone needs to flush the TLBs since there are no ASIDs in
X86 TLBs, this change moves the flush into the clone system call.

Change-Id: Ic069ca02994436b36246403f9faef80c3aede55a
Signed-off-by: Sean Wilson 
---
M src/arch/x86/utility.cc
M src/sim/syscall_emul.hh
2 files changed, 4 insertions(+), 6 deletions(-)



diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 33b53ca..cb99d4e 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -213,9 +213,8 @@
 void
 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 {
-// This function assumes no side effects other than TLB invalidation
-// need to be considered while copying state. That will likely not be
-// true in the future.
+// This function assumes no side effects need to be considered
+// while copying state.
 for (int i = 0; i < NUM_MISCREGS; ++i) {
 if (!isValidMiscReg(i))
  continue;
@@ -226,9 +225,6 @@
 // The TSC has to be updated with side-effects if the CPUs in a
 // CPU switch have different frequencies.
 dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC));
-
-dest->getITBPtr()->flushAll();
-dest->getDTBPtr()->flushAll();
 }

 void
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 7efd7c7..2911c7f 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1339,6 +1339,8 @@
 ctc->setMiscRegNoEffect(TheISA::MISCREG_FS_BASE, tlsPtr);
 ctc->setMiscRegNoEffect(TheISA::MISCREG_FS_EFF_BASE, tlsPtr);
 }
+ctc->getITBPtr()->flushAll();
+ctc->getDTBPtr()->flushAll();
 #endif

 if (newStack)

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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic069ca02994436b36246403f9faef80c3aede55a
Gerrit-Change-Number: 4000
Gerrit-PatchSet: 1
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[gem5-dev] Change in public/gem5[master]: cpu: Use the same TLB pointer for all switching CPUs.

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/4002



Change subject: cpu: Use the same TLB pointer for all switching CPUs.
..

cpu: Use the same TLB pointer for all switching CPUs.

Previously, before a CPU was switched out, the TLB was always flushed.
With this changeset, when you switch from atomic to timing mode the
TLB is warm.

Change-Id: I8413e059d4b75d68f3577512fd7231cfccf461f4
Signed-off-by: Sean Wilson 
---
M src/cpu/base.cc
1 file changed, 0 insertions(+), 67 deletions(-)



diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 6f460d3..eb0c0ed 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -510,10 +510,6 @@
 _switchedOut = true;
 if (profileEvent && profileEvent->scheduled())
 deschedule(profileEvent);
-
-// Flush all TLBs in the CPU to avoid having stale translations if
-// it gets switched in later.
-flushTLBs();
 }

 void
@@ -546,69 +542,6 @@
if (DTRACE(Context))
 ThreadContext::compare(oldTC, newTC);
 */
-
-BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort();
-BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort();
-BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort();
-BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort();
-
-// Move over any table walker ports if they exist
-if (new_itb_port) {
-assert(!new_itb_port->isConnected());
-assert(old_itb_port);
-assert(old_itb_port->isConnected());
-BaseSlavePort  = old_itb_port->getSlavePort();
-old_itb_port->unbind();
-new_itb_port->bind(slavePort);
-}
-if (new_dtb_port) {
-assert(!new_dtb_port->isConnected());
-assert(old_dtb_port);
-assert(old_dtb_port->isConnected());
-BaseSlavePort  = old_dtb_port->getSlavePort();
-old_dtb_port->unbind();
-new_dtb_port->bind(slavePort);
-}
-newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr());
-newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr());
-
-// Checker whether or not we have to transfer CheckerCPU
-// objects over in the switch
-CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
-CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
-if (oldChecker && newChecker) {
-BaseMasterPort *old_checker_itb_port =
-oldChecker->getITBPtr()->getMasterPort();
-BaseMasterPort *old_checker_dtb_port =
-oldChecker->getDTBPtr()->getMasterPort();
-BaseMasterPort *new_checker_itb_port =
-newChecker->getITBPtr()->getMasterPort();
-BaseMasterPort *new_checker_dtb_port =
-newChecker->getDTBPtr()->getMasterPort();
-
-newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr());
-newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr());
-
-// Move over any table walker ports if they exist for checker
-if (new_checker_itb_port) {
-assert(!new_checker_itb_port->isConnected());
-assert(old_checker_itb_port);
-assert(old_checker_itb_port->isConnected());
-BaseSlavePort  =
-old_checker_itb_port->getSlavePort();
-old_checker_itb_port->unbind();
-new_checker_itb_port->bind(slavePort);
-}
-if (new_checker_dtb_port) {
-assert(!new_checker_dtb_port->isConnected());
-assert(old_checker_dtb_port);
-assert(old_checker_dtb_port->isConnected());
-BaseSlavePort  =
-old_checker_dtb_port->getSlavePort();
-old_checker_dtb_port->unbind();
-new_checker_dtb_port->bind(slavePort);
-}
-}
 }

 interrupts = oldCPU->interrupts;

--
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[gem5-dev] Change in public/gem5[master]: x86: Add stats to X86 TLB

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3980



Change subject: x86: Add stats to X86 TLB
..

x86: Add stats to X86 TLB

Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4
Signed-off-by: Sean Wilson 
---
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
2 files changed, 48 insertions(+), 4 deletions(-)



diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 191e91a..84d011b 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -332,7 +332,21 @@
 DPRINTF(TLB, "Paging enabled.\n");
 // The vaddr already has the segment base applied.
 TlbEntry *entry = lookup(vaddr);
+if (mode == Read) {
+rdAccesses++;
+}
+else {
+wrAccesses++;
+}
 if (!entry) {
+DPRINTF(TLB, "Handling a TLB miss for "
+"address %#x at pc %#x.\n",
+vaddr, tc->instAddr());
+if (mode == Read) {
+rdMisses++;
+} else {
+wrMisses++;
+}
 if (FullSystem) {
 Fault fault = walker->start(tc, translation, req,  
mode);

 if (timing || fault != NoFault) {
@@ -343,10 +357,6 @@
 entry = lookup(vaddr);
 assert(entry);
 } else {
-DPRINTF(TLB, "Handling a TLB miss for "
-"address %#x at pc %#x.\n",
-vaddr, tc->instAddr());
-
 Process *p = tc->getProcessPtr();
 TlbEntry newEntry;
 bool success = p->pTable->lookup(vaddr, newEntry);
@@ -445,6 +455,29 @@
 }

 void
+TLB::regStats()
+{
+using namespace Stats;
+
+rdAccesses
+.name(name() + ".rdAccesses")
+.desc("TLB accesses on read requests");
+
+wrAccesses
+.name(name() + ".wrAccesses")
+.desc("TLB accesses on write requests");
+
+rdMisses
+.name(name() + ".rdMisses")
+.desc("TLB misses on read requests");
+
+wrMisses
+.name(name() + ".wrMisses")
+.desc("TLB misses on write requests");
+
+}
+
+void
 TLB::serialize(CheckpointOut ) const
 {
 // Only store the entries in use.
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index a134ad4..09cd6ed 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -100,6 +100,12 @@
 TlbEntryTrie trie;
 uint64_t lruSeq;

+// Statistics
+Stats::Scalar rdAccesses;
+Stats::Scalar wrAccesses;
+Stats::Scalar rdMisses;
+Stats::Scalar wrMisses;
+
 Fault translateInt(RequestPtr req, ThreadContext *tc);

 Fault translate(RequestPtr req, ThreadContext *tc,
@@ -142,6 +148,11 @@

 TlbEntry * insert(Addr vpn, TlbEntry );

+/*
+ * Function to register Stats
+ */
+void regStats();
+
 // Checkpointing
 void serialize(CheckpointOut ) const override;
 void unserialize(CheckpointIn ) override;

--
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[gem5-dev] Change in public/gem5[master]: cpu: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/3923

to look at the new patch set (#2).

Change subject: cpu: Refactor some Event subclasses to lambdas
..

cpu: Refactor some Event subclasses to lambdas

Change-Id: If765c6100d67556f157e4e61aa33c2b7eeb8d2f0
Signed-off-by: Sean Wilson 
---
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
10 files changed, 30 insertions(+), 138 deletions(-)


--
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Gerrit-Change-Id: If765c6100d67556f157e4e61aa33c2b7eeb8d2f0
Gerrit-Change-Number: 3923
Gerrit-PatchSet: 2
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: arm: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Hello Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/3929

to look at the new patch set (#2).

Change subject: arm: Refactor some Event subclasses to lambdas
..

arm: Refactor some Event subclasses to lambdas

Change-Id: Ic59add8afee1d49633634272d9687a4b1558537e
Signed-off-by: Sean Wilson 
---
M src/dev/arm/gic_pl390.cc
M src/dev/arm/gic_pl390.hh
M src/dev/arm/vgic.cc
M src/dev/arm/vgic.hh
4 files changed, 17 insertions(+), 32 deletions(-)


--
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Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: dev: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Hello Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/3928

to look at the new patch set (#2).

Change subject: dev: Refactor some Event subclasses to lambdas
..

dev: Refactor some Event subclasses to lambdas

Change-Id: I965d31ff8ad1658b03a902bf4244d7d0977b0466
Signed-off-by: Sean Wilson 
---
M src/dev/dma_device.hh
M src/dev/uart8250.cc
M src/dev/uart8250.hh
3 files changed, 23 insertions(+), 59 deletions(-)


--
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[gem5-dev] Change in public/gem5[master]: sim, gdb: Refactor some Event subclasses into lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3921



Change subject: sim, gdb: Refactor some Event subclasses into lambdas
..

sim, gdb: Refactor some Event subclasses into lambdas

Change-Id: If3e4329204f27eda96b50ec6ac279ebc6ef23d99
Signed-off-by: Sean Wilson 
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
M src/sim/ticked_object.cc
M src/sim/ticked_object.hh
4 files changed, 26 insertions(+), 53 deletions(-)



diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index f7b0253..1f1b408 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -279,17 +279,18 @@
 }

 void
-BaseRemoteGDB::SingleStepEvent::process()
+BaseRemoteGDB::processSingleStepEvent()
 {
-if (!gdb->singleStepEvent.scheduled())
-gdb->scheduleInstCommitEvent(>singleStepEvent, 1);
-gdb->trap(SIGTRAP);
+if (!singleStepEvent.scheduled())
+scheduleInstCommitEvent(, 1);
+trap(SIGTRAP);
 }

 BaseRemoteGDB::BaseRemoteGDB(System *_system, ThreadContext *c) :
-inputEvent(NULL), trapEvent(this), listener(NULL),
-number(-1), fd(-1), active(false), attached(false),  
system(_system),

-context(c), singleStepEvent(this)
+inputEvent(NULL), trapEvent(this), listener(NULL), number(-1),
+fd(-1), active(false), attached(false), system(_system),
+context(c),
+singleStepEvent([this]{ processSingleStepEvent(); }, name())
 {
 }

@@ -1113,4 +1114,3 @@
 *srcp = src;
 return r;
 }
-
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index b860f5d..0057a5d 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -260,20 +260,8 @@
 return trap(SIGTRAP);
 }

-  protected:
-class SingleStepEvent : public Event
-{
-  protected:
-BaseRemoteGDB *gdb;
-
-  public:
-SingleStepEvent(BaseRemoteGDB *g) : gdb(g)
-{}
-
-void process();
-};
-
-SingleStepEvent singleStepEvent;
+void processSingleStepEvent();
+EventFunctionWrapper singleStepEvent;

 void clearSingleStep();
 void setSingleStep();
diff --git a/src/sim/ticked_object.cc b/src/sim/ticked_object.cc
index 4cd0dc1..95d2771 100644
--- a/src/sim/ticked_object.cc
+++ b/src/sim/ticked_object.cc
@@ -46,7 +46,7 @@
 Stats::Scalar *imported_num_cycles,
 Event::Priority priority) :
 object(object_),
-event(*this, priority),
+event([this]{ processClockEvent(); }, name(), false, priority),
 running(false),
 lastStopped(0),
 /* Allocate numCycles if an external stat wasn't passed in */
@@ -56,6 +56,16 @@
 { }

 void
+Ticked::processClockEvent() {
+++tickCycles;
+++numCycles;
+countCycles(Cycles(1));
+evaluate();
+if (running)
+object.schedule(event, object.clockEdge(Cycles(1)));
+}
+
+void
 Ticked::regStats()
 {
 if (numCyclesLocal) {
diff --git a/src/sim/ticked_object.hh b/src/sim/ticked_object.hh
index d8b69a3..973d39f 100644
--- a/src/sim/ticked_object.hh
+++ b/src/sim/ticked_object.hh
@@ -60,39 +60,14 @@
 class Ticked : public Serializable
 {
   protected:
-/** An event to call process periodically */
-class ClockEvent : public Event
-{
-  public:
-Ticked 
-
-ClockEvent(Ticked _, Priority priority) :
-Event(priority),
-owner(owner_)
-{ }
-
-/** Evaluate and reschedule */
-void
-process()
-{
-++owner.tickCycles;
-++owner.numCycles;
-owner.countCycles(Cycles(1));
-owner.evaluate();
-if (owner.running) {
-owner.object.schedule(this,
-owner.object.clockEdge(Cycles(1)));
-}
-}
-};
-
-friend class ClockEvent;
-
 /** ClockedObject who is responsible for this Ticked's actions/stats */
 ClockedObject 

-/** The single instance of ClockEvent used */
-ClockEvent event;
+/** The wrapper for processClockEvent */
+EventFunctionWrapper event;
+
+/** Evaluate and reschedule */
+void processClockEvent();

 /** Have I been started? and am not stopped */
 bool running;

--
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[gem5-dev] Change in public/gem5[master]: net: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3927



Change subject: net: Refactor some Event subclasses to lambdas
..

net: Refactor some Event subclasses to lambdas

Change-Id: I0e23f1529b26c36d749bf5211ee8623744d0b10f
Signed-off-by: Sean Wilson 
---
M src/dev/net/etherbus.cc
M src/dev/net/etherbus.hh
M src/dev/net/ethertap.cc
M src/dev/net/ethertap.hh
4 files changed, 6 insertions(+), 30 deletions(-)



diff --git a/src/dev/net/etherbus.cc b/src/dev/net/etherbus.cc
index 7ccb8a4..243e27b 100644
--- a/src/dev/net/etherbus.cc
+++ b/src/dev/net/etherbus.cc
@@ -52,7 +52,8 @@

 EtherBus::EtherBus(const Params *p)
 : EtherObject(p), ticksPerByte(p->speed), loopback(p->loopback),
-  event(this), sender(0), dump(p->dump)
+  event([this]{ txDone(); }, "ethernet bus completion"),
+  sender(0), dump(p->dump)
 {
 }

diff --git a/src/dev/net/etherbus.hh b/src/dev/net/etherbus.hh
index 7395c28..1b26453 100644
--- a/src/dev/net/etherbus.hh
+++ b/src/dev/net/etherbus.hh
@@ -52,19 +52,7 @@
 bool loopback;

   protected:
-class DoneEvent : public Event
-{
-  protected:
-EtherBus *bus;
-
-  public:
-DoneEvent(EtherBus *b) : bus(b) {}
-virtual void process() { bus->txDone(); }
-virtual const char *description() const
-{ return "ethernet bus completion"; }
-};
-
-DoneEvent event;
+EventFunctionWrapper event;
 EthPacketPtr packet;
 EtherInt *sender;
 EtherDump *dump;
diff --git a/src/dev/net/ethertap.cc b/src/dev/net/ethertap.cc
index 0c027b6..59314e5 100644
--- a/src/dev/net/ethertap.cc
+++ b/src/dev/net/ethertap.cc
@@ -84,7 +84,8 @@

 EtherTapBase::EtherTapBase(const Params *p)
 : EtherObject(p), buflen(p->bufsz), dump(p->dump), event(NULL),
-  interface(NULL), txEvent(this)
+  interface(NULL),
+  txEvent([this]{ retransmit(); }, "EtherTapBase retransmit")
 {
 buffer = new uint8_t[buflen];
 interface = new EtherTapInt(name() + ".interface", this);
diff --git a/src/dev/net/ethertap.hh b/src/dev/net/ethertap.hh
index 96cc471..9b4e175 100644
--- a/src/dev/net/ethertap.hh
+++ b/src/dev/net/ethertap.hh
@@ -109,21 +109,7 @@
   protected:
 std::queue packetBuffer;
 void retransmit();
-
-class TxEvent : public Event
-{
-  protected:
-EtherTapBase *tap;
-
-  public:
-TxEvent(EtherTapBase *_tap) : tap(_tap) {}
-void process() { tap->retransmit(); }
-virtual const char *description() const
-{ return "EtherTapBase retransmit"; }
-};
-
-friend class TxEvent;
-TxEvent txEvent;
+EventFunctionWrapper txEvent;
 };

 class EtherTapInt : public EtherInt

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[gem5-dev] Change in public/gem5[master]: kvm, mem: Refactor some Event subclasses into lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3924



Change subject: kvm, mem: Refactor some Event subclasses into lambdas
..

kvm, mem: Refactor some Event subclasses into lambdas

Change-Id: Ifafdcf4692d58a17f90e66ff8de8fa3e146c34bb
Signed-off-by: Sean Wilson 
---
M src/cpu/kvm/base.cc
M src/cpu/kvm/base.hh
M src/mem/external_slave.cc
3 files changed, 16 insertions(+), 36 deletions(-)



diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index 23a4080..250c6a2 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -74,7 +74,8 @@
   vcpuID(vm.allocVCPUID()), vcpuFD(-1), vcpuMMapSize(0),
   _kvmRun(NULL), mmioRing(NULL),
   pageSize(sysconf(_SC_PAGE_SIZE)),
-  tickEvent(*this),
+  tickEvent([this]{ tick(); }, "BaseKvmCPU tick",
+false, Event::CPU_Tick_Pri),
   activeInstPeriod(0),
   perfControlledByTimer(params->usePerfOverflow),
   hostFactor(params->hostFactor),
diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index 6f30c55..29872e7 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -630,20 +630,6 @@
 pthread_t vcpuThread;

   private:
-struct TickEvent : public Event
-{
-BaseKvmCPU 
-
-TickEvent(BaseKvmCPU )
-: Event(CPU_Tick_Pri), cpu(c) {}
-
-void process() { cpu.tick(); }
-
-const char *description() const {
-return "BaseKvmCPU tick";
-}
-};
-
 /**
  * Service MMIO requests in the mmioRing.
  *
@@ -708,7 +694,7 @@
 /** Cached page size of the host */
 const long pageSize;

-TickEvent tickEvent;
+EventFunctionWrapper tickEvent;

 /**
  * Setup an instruction break if there is one pending.
diff --git a/src/mem/external_slave.cc b/src/mem/external_slave.cc
index 990e356..ac93e66 100644
--- a/src/mem/external_slave.cc
+++ b/src/mem/external_slave.cc
@@ -52,17 +52,9 @@
 class StubSlavePort : public ExternalSlave::Port
 {
   public:
-class ResponseEvent : public Event
-{
-  public:
-StubSlavePort 
+void processResponseEvent();

-ResponseEvent(StubSlavePort _) : owner(owner_) { }
-
-void process();
-};
-
-ResponseEvent responseEvent;
+EventFunctionWrapper responseEvent;

 /** Stub can handle a single request at a time.  This will be
  *  NULL when no packet is in flight */
@@ -75,7 +67,8 @@
 StubSlavePort(const std::string _,
 ExternalSlave _) :
 ExternalSlave::Port(name_, owner_),
-responseEvent(*this), responsePacket(NULL), mustRetry(false)
+responseEvent([this]{ processResponseEvent(); }, name()),
+responsePacket(NULL), mustRetry(false)
 { }

 Tick recvAtomic(PacketPtr packet);
@@ -123,18 +116,18 @@
 }

 void
-StubSlavePort::ResponseEvent::process()
+StubSlavePort::processResponseEvent()
 {
-owner.responsePacket->makeResponse();
-owner.responsePacket->headerDelay = 0;
-owner.responsePacket->payloadDelay = 0;
+responsePacket->makeResponse();
+responsePacket->headerDelay = 0;
+responsePacket->payloadDelay = 0;

-if (owner.sendTimingResp(owner.responsePacket)) {
-owner.responsePacket = NULL;
+if (sendTimingResp(responsePacket)) {
+responsePacket = NULL;

-if (owner.mustRetry)
-owner.sendRetryReq();
-owner.mustRetry = false;
+if (mustRetry)
+sendRetryReq();
+mustRetry = false;
 }
 }


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[gem5-dev] Change in public/gem5[master]: mips, x86: Refactor some Event subclasses into lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3920



Change subject: mips, x86: Refactor some Event subclasses into lambdas
..

mips, x86: Refactor some Event subclasses into lambdas

Change-Id: I09570e569efe55f5502bc201e03456738999e714
Signed-off-by: Sean Wilson 
---
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/x86/interrupts.cc
M src/arch/x86/interrupts.hh
4 files changed, 16 insertions(+), 75 deletions(-)



diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 6310f67..df70bac 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -523,7 +523,9 @@
 cp0Updated = true;

 //schedule UPDATE
-CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
+auto cp0_event = new EventFunctionWrapper(
+[this, cpu]{ processCP0Event(cpu, UpdateCP0); },
+"Coprocessor-0 event", true, Event::CPU_Tick_Pri);
 cpu->schedule(cp0_event, cpu->clockEdge(delay));
 }
 }
@@ -557,40 +559,17 @@
 cp0Updated = false;
 }

-ISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type)
-: Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type)
-{  }
-
 void
-ISA::CP0Event::process()
+ISA::processCP0Event(BaseCPU *cpu, CP0EventType cp0EventType)
 {
 switch (cp0EventType)
 {
   case UpdateCP0:
-cp0->updateCPU(cpu);
+updateCPU(cpu);
 break;
 }
 }

-const char *
-ISA::CP0Event::description() const
-{
-return "Coprocessor-0 event";
-}
-
-void
-ISA::CP0Event::scheduleEvent(Cycles delay)
-{
-cpu->reschedule(this, cpu->clockEdge(delay), true);
-}
-
-void
-ISA::CP0Event::unscheduleEvent()
-{
-if (scheduled())
-squash();
-}
-
 }

 MipsISA::ISA *
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index feb55e4..6f5beba 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -117,31 +117,8 @@
 UpdateCP0
 };

-// Declare A CP0Event Class for scheduling
-class CP0Event : public Event
-{
-  protected:
-ISA::CP0 *cp0;
-BaseCPU *cpu;
-CP0EventType cp0EventType;
-Fault fault;
-
-  public:
-/** Constructs a CP0 event. */
-CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type);
-
-/** Process this event. */
-virtual void process();
-
-/** Returns the description of this event. */
-const char *description() const;
-
-/** Schedule This Event */
-void scheduleEvent(Cycles delay);
-
-/** Unschedule This Event */
-void unscheduleEvent();
-};
+/** Process a CP0 event */
+void processCP0Event(BaseCPU *cpu, CP0EventType);

 // Schedule a CP0 Update Event
 void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
@@ -150,9 +127,6 @@
 // and if necessary alert the CPU
 void updateCPU(BaseCPU *cpu);

-// Keep a List of CPU Events that need to be deallocated
-std::queue cp0EventRemoveList;
-
 static std::string miscRegNames[NumMiscRegs];

   public:
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index b869a92..0ef79a4 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -588,7 +588,7 @@

 X86ISA::Interrupts::Interrupts(Params * p)
 : BasicPioDevice(p, PageBytes), IntDevice(this, p->int_latency),
-  apicTimerEvent(this),
+  apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
   pendingSmi(false), smiVector(0),
   pendingNmi(false), nmiVector(0),
   pendingExtInt(false), extIntVector(0),
@@ -767,3 +767,9 @@
 {
 return new X86ISA::Interrupts(this);
 }
+
+void
+X86ISA::Interrupts::processApicTimerEvent() {
+if (triggerTimerInterrupt())
+setReg(APIC_INITIAL_COUNT, readReg(APIC_INITIAL_COUNT));
+}
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 26699b0..bfd1889 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -92,26 +92,8 @@
 /*
  * Timing related stuff.
  */
-class ApicTimerEvent : public Event
-{
-  private:
-Interrupts *localApic;
-  public:
-ApicTimerEvent(Interrupts *_localApic) :
-Event(), localApic(_localApic)
-{}
-
-void process()
-{
-assert(localApic);
-if (localApic->triggerTimerInterrupt()) {
-localApic->setReg(APIC_INITIAL_COUNT,
-localApic->readReg(APIC_INITIAL_COUNT));
-}
-}
-};
-
-ApicTimerEvent apicTimerEvent;
+EventFunctionWrapper apicTimerEvent;
+void processApicTimerEvent();

 /*
  * A set of variables to keep track of interrupts that don't go through

--
To view, visit 

[gem5-dev] Change in public/gem5[master]: gpu-compute: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3922



Change subject: gpu-compute: Refactor some Event subclasses to lambdas
..

gpu-compute: Refactor some Event subclasses to lambdas

Change-Id: Ic1332b8e8ba0afacbe591c80f4d06afbf5f04bd9
Signed-off-by: Sean Wilson 
---
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/dispatcher.cc
M src/gpu-compute/dispatcher.hh
M src/gpu-compute/shader.cc
M src/gpu-compute/shader.hh
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/tlb_coalescer.hh
8 files changed, 95 insertions(+), 199 deletions(-)



diff --git a/src/gpu-compute/compute_unit.cc  
b/src/gpu-compute/compute_unit.cc

index ffa5243..87f29eb 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -669,9 +669,8 @@
 return true;
 }

-ComputeUnit::DataPort::MemRespEvent *mem_resp_event =
-new  
ComputeUnit::DataPort::MemRespEvent(computeUnit->memPort[index],

-pkt);
+EventFunctionWrapper *mem_resp_event =
+computeUnit->memPort[index]->createMemRespEvent(pkt);

 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x received!\n",
 computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
@@ -845,8 +844,8 @@

 // translation is done. Schedule the mem_req_event at the
 // appropriate cycle to send the timing memory request to ruby
-ComputeUnit::DataPort::MemReqEvent *mem_req_event =
-new ComputeUnit::DataPort::MemReqEvent(memPort[index],  
pkt);

+EventFunctionWrapper *mem_req_event =
+memPort[index]->createMemReqEvent(pkt);

 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x data "
 "scheduled\n", cu_id, gpuDynInst->simdId,
@@ -923,8 +922,8 @@
 void
 ComputeUnit::sendSyncRequest(GPUDynInstPtr gpuDynInst, int index,  
PacketPtr pkt)

 {
-ComputeUnit::DataPort::MemReqEvent *mem_req_event =
-new ComputeUnit::DataPort::MemReqEvent(memPort[index], pkt);
+EventFunctionWrapper *mem_req_event =
+memPort[index]->createMemReqEvent(pkt);


 // New SenderState for the memory access
@@ -972,26 +971,20 @@
 sendSyncRequest(gpuDynInst, 0, pkt);
 }

-const char*
-ComputeUnit::DataPort::MemRespEvent::description() const
-{
-return "ComputeUnit memory response event";
-}
-
 void
-ComputeUnit::DataPort::MemRespEvent::process()
+ComputeUnit::DataPort::processMemRespEvent(PacketPtr pkt)
 {
 DataPort::SenderState *sender_state =
 safe_cast(pkt->senderState);

 GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst;
-ComputeUnit *compute_unit = dataPort->computeUnit;
+ComputeUnit *compute_unit = computeUnit;

 assert(gpuDynInst);

 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: Response for addr %#x, index %d\n",
 compute_unit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
-pkt->req->getPaddr(), dataPort->index);
+pkt->req->getPaddr(), index);

 Addr paddr = pkt->req->getPaddr();

@@ -1045,8 +1038,9 @@
 // this memory request
 if (gpuDynInst->useContinuation) {
 assert(!gpuDynInst->isNoScope());
- 
gpuDynInst->execContinuation(gpuDynInst->staticInstruction(),

- gpuDynInst);
+gpuDynInst->execContinuation(
+gpuDynInst->staticInstruction(),
+gpuDynInst);
 }
 }
 }
@@ -1230,9 +1224,8 @@

 // translation is done. Schedule the mem_req_event at the appropriate
 // cycle to send the timing memory request to ruby
-ComputeUnit::DataPort::MemReqEvent *mem_req_event =
-new  
ComputeUnit::DataPort::MemReqEvent(computeUnit->memPort[mp_index],

-   new_pkt);
+EventFunctionWrapper *mem_req_event =
+computeUnit->memPort[mp_index]->createMemReqEvent(new_pkt);

 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x data  
scheduled\n",

 computeUnit->cu_id, gpuDynInst->simdId,
@@ -1244,32 +1237,42 @@
 return true;
 }

-const char*
-ComputeUnit::DataPort::MemReqEvent::description() const
+EventFunctionWrapper*
+ComputeUnit::DataPort::createMemReqEvent(PacketPtr pkt)
 {
-return "ComputeUnit memory request event";
+return new EventFunctionWrapper(
+[this, pkt]{ processMemReqEvent(pkt); },
+"ComputeUnit memory request event", true);
+}
+
+EventFunctionWrapper*
+ComputeUnit::DataPort::createMemRespEvent(PacketPtr pkt)
+{
+return new EventFunctionWrapper(
+[this, pkt]{ processMemRespEvent(pkt); },
+"ComputeUnit memory response event", true);
 }

 void

[gem5-dev] Change in public/gem5[master]: cpu: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3923



Change subject: cpu: Refactor some Event subclasses to lambdas
..

cpu: Refactor some Event subclasses to lambdas

Change-Id: If765c6100d67556f157e4e61aa33c2b7eeb8d2f0
Signed-off-by: Sean Wilson 
---
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
10 files changed, 30 insertions(+), 138 deletions(-)



diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 6f460d3..8543841 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -248,7 +248,9 @@

 if (FullSystem) {
 if (params()->profile)
-profileEvent = new ProfileEvent(this, params()->profile);
+profileEvent = new EventFunctionWrapper(
+[this]{ processProfileEvent(params()->profile); },
+name());
 }
 tracer = params()->tracer;

@@ -658,21 +660,15 @@
 }
 }

-
-BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
-: cpu(_cpu), interval(_interval)
-{ }
-
 void
-BaseCPU::ProfileEvent::process()
+BaseCPU::processProfileEvent(Tick interval)
 {
-ThreadID size = cpu->threadContexts.size();
-for (ThreadID i = 0; i < size; ++i) {
-ThreadContext *tc = cpu->threadContexts[i];
-tc->profileSample();
-}
+ThreadID size = threadContexts.size();

-cpu->schedule(this, curTick() + interval);
+for (ThreadID i = 0; i < size; ++i)
+threadContexts[i]->profileSample();
+
+schedule(profileEvent, curTick() + interval);
 }

 void
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 14dfc26..6ce3122 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -248,17 +248,8 @@
 return FullSystem &&  
interrupts[tc->threadId()]->checkInterrupts(tc);

 }

-class ProfileEvent : public Event
-{
-  private:
-BaseCPU *cpu;
-Tick interval;
-
-  public:
-ProfileEvent(BaseCPU *cpu, Tick interval);
-void process();
-};
-ProfileEvent *profileEvent;
+void processProfileEvent(Tick interval);
+EventFunctionWrapper * profileEvent;

   protected:
 std::vector threadContexts;
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index 3b70c53..bf26120 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -321,7 +321,8 @@
 LSQ::SplitDataRequest::SplitDataRequest(LSQ _, MinorDynInstPtr inst_,
 bool isLoad_, PacketDataPtr data_, uint64_t *res_) :
 LSQRequest(port_, inst_, isLoad_, data_, res_),
-translationEvent(*this),
+translationEvent([this]{ sendNextFragmentToTranslation(); },
+ "translationEvent"),
 numFragments(0),
 numInTranslationFragments(0),
 numTranslatedFragments(0),
diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh
index 1a90948..d4973f5 100644
--- a/src/cpu/minor/lsq.hh
+++ b/src/cpu/minor/lsq.hh
@@ -377,20 +377,7 @@
 {
   protected:
 /** Event to step between translations */
-class TranslationEvent : public Event
-{
-  protected:
-SplitDataRequest 
-
-  public:
-TranslationEvent(SplitDataRequest _)
-: owner(owner_) { }
-
-void process()
-{ owner.sendNextFragmentToTranslation(); }
-};
-
-TranslationEvent translationEvent;
+EventFunctionWrapper translationEvent;
   protected:
 /** Number of fragments this request is split into */
 unsigned int numFragments;
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 3cce7f6..38f1671 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -101,21 +101,6 @@

 typedef O3ThreadState Thread;

-/** Event class used to schedule a squash due to a trap (fault or
- * interrupt) to happen on a specific cycle.
- */
-class TrapEvent : public Event {
-  private:
-DefaultCommit *commit;
-ThreadID tid;
-
-  public:
-TrapEvent(DefaultCommit *_commit, ThreadID _tid);
-
-void process();
-const char *description() const;
-};
-
 /** Overall commit status. Used to determine if the CPU can deschedule
  * itself due to a lack of activity.
  */
@@ -157,6 +142,9 @@
 /** To probe when an instruction is squashed */
 ProbePointArg *ppSquash;

+/** Mark the thread as processing a trap. */
+void processTrapEvent(ThreadID tid);
+
   public:
 /** Construct a DefaultCommit with the given parameters. */
 DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index ea77f18..aa6ad23 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -71,26 +71,12 @@
 using namespace std;

 

[gem5-dev] Change in public/gem5[master]: ruby: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3930



Change subject: ruby: Refactor some Event subclasses to lambdas
..

ruby: Refactor some Event subclasses to lambdas

Change-Id: I9f47a20a869553515a759d9a29c05f6ce4b42d64
Signed-off-by: Sean Wilson 
---
M src/mem/ruby/common/Consumer.cc
M src/mem/ruby/common/Consumer.hh
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/RubySystem.cc
M src/mem/ruby/system/RubySystem.hh
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
8 files changed, 20 insertions(+), 96 deletions(-)



diff --git a/src/mem/ruby/common/Consumer.cc  
b/src/mem/ruby/common/Consumer.cc

index 59605d5..f68ee14 100644
--- a/src/mem/ruby/common/Consumer.cc
+++ b/src/mem/ruby/common/Consumer.cc
@@ -41,7 +41,9 @@
 {
 if (!alreadyScheduled(evt_time)) {
 // This wakeup is not redundant
-ConsumerEvent *evt = new ConsumerEvent(this);
+auto *evt = new EventFunctionWrapper(
+[this]{ wakeup(); }, "Consumer Event", true);
+
 em->schedule(evt, evt_time);
 insertScheduledWakeupTime(evt_time);
 }
diff --git a/src/mem/ruby/common/Consumer.hh  
b/src/mem/ruby/common/Consumer.hh

index 20f2bdd..b0d35bf 100644
--- a/src/mem/ruby/common/Consumer.hh
+++ b/src/mem/ruby/common/Consumer.hh
@@ -76,20 +76,6 @@
   private:
 std::set m_scheduled_wakeups;
 ClockedObject *em;
-
-class ConsumerEvent : public Event
-{
-  public:
-  ConsumerEvent(Consumer* _consumer)
-  : Event(Default_Pri, AutoDelete), m_consumer_ptr(_consumer)
-  {
-  }
-
-  void process() { m_consumer_ptr->wakeup(); }
-
-  private:
-  Consumer* m_consumer_ptr;
-};
 };

 inline std::ostream&
diff --git a/src/mem/ruby/system/GPUCoalescer.cc  
b/src/mem/ruby/system/GPUCoalescer.cc

index 991b217..a615c40 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -116,7 +116,10 @@
 }

 GPUCoalescer::GPUCoalescer(const Params *p)
-: RubyPort(p), issueEvent(this), deadlockCheckEvent(this)
+: RubyPort(p),
+  issueEvent([this]{ completeIssue(); }, "Issue coalesced request",
+ false, Event::Progress_Event_Pri),
+  deadlockCheckEvent([this]{ wakeup(); }, "GPUCoalescer deadlock  
check")

 {
 m_store_waiting_on_load_cycles = 0;
 m_store_waiting_on_store_cycles = 0;
@@ -996,11 +999,6 @@
 SequencerRequestType_to_string(requestType));
 }

-GPUCoalescer::IssueEvent::IssueEvent(GPUCoalescer* _seq)
-: Event(Progress_Event_Pri), seq(_seq)
-{
-}
-

 void
 GPUCoalescer::completeIssue()
@@ -1042,18 +1040,6 @@
 }

 void
-GPUCoalescer::IssueEvent::process()
-{
-seq->completeIssue();
-}
-
-const char *
-GPUCoalescer::IssueEvent::description() const
-{
-return "Issue coalesced request";
-}
-
-void
 GPUCoalescer::evictionCallback(Addr address)
 {
 ruby_eviction_callback(address);
diff --git a/src/mem/ruby/system/GPUCoalescer.hh  
b/src/mem/ruby/system/GPUCoalescer.hh

index 2b42e19..8946838 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -255,17 +255,7 @@

 bool handleLlsc(Addr address, GPUCoalescerRequest* request);

-class IssueEvent : public Event
-{
-  private:
-GPUCoalescer *seq;
-  public:
-IssueEvent(GPUCoalescer *_seq);
-void process();
-const char *description() const;
-};
-
-IssueEvent issueEvent;
+EventFunctionWrapper issueEvent;


   // Changed to protected to enable inheritance by VIPER Coalescer
@@ -305,22 +295,7 @@

 bool m_runningGarnetStandalone;

-class GPUCoalescerWakeupEvent : public Event
-{
-  private:
-GPUCoalescer *m_GPUCoalescer_ptr;
-
-  public:
-GPUCoalescerWakeupEvent(GPUCoalescer *_seq) :
-m_GPUCoalescer_ptr(_seq) {}
-void process() { m_GPUCoalescer_ptr->wakeup(); }
-const char *description() const
-{
-return "GPUCoalescer deadlock check";
-}
-};
-
-GPUCoalescerWakeupEvent deadlockCheckEvent;
+EventFunctionWrapper deadlockCheckEvent;
 bool assumingRfOCoherence;

 // m5 style stats for TCP hit/miss counts
@@ -382,4 +357,3 @@
 }

 #endif // __MEM_RUBY_SYSTEM_GPU_COALESCER_HH__
-
diff --git a/src/mem/ruby/system/RubySystem.cc  
b/src/mem/ruby/system/RubySystem.cc

index e1717e5..3d0470c 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -380,12 +380,12 @@
 }

 void
-RubySystem::RubyEvent::process()
+RubySystem::processRubyEvent()
 {
-if (RubySystem::getWarmupEnabled()) {
-m_ruby_system->m_cache_recorder->enqueueNextFetchRequest();
-} else if (RubySystem::getCooldownEnabled()) {
-m_ruby_system->m_cache_recorder->enqueueNextFlushRequest();
+ 

[gem5-dev] Change in public/gem5[master]: testers: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3926



Change subject: testers: Refactor some Event subclasses to lambdas
..

testers: Refactor some Event subclasses to lambdas

Change-Id: I897b6162a827216b7bad74d955c0e50e06a5a3ec
Signed-off-by: Sean Wilson 
---
M src/cpu/testers/directedtest/RubyDirectedTester.cc
M src/cpu/testers/directedtest/RubyDirectedTester.hh
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/rubytest/RubyTester.hh
6 files changed, 11 insertions(+), 49 deletions(-)



diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc  
b/src/cpu/testers/directedtest/RubyDirectedTester.cc

index 667d50f..ef13337 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.cc
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc
@@ -47,7 +47,9 @@
 #include "sim/sim_exit.hh"

 RubyDirectedTester::RubyDirectedTester(const Params *p)
-  : MemObject(p), directedStartEvent(this),
+  : MemObject(p),
+directedStartEvent([this]{ wakeup(); }, "Directed tick",
+   false, Event::CPU_Tick_Pri),
 m_requests_to_complete(p->requests_to_complete),
 generator(p->generator)
 {
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh  
b/src/cpu/testers/directedtest/RubyDirectedTester.hh

index 74a8911..00278a6 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.hh
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh
@@ -85,20 +85,7 @@
 void print(std::ostream& out) const;

   protected:
-class DirectedStartEvent : public Event
-{
-  private:
-RubyDirectedTester *tester;
-
-  public:
-DirectedStartEvent(RubyDirectedTester *_tester)
-: Event(CPU_Tick_Pri), tester(_tester)
-{}
-void process() { tester->wakeup(); }
-virtual const char *description() const { return "Directed tick"; }
-};
-
-DirectedStartEvent directedStartEvent;
+EventFunctionWrapper directedStartEvent;

   private:
 void hitCallback(NodeID proc, Addr addr);
diff --git  
a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc  
b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc

index 0f8c877..1345fe9 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
@@ -76,7 +76,8 @@

 GarnetSyntheticTraffic::GarnetSyntheticTraffic(const Params *p)
 : MemObject(p),
-  tickEvent(this),
+  tickEvent([this]{ tick(); }, "GarnetSyntheticTraffic tick",
+false, Event::CPU_Tick_Pri),
   cachePort("GarnetSyntheticTraffic", this),
   retryPkt(NULL),
   size(p->memory_size),
diff --git  
a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh  
b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh

index 94eee44..3da7e27 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
@@ -74,21 +74,7 @@
 void printAddr(Addr a);

   protected:
-class TickEvent : public Event
-{
-  private:
-GarnetSyntheticTraffic *cpu;
-
-  public:
-TickEvent(GarnetSyntheticTraffic *c) : Event(CPU_Tick_Pri), cpu(c)  
{}

-void process() { cpu->tick(); }
-virtual const char *description() const
-{
-return "GarnetSyntheticTraffic tick";
-}
-};
-
-TickEvent tickEvent;
+EventFunctionWrapper tickEvent;

 class CpuPort : public MasterPort
 {
@@ -160,6 +146,3 @@
 };

 #endif // __CPU_GARNET_SYNTHETIC_TRAFFIC_HH__
-
-
-
diff --git a/src/cpu/testers/rubytest/RubyTester.cc  
b/src/cpu/testers/rubytest/RubyTester.cc

index baf2b7e..712d15d 100644
--- a/src/cpu/testers/rubytest/RubyTester.cc
+++ b/src/cpu/testers/rubytest/RubyTester.cc
@@ -50,7 +50,9 @@
 #include "sim/system.hh"

 RubyTester::RubyTester(const Params *p)
-  : MemObject(p), checkStartEvent(this),
+  : MemObject(p),
+checkStartEvent([this]{ wakeup(); }, "RubyTester tick",
+false, Event::CPU_Tick_Pri),
 _masterId(p->system->getMasterId(name())),
 m_checkTable_ptr(nullptr),
 m_num_cpus(p->num_cpus),
diff --git a/src/cpu/testers/rubytest/RubyTester.hh  
b/src/cpu/testers/rubytest/RubyTester.hh

index 39e6d78..0070359 100644
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/testers/rubytest/RubyTester.hh
@@ -118,20 +118,7 @@

 MasterID masterId() { return _masterId; }
   protected:
-class CheckStartEvent : public Event
-{
-  private:
-RubyTester *tester;
-
-  public:
-CheckStartEvent(RubyTester *_tester)
-: Event(CPU_Tick_Pri), tester(_tester)
-

[gem5-dev] Change in public/gem5[master]: dev: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3928



Change subject: dev: Refactor some Event subclasses to lambdas
..

dev: Refactor some Event subclasses to lambdas

Change-Id: I965d31ff8ad1658b03a902bf4244d7d0977b0466
Signed-off-by: Sean Wilson 
---
M src/dev/dma_device.hh
M src/dev/uart8250.cc
M src/dev/uart8250.hh
3 files changed, 21 insertions(+), 59 deletions(-)



diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index f354d38..0dc79df 100644
--- a/src/dev/dma_device.hh
+++ b/src/dev/dma_device.hh
@@ -240,22 +240,6 @@
 }
 }

-/**
- * Event invoked by DmaDevice on completion of each chunk.
- */
-class DmaChunkEvent : public Event
-{
-  private:
-DmaCallback *callback;
-
-  public:
-DmaChunkEvent(DmaCallback *cb)
-  : Event(Default_Pri, AutoDelete), callback(cb)
-{ }
-
-void process() { callback->chunkComplete(); }
-};
-
   public:

 /**
@@ -265,7 +249,8 @@
 Event *getChunkEvent()
 {
 ++count;
-return new DmaChunkEvent(this);
+return new EventFunctionWrapper([this]{ chunkComplete(); }, name(),
+true);
 }
 };

diff --git a/src/dev/uart8250.cc b/src/dev/uart8250.cc
index 3c97604..8ee763f 100644
--- a/src/dev/uart8250.cc
+++ b/src/dev/uart8250.cc
@@ -49,27 +49,14 @@
 using namespace std;
 using namespace TheISA;

-Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
-: uart(u)
-{
-DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
-intrBit = bit;
-}
-
-const char *
-Uart8250::IntrEvent::description() const
-{
-return "uart interrupt delay";
-}
-
 void
-Uart8250::IntrEvent::process()
+Uart8250::processIntrEvent(int intrBit)
 {
-if (intrBit & uart->IER) {
+if (intrBit & IER) {
DPRINTF(Uart, "UART InterEvent, interrupting\n");
-   uart->platform->postConsoleInt();
-   uart->status |= intrBit;
-   uart->lastTxInt = curTick();
+   platform->postConsoleInt();
+   status |= intrBit;
+   lastTxInt = curTick();
 }
 else
DPRINTF(Uart, "UART InterEvent, not interrupting\n");
@@ -89,21 +76,20 @@
  * character to send to alleviate this problem. --Ali
  */
 void
-Uart8250::IntrEvent::scheduleIntr()
+Uart8250::scheduleIntr(Event *event)
 {
 static const Tick interval = 225 * SimClock::Int::ns;
-DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n",  
intrBit,

-curTick() + interval);
-if (!scheduled())
-uart->schedule(this, curTick() + interval);
+if (!event->scheduled())
+schedule(event, curTick() + interval);
 else
-uart->reschedule(this, curTick() + interval);
+reschedule(event, curTick() + interval);
 }


 Uart8250::Uart8250(const Params *p)
 : Uart(p, 8), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
-  txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
+  txIntrEvent([this]{ processIntrEvent(TX_INT); }, "uart interrupt  
delay"),
+  rxIntrEvent([this]{ processIntrEvent(RX_INT); }, "uart interrupt  
delay")

 {
 }

@@ -131,7 +117,7 @@
 platform->clearConsoleInt();

 if (term->dataAvailable() && (IER & UART_IER_RDI))
-rxIntrEvent.scheduleIntr();
+scheduleIntr();
 } else { // dll divisor latch
;
 }
@@ -206,7 +192,7 @@
 platform->clearConsoleInt();
 status &= ~TX_INT;
 if (UART_IER_THRI & IER)
-txIntrEvent.scheduleIntr();
+scheduleIntr();
 } else { // dll divisor latch
;
 }
@@ -224,7 +210,7 @@
 } else {
 DPRINTF(Uart, "-- Delaying interrupt... %d,%d\n",
 curTick(), lastTxInt);
-txIntrEvent.scheduleIntr();
+scheduleIntr();
 }
 }
 else
@@ -239,7 +225,7 @@

 if ((UART_IER_RDI & IER) && term->dataAvailable()) {
 DPRINTF(Uart, "IER: IER_RDI set, scheduling RX  
intrrupt\n");

-rxIntrEvent.scheduleIntr();
+scheduleIntr();
 } else {
 DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX  
intrrupt\n");

 if (rxIntrEvent.scheduled())
diff --git a/src/dev/uart8250.hh b/src/dev/uart8250.hh
index ac1..b7fefc5 100644
--- a/src/dev/uart8250.hh
+++ b/src/dev/uart8250.hh
@@ -73,20 +73,11 @@
 uint8_t IER, DLAB, LCR, MCR;
 Tick lastTxInt;

-class IntrEvent : public Event
-{
-protected:
-Uart8250 *uart;
-int intrBit;
-public:
-IntrEvent(Uart8250 *u, int bit);

[gem5-dev] Change in public/gem5[master]: arm: Refactor some Event subclasses to lambdas

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3929



Change subject: arm: Refactor some Event subclasses to lambdas
..

arm: Refactor some Event subclasses to lambdas

Change-Id: Ic59add8afee1d49633634272d9687a4b1558537e
Signed-off-by: Sean Wilson 
---
M src/dev/arm/gic_pl390.cc
M src/dev/arm/gic_pl390.hh
M src/dev/arm/vgic.cc
M src/dev/arm/vgic.hh
4 files changed, 18 insertions(+), 32 deletions(-)



diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc
index 7b63306..22dc90e 100644
--- a/src/dev/arm/gic_pl390.cc
+++ b/src/dev/arm/gic_pl390.cc
@@ -87,7 +87,9 @@
 cpuBpr[x] = GICC_BPR_MINIMUM;
 // Initialize cpu highest int
 cpuHighestInt[x] = SPURIOUS_INT;
-postIntEvent[x] = new PostIntEvent(*this, x);
+postIntEvent[x] =
+new EventFunctionWrapper([this, x]{ postDelayedInt(x); },
+ "Post Interrupt to CPU");
 }
 DPRINTF(Interrupt, "cpuEnabled[0]=%d cpuEnabled[1]=%d\n",  
cpuEnabled[0],

 cpuEnabled[1]);
diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh
index 5c8a712..d11e0f0 100644
--- a/src/dev/arm/gic_pl390.hh
+++ b/src/dev/arm/gic_pl390.hh
@@ -340,21 +340,7 @@
  */
 void postDelayedInt(uint32_t cpu);

-/** Event definition to post interrupt to CPU after a delay
-*/
-class PostIntEvent : public Event
-{
-  private:
-Pl390 
-uint32_t cpu;
-  public:
-PostIntEvent(Pl390 &_parent, uint32_t _cpu)
-: parent(_parent), cpu(_cpu)
-{ }
-void process() { parent.postDelayedInt(cpu); }
-const char *description() const { return "Post Interrupt to CPU"; }
-};
-PostIntEvent *postIntEvent[CPU_MAX];
+EventFunctionWrapper *postIntEvent[CPU_MAX];
 int pendingDelayedInterrupts;

   public:
diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc
index 6744ad5..a641545 100644
--- a/src/dev/arm/vgic.cc
+++ b/src/dev/arm/vgic.cc
@@ -53,7 +53,10 @@
   maintInt(p->ppint)
 {
 for (int x = 0; x < VGIC_CPU_MAX; x++) {
-postVIntEvent[x] = new PostVIntEvent(x, p->platform);
+auto tempPlatform = p->platform;
+postVIntEvent[x] = new EventFunctionWrapper(
+[x, tempPlatform]{ processPostVIntEvent(x, tempPlatform); },
+"Post VInterrupt to CPU");
 maintIntPosted[x] = false;
 vIntPosted[x] = false;
 }
@@ -369,6 +372,13 @@
 }

 void
+VGic::processPostVIntEvent(uint32_t cpu, Platform *platform)
+{
+ platform->intrctrl->post(cpu, ArmISA::INT_VIRT_IRQ, 0);
+}
+
+
+void
 VGic::postMaintInt(uint32_t cpu)
 {
 DPRINTF(VGIC, "Posting maintenance PPI to GIC/cpu%d\n", cpu);
diff --git a/src/dev/arm/vgic.hh b/src/dev/arm/vgic.hh
index e9bc29c..4973fdd 100644
--- a/src/dev/arm/vgic.hh
+++ b/src/dev/arm/vgic.hh
@@ -104,22 +104,10 @@
 static const uint32_t LR_PENDING= 1;
 static const uint32_t LR_ACTIVE = 2;

-/** Event definition to post interrupt to CPU after a delay
-*/
-class PostVIntEvent : public Event
-{
-  private:
-uint32_t cpu;
-Platform *platform;
-  public:
-PostVIntEvent( uint32_t c, Platform* p)
-: cpu(c), platform(p)
-{ }
-void process() { platform->intrctrl->post(cpu,  
ArmISA::INT_VIRT_IRQ, 0);}
-const char *description() const { return "Post VInterrupt to CPU";  
}

-};
+/** Post interrupt to CPU */
+static void processPostVIntEvent(uint32_t cpu, Platform *platform);

-PostVIntEvent *postVIntEvent[VGIC_CPU_MAX];
+EventFunctionWrapper *postVIntEvent[VGIC_CPU_MAX];
 boolmaintIntPosted[VGIC_CPU_MAX];
 boolvIntPosted[VGIC_CPU_MAX];


--
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Gerrit-Change-Id: Ic59add8afee1d49633634272d9687a4b1558537e
Gerrit-Change-Number: 3929
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[gem5-dev] Change in public/gem5[master]: arm: Fix memleak in VGic by adding destructor

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3900 )


Change subject: arm: Fix memleak in VGic by adding destructor
..

arm: Fix memleak in VGic by adding destructor

Change-Id: I864b5d9ed655cc52e440e2eb54987e8ff9a73296
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3900
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/dev/arm/vgic.cc
M src/dev/arm/vgic.hh
2 files changed, 7 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc
index 60866f1..6744ad5 100644
--- a/src/dev/arm/vgic.cc
+++ b/src/dev/arm/vgic.cc
@@ -60,6 +60,12 @@
 assert(sys->numRunningContexts() <= VGIC_CPU_MAX);
 }

+VGic::~VGic()
+{
+for (int x = 0; x < VGIC_CPU_MAX; x++)
+delete postVIntEvent[x];
+}
+
 Tick
 VGic::read(PacketPtr pkt)
 {
diff --git a/src/dev/arm/vgic.hh b/src/dev/arm/vgic.hh
index 8328673..e9bc29c 100644
--- a/src/dev/arm/vgic.hh
+++ b/src/dev/arm/vgic.hh
@@ -206,6 +206,7 @@
 return dynamic_cast(_params);
 }
 VGic(const Params *p);
+~VGic();

 AddrRangeList getAddrRanges() const override;


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I864b5d9ed655cc52e440e2eb54987e8ff9a73296
Gerrit-Change-Number: 3900
Gerrit-PatchSet: 2
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: arm: Fix memleak in Pl390 by adding destructor

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3901 )


Change subject: arm: Fix memleak in Pl390 by adding destructor
..

arm: Fix memleak in Pl390 by adding destructor

Change-Id: I3395e64311f6aa7bbfb6eee9bfec82e832bcbd4d
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3901
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/dev/arm/gic_pl390.cc
M src/dev/arm/gic_pl390.hh
2 files changed, 7 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc
index ce27e94..7b63306 100644
--- a/src/dev/arm/gic_pl390.cc
+++ b/src/dev/arm/gic_pl390.cc
@@ -95,6 +95,12 @@
 gem5ExtensionsEnabled = false;
 }

+Pl390::~Pl390()
+{
+for (int x = 0; x < CPU_MAX; x++)
+delete postIntEvent[x];
+}
+
 Tick
 Pl390::read(PacketPtr pkt)
 {
diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh
index 05c9b5f..5c8a712 100644
--- a/src/dev/arm/gic_pl390.hh
+++ b/src/dev/arm/gic_pl390.hh
@@ -365,6 +365,7 @@
 return dynamic_cast(_params);
 }
 Pl390(const Params *p);
+~Pl390();

 DrainState drain() override;


--
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Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I3395e64311f6aa7bbfb6eee9bfec82e832bcbd4d
Gerrit-Change-Number: 3901
Gerrit-PatchSet: 2
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Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: sim, x86: Make clone a virtual function

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3902



Change subject: sim, x86: Make clone a virtual function
..

sim, x86: Make clone a virtual function

This fixes the function call to clone in syscall_emul.hh where
the x86 version should be called before the base implementation
of clone.

Change-Id: Iccd2f680ff6e3a5536037d688a80ab3f236bbd98
Signed-off-by: Sean Wilson 
---
M src/arch/x86/process.hh
M src/sim/process.hh
2 files changed, 5 insertions(+), 5 deletions(-)



diff --git a/src/arch/x86/process.hh b/src/arch/x86/process.hh
index 9cd5378..3eb9620 100644
--- a/src/arch/x86/process.hh
+++ b/src/arch/x86/process.hh
@@ -84,7 +84,7 @@
 void setSyscallReturn(ThreadContext *tc,
   SyscallReturn return_value) override;
 void clone(ThreadContext *old_tc, ThreadContext *new_tc,
-   Process *process, TheISA::IntReg flags);
+   Process *process, TheISA::IntReg flags) override;

 X86Process &
 operator=(const X86Process )
@@ -140,7 +140,7 @@
 void setSyscallArg(ThreadContext *tc, int i,
X86ISA::IntReg val) override;
 void clone(ThreadContext *old_tc, ThreadContext *new_tc,
-   Process *process, TheISA::IntReg flags);
+   Process *process, TheISA::IntReg flags) override;
 };

 class I386Process : public X86Process
@@ -186,7 +186,7 @@
 void setSyscallArg(ThreadContext *tc, int i,
X86ISA::IntReg val) override;
 void clone(ThreadContext *old_tc, ThreadContext *new_tc,
-   Process *process, TheISA::IntReg flags);
+   Process *process, TheISA::IntReg flags) override;
 };

 /**
diff --git a/src/sim/process.hh b/src/sim/process.hh
index 5da30a4..e4a52e3 100644
--- a/src/sim/process.hh
+++ b/src/sim/process.hh
@@ -161,8 +161,8 @@
 void replicatePage(Addr vaddr, Addr new_paddr, ThreadContext *old_tc,
ThreadContext *new_tc, bool alloc_page);

-void clone(ThreadContext *old_tc, ThreadContext *new_tc, Process  
*new_p,

-   TheISA::IntReg flags);
+virtual void clone(ThreadContext *old_tc, ThreadContext *new_tc,
+   Process *new_p, TheISA::IntReg flags);

 // thread contexts associated with this process
 std::vector contextIds;

--
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[gem5-dev] Change in public/gem5[master]: arm: Fix memleak in VGic by adding destructor

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3900



Change subject: arm: Fix memleak in VGic by adding destructor
..

arm: Fix memleak in VGic by adding destructor

Change-Id: I864b5d9ed655cc52e440e2eb54987e8ff9a73296
Signed-off-by: Sean Wilson 
---
M src/dev/arm/vgic.cc
M src/dev/arm/vgic.hh
2 files changed, 7 insertions(+), 0 deletions(-)



diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc
index 60866f1..6744ad5 100644
--- a/src/dev/arm/vgic.cc
+++ b/src/dev/arm/vgic.cc
@@ -60,6 +60,12 @@
 assert(sys->numRunningContexts() <= VGIC_CPU_MAX);
 }

+VGic::~VGic()
+{
+for (int x = 0; x < VGIC_CPU_MAX; x++)
+delete postVIntEvent[x];
+}
+
 Tick
 VGic::read(PacketPtr pkt)
 {
diff --git a/src/dev/arm/vgic.hh b/src/dev/arm/vgic.hh
index 8328673..e9bc29c 100644
--- a/src/dev/arm/vgic.hh
+++ b/src/dev/arm/vgic.hh
@@ -206,6 +206,7 @@
 return dynamic_cast(_params);
 }
 VGic(const Params *p);
+~VGic();

 AddrRangeList getAddrRanges() const override;


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[gem5-dev] Change in public/gem5[master]: arm: Fix memleak in Pl390 by adding destructor

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3901



Change subject: arm: Fix memleak in Pl390 by adding destructor
..

arm: Fix memleak in Pl390 by adding destructor

Change-Id: I3395e64311f6aa7bbfb6eee9bfec82e832bcbd4d
Signed-off-by: Sean Wilson 
---
M src/dev/arm/gic_pl390.cc
M src/dev/arm/gic_pl390.hh
2 files changed, 7 insertions(+), 0 deletions(-)



diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc
index ce27e94..7b63306 100644
--- a/src/dev/arm/gic_pl390.cc
+++ b/src/dev/arm/gic_pl390.cc
@@ -95,6 +95,12 @@
 gem5ExtensionsEnabled = false;
 }

+Pl390::~Pl390()
+{
+for (int x = 0; x < CPU_MAX; x++)
+delete postIntEvent[x];
+}
+
 Tick
 Pl390::read(PacketPtr pkt)
 {
diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh
index 05c9b5f..5c8a712 100644
--- a/src/dev/arm/gic_pl390.hh
+++ b/src/dev/arm/gic_pl390.hh
@@ -365,6 +365,7 @@
 return dynamic_cast(_params);
 }
 Pl390(const Params *p);
+~Pl390();

 DrainState drain() override;


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[gem5-dev] Change in public/gem5[master]: mem: Replace EventWrapper in PacketQueue with EventFunctionW...

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3744 )


Change subject: mem: Replace EventWrapper in PacketQueue with  
EventFunctionWrapper

..

mem: Replace EventWrapper in PacketQueue with EventFunctionWrapper

In order to replicate the same `name()` output with `PacketQueue`,  
subclasses
using EventFunctionWrapper must initialize PacketQueue with their own name  
so

the sendEvent holds the name of the subclass.

Change-Id: Ib091e118bab8858192e1d1370d61def42958ec29
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3744
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Jason Lowe-Power 
Maintainer: Nikos Nikoleris 
---
M src/mem/packet_queue.cc
M src/mem/packet_queue.hh
2 files changed, 32 insertions(+), 8 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/packet_queue.cc b/src/mem/packet_queue.cc
index f7df331..7649fe5 100644
--- a/src/mem/packet_queue.cc
+++ b/src/mem/packet_queue.cc
@@ -50,8 +50,10 @@
 using namespace std;

 PacketQueue::PacketQueue(EventManager& _em, const std::string& _label,
+ const std::string& _sendEventName,
  bool disable_sanity_check)
-: em(_em), sendEvent(this), _disableSanityCheck(disable_sanity_check),
+: em(_em), sendEvent([this]{ processSendEvent(); }, _sendEventName),
+  _disableSanityCheck(disable_sanity_check),
   label(_label), waitingOnRetry(false)
 {
 }
@@ -237,7 +239,8 @@

 ReqPacketQueue::ReqPacketQueue(EventManager& _em, MasterPort& _masterPort,
const std::string _label)
-: PacketQueue(_em, _label), masterPort(_masterPort)
+: PacketQueue(_em, _label, name(_masterPort, _label)),
+  masterPort(_masterPort)
 {
 }

@@ -250,7 +253,8 @@
 SnoopRespPacketQueue::SnoopRespPacketQueue(EventManager& _em,
MasterPort& _masterPort,
const std::string _label)
-: PacketQueue(_em, _label), masterPort(_masterPort)
+: PacketQueue(_em, _label, name(_masterPort, _label)),
+  masterPort(_masterPort)
 {
 }

@@ -262,7 +266,8 @@

 RespPacketQueue::RespPacketQueue(EventManager& _em, SlavePort& _slavePort,
  const std::string _label)
-: PacketQueue(_em, _label), slavePort(_slavePort)
+: PacketQueue(_em, _label, name(_slavePort, _label)),
+  slavePort(_slavePort)
 {
 }

diff --git a/src/mem/packet_queue.hh b/src/mem/packet_queue.hh
index b1001e7..f7379c9 100644
--- a/src/mem/packet_queue.hh
+++ b/src/mem/packet_queue.hh
@@ -87,7 +87,7 @@
 void processSendEvent();

 /** Event used to call processSendEvent. */
-EventWrapper sendEvent;
+EventFunctionWrapper sendEvent;

  /*
   * Optionally disable the sanity check
@@ -134,6 +134,7 @@
  *on the size of the transmitList. The check is enabled by  
default.

  */
 PacketQueue(EventManager& _em, const std::string& _label,
+const std::string& _sendEventName,
 bool disable_sanity_check = false);

 /**
@@ -215,6 +216,12 @@

 MasterPort& masterPort;

+// Static definition so it can be called when constructing the parent
+// without us being completely initialized.
+static const std::string name(const MasterPort& masterPort,
+  const std::string& label)
+{ return masterPort.name() + "-" + label; }
+
   public:

 /**
@@ -232,7 +239,7 @@
 virtual ~ReqPacketQueue() { }

 const std::string name() const
-{ return masterPort.name() + "-" + label; }
+{ return name(masterPort, label); }

 bool sendTiming(PacketPtr pkt);

@@ -245,6 +252,12 @@

 MasterPort& masterPort;

+// Static definition so it can be called when constructing the parent
+// without us being completely initialized.
+static const std::string name(const MasterPort& masterPort,
+  const std::string& label)
+{ return masterPort.name() + "-" + label; }
+
   public:

 /**
@@ -262,7 +275,7 @@
 virtual ~SnoopRespPacketQueue() { }

 const std::string name() const
-{ return masterPort.name() + "-" + label; }
+{ return name(masterPort, label); }

 bool sendTiming(PacketPtr pkt);

@@ -275,6 +288,12 @@

 SlavePort& slavePort;

+// Static definition so it can be called when constructing the parent
+// without us being completely initialized.
+static const std::string name(const SlavePort& slavePort,
+  const std::string& label)
+{ return slavePort.name() + "-" + label; }
+
   public:

 /**
@@ -292,7 

[gem5-dev] Change in public/gem5[master]: sim: Remove DelayFunction

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3741 )


Change subject: sim: Remove DelayFunction
..

sim: Remove DelayFunction

`DelayFunction` is unused.

Change-Id: I28aa756054c9b121fe4cfa65c393366f26ccb128
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3741
Reviewed-by: Andreas Sandberg 
Reviewed-by: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
---
M src/sim/eventq.hh
1 file changed, 0 insertions(+), 20 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index b138f56..9d3c5c3 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -769,26 +769,6 @@
 };

 template 
-void
-DelayFunction(EventQueue *eventq, Tick when, T *object)
-{
-class DelayEvent : public Event
-{
-  private:
-T *object;
-
-  public:
-DelayEvent(T *o)
-: Event(Default_Pri, AutoDelete), object(o)
-{ }
-void process() { (object->*F)(); }
-const char *description() const { return "delay"; }
-};
-
-eventq->schedule(new DelayEvent(object), when);
-}
-
-template 
 class EventWrapper : public Event
 {
   private:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I28aa756054c9b121fe4cfa65c393366f26ccb128
Gerrit-Change-Number: 3741
Gerrit-PatchSet: 3
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sean Wilson 
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[gem5-dev] Change in public/gem5[master]: dev: Replace EventWrapper use with EventFunctionWrapper

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3748 )


Change subject: dev: Replace EventWrapper use with EventFunctionWrapper
..

dev: Replace EventWrapper use with EventFunctionWrapper

Change-Id: I6b03cc6f67e76dffb79940431711ae6171901c6a
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3748
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/dev/arm/ufs_device.cc
M src/dev/arm/ufs_device.hh
M src/dev/dma_device.cc
M src/dev/dma_device.hh
M src/dev/net/dist_etherlink.hh
M src/dev/net/etherlink.cc
M src/dev/net/etherlink.hh
M src/dev/net/etherswitch.cc
M src/dev/net/etherswitch.hh
M src/dev/net/i8254xGBe.cc
M src/dev/net/i8254xGBe.hh
M src/dev/net/ns_gige.cc
M src/dev/net/ns_gige.hh
M src/dev/net/sinic.cc
M src/dev/net/sinic.hh
M src/dev/pci/copy_engine.cc
M src/dev/pci/copy_engine.hh
M src/dev/storage/ide_disk.cc
M src/dev/storage/ide_disk.hh
19 files changed, 123 insertions(+), 135 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/arm/ufs_device.cc b/src/dev/arm/ufs_device.cc
index 5a5a132..cd1bbca 100644
--- a/src/dev/arm/ufs_device.cc
+++ b/src/dev/arm/ufs_device.cc
@@ -733,8 +733,8 @@
 transferTrack(0),
 taskCommandTrack(0),
 idlePhaseStart(0),
-SCSIResumeEvent(this),
-UTPEvent(this)
+SCSIResumeEvent([this]{ SCSIStart(); }, name()),
+UTPEvent([this]{ finalUTP(); }, name())
 {
 DPRINTF(UFSHostDevice, "The hostcontroller hosts %d Logic units\n",
 lunAvail);
@@ -1280,7 +1280,8 @@
 task_info.size = size;
 task_info.done = UFSHCIMem.TMUTMRLDBR;
 taskInfo.push_back(task_info);
-taskEventQueue.push_back(this);
+taskEventQueue.push_back(
+EventFunctionWrapper([this]{ taskStart(); }, name()));
 writeDevice((), false, address, size,
 reinterpret_cast
 (().destination), 0, 0);
@@ -1328,7 +1329,8 @@
 UTPTransferReqDesc;
 DPRINTF(UFSHostDevice, "Initial transfer start: 0x%8x\n",
 transferstart_info.done);
-transferEventQueue.push_back(this);
+transferEventQueue.push_back(
+EventFunctionWrapper([this]{ transferStart(); }, name()));

 if (transferEventQueue.size() < 2) {
 writeDevice((), false,
@@ -2260,7 +2262,8 @@
 UFSDevice[this_lun]->clearReadSignal();
 SSDReadPending.push_back(UFSDevice[this_lun]->SSDReadInfo.front());
 UFSDevice[this_lun]->SSDReadInfo.pop_front();
-readGarbageEventQueue.push_back(this);
+readGarbageEventQueue.push_back(
+EventFunctionWrapper([this]{ readGarbage(); }, name()));

 //make sure the queue is popped a the end of the dma transaction
 readDevice(false, SSDReadPending.front().offset,
diff --git a/src/dev/arm/ufs_device.hh b/src/dev/arm/ufs_device.hh
index 24a05b0..69abc27 100644
--- a/src/dev/arm/ufs_device.hh
+++ b/src/dev/arm/ufs_device.hh
@@ -1150,28 +1150,25 @@
 /**
  * Wait for the SCSI specific data to arive
  */
-EventWrapper SCSIResumeEvent;
+EventFunctionWrapper SCSIResumeEvent;

 /**
  * Wait for the moment where we can send the last frame
  */
-EventWrapper UTPEvent;
+EventFunctionWrapper UTPEvent;

 /**
  * Event after a read to clean up the UTP data structures
  */
-std::deque >
-readGarbageEventQueue;
+std::deque readGarbageEventQueue;

 /**
  * Multiple tasks transfers can be scheduled at once for the device,  
the

  * only thing we know for sure about them is that they will happen in a
  * first come first serve order; hence we need to queue.
  */
-std::deque >
-taskEventQueue;
-std::deque >
-transferEventQueue;
+std::deque taskEventQueue;
+std::deque transferEventQueue;

 /**
  * Bits of interest within UFS data packages
diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index f84b4c3..a78819a 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -56,7 +56,8 @@
 DmaPort::DmaPort(MemObject *dev, System *s)
 : MasterPort(dev->name() + ".dma", dev),
   device(dev), sys(s), masterId(s->getMasterId(dev->name())),
-  sendEvent(this), pendingCount(0), inRetry(false)
+  sendEvent([this]{ sendDma(); }, dev->name()),
+  pendingCount(0), inRetry(false)
 { }

 void
diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index 4a1946a..f354d38 100644
--- 

[gem5-dev] Change in public/gem5[master]: mem: Replace EventWrapper use with EventFunctionWrapper

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3745 )


Change subject: mem: Replace EventWrapper use with EventFunctionWrapper
..

mem: Replace EventWrapper use with EventFunctionWrapper

NOTE: With this change there is a possibility for `DRAMCtrl::Rank`s
event names to not properly match the rank they were generated by. This
could occur if the public rank member is modified after the Rank's
construction. A patch would mean refactoring Rank and `DRAMCtrl`b to
privatize many of the members of Rank behind getters.

Change-Id: I7b8bd15086f4ffdfd3f40be4aeddac5e786fd78e
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3745
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Anthony Gutierrez 
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
---
M src/mem/bridge.cc
M src/mem/bridge.hh
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
M src/mem/comm_monitor.cc
M src/mem/comm_monitor.hh
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
M src/mem/dramsim2.cc
M src/mem/dramsim2.hh
M src/mem/serial_link.cc
M src/mem/serial_link.hh
M src/mem/simple_mem.cc
M src/mem/simple_mem.hh
M src/mem/xbar.cc
M src/mem/xbar.hh
18 files changed, 45 insertions(+), 46 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved



diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index a7adcba..0c9e2c1 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -61,8 +61,8 @@
  std::vector _ranges)
 : SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
   delay(_delay), ranges(_ranges.begin(), _ranges.end()),
-  outstandingResponses(0), retryReq(false),
-  respQueueLimit(_resp_limit), sendEvent(*this)
+  outstandingResponses(0), retryReq(false),  
respQueueLimit(_resp_limit),

+  sendEvent([this]{ trySendTiming(); }, _name)
 {
 }

@@ -71,7 +71,8 @@
BridgeSlavePort& _slavePort,
Cycles _delay, int _req_limit)
 : MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
-  delay(_delay), reqQueueLimit(_req_limit), sendEvent(*this)
+  delay(_delay), reqQueueLimit(_req_limit),
+  sendEvent([this]{ trySendTiming(); }, _name)
 {
 }

diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index ad35859..f2cc445 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -156,8 +156,7 @@
 void trySendTiming();

 /** Send event for the response queue. */
-EventWrapper sendEvent;
+EventFunctionWrapper sendEvent;

   public:

@@ -255,8 +254,7 @@
 void trySendTiming();

 /** Send event for the request queue. */
-EventWrapper sendEvent;
+EventFunctionWrapper sendEvent;

   public:

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 7f08d17..6f25323 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -62,7 +62,8 @@
   BaseCache *_cache,
   const std::string &_label)
 : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label),
-  blocked(false), mustSendRetry(false), sendRetryEvent(this)
+  blocked(false), mustSendRetry(false),
+  sendRetryEvent([this]{ processSendRetry(); }, _name)
 {
 }

diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 2787eea..2f4b934 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -177,8 +177,7 @@

 void processSendRetry();

-EventWrapper sendRetryEvent;
+EventFunctionWrapper sendRetryEvent;

 };

diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 0914810..fdc14a7 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -73,7 +73,8 @@
   clusivity(p->clusivity),
   writebackClean(p->writeback_clean),
   tempBlockWriteback(nullptr),
-  writebackTempBlockAtomicEvent(this, false,
+  writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
+name(), false,
 EventBase::Delayed_Writeback_Pri)
 {
 tempBlock = new CacheBlk();
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index e5c8ab6..9d135c6 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -257,8 +257,7 @@
  * finishes. To avoid other calls to recvAtomic 

[gem5-dev] Change in public/gem5[master]: sim: Add generic EventFunctionWrapper

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3743 )


Change subject: sim: Add generic EventFunctionWrapper
..

sim: Add generic EventFunctionWrapper

Add EventFunctionWrapper, an event wrapper which takes any callable
object to use as its callback. (This includes c++ lambdas, function
pointers, bound functions, and std::functions.)

Change-Id: Iab140df47bd0f7e4b3fe3b568f9dd122a43cee1c
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3743
Reviewed-by: Anthony Gutierrez 
Reviewed-by: Jason Lowe-Power 
Maintainer: Anthony Gutierrez 
---
M src/sim/eventq.hh
1 file changed, 28 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved



diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index 9d3c5c3..6d68b4e 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -800,4 +800,32 @@
 const char *description() const { return "EventWrapped"; }
 };

+class EventFunctionWrapper : public Event
+{
+  private:
+  std::function callback;
+  std::string _name;
+
+  public:
+EventFunctionWrapper(const std::function ,
+ const std::string ,
+ bool del = false,
+ Priority p = Default_Pri)
+: Event(p), callback(callback), _name(name)
+{
+if (del)
+setFlags(AutoDelete);
+}
+
+void process() { callback(); }
+
+const std::string
+name() const
+{
+return _name + ".wrapped_function_event";
+}
+
+const char *description() const { return "EventFunctionWrapped"; }
+};
+
 #endif // __SIM_EVENTQ_HH__

--
To view, visit https://gem5-review.googlesource.com/3743
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Iab140df47bd0f7e4b3fe3b568f9dd122a43cee1c
Gerrit-Change-Number: 3743
Gerrit-PatchSet: 3
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sean Wilson 
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[gem5-dev] Change in public/gem5[master]: arm: Replace EventWrapper use with EventFunctionWrapper

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3747 )


Change subject: arm: Replace EventWrapper use with EventFunctionWrapper
..

arm: Replace EventWrapper use with EventFunctionWrapper

Change-Id: I08de5f72513645d1fe92bde99fa205dde897e951
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3747
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Anthony Gutierrez 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/dev/arm/energy_ctrl.cc
M src/dev/arm/energy_ctrl.hh
M src/dev/arm/flash_device.cc
M src/dev/arm/flash_device.hh
M src/dev/arm/generic_timer.cc
M src/dev/arm/generic_timer.hh
M src/dev/arm/hdlcd.cc
M src/dev/arm/hdlcd.hh
M src/dev/arm/kmi.cc
M src/dev/arm/kmi.hh
M src/dev/arm/pl011.cc
M src/dev/arm/pl011.hh
M src/dev/arm/pl111.cc
M src/dev/arm/pl111.hh
M src/dev/arm/rtc_pl031.cc
M src/dev/arm/rtc_pl031.hh
M src/dev/arm/timer_cpulocal.cc
M src/dev/arm/timer_cpulocal.hh
M src/dev/arm/timer_sp804.cc
M src/dev/arm/timer_sp804.hh
M src/dev/arm/ufs_device.cc
M src/dev/arm/ufs_device.hh
24 files changed, 54 insertions(+), 48 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved



diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 8783d0a..2d66642 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -64,12 +64,15 @@
   numSquashable(p->num_squash_per_cycle),
   pendingReqs(0),
   pendingChangeTick(curTick()),
-  doL1DescEvent(this), doL2DescEvent(this),
-  doL0LongDescEvent(this), doL1LongDescEvent(this),
-  doL2LongDescEvent(this), doL3LongDescEvent(this),
+  doL1DescEvent([this]{ doL1DescriptorWrapper(); }, name()),
+  doL2DescEvent([this]{ doL2DescriptorWrapper(); }, name()),
+  doL0LongDescEvent([this]{ doL0LongDescriptorWrapper(); }, name()),
+  doL1LongDescEvent([this]{ doL1LongDescriptorWrapper(); }, name()),
+  doL2LongDescEvent([this]{ doL2LongDescriptorWrapper(); }, name()),
+  doL3LongDescEvent([this]{ doL3LongDescriptorWrapper(); }, name()),
   LongDescEventByLevel { , ,
  ,  },
-  doProcessEvent(this)
+  doProcessEvent([this]{ processWalkWrapper(); }, name())
 {
 sctlr = 0;

diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index c52cfcb..b322c50 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -920,28 +920,22 @@

 void doL1Descriptor();
 void doL1DescriptorWrapper();
-EventWrapper doL1DescEvent;
+EventFunctionWrapper doL1DescEvent;

 void doL2Descriptor();
 void doL2DescriptorWrapper();
-EventWrapper doL2DescEvent;
+EventFunctionWrapper doL2DescEvent;

 void doLongDescriptor();

 void doL0LongDescriptorWrapper();
-EventWrapper  
doL0LongDescEvent;

+EventFunctionWrapper doL0LongDescEvent;
 void doL1LongDescriptorWrapper();
-EventWrapper  
doL1LongDescEvent;

+EventFunctionWrapper doL1LongDescEvent;
 void doL2LongDescriptorWrapper();
-EventWrapper  
doL2LongDescEvent;

+EventFunctionWrapper doL2LongDescEvent;
 void doL3LongDescriptorWrapper();
-EventWrapper  
doL3LongDescEvent;

+EventFunctionWrapper doL3LongDescEvent;

 void doLongDescriptorWrapper(LookupLevel curr_lookup_level);
 Event* LongDescEventByLevel[4];
@@ -960,7 +954,7 @@
 static bool checkAddrSizeFaultAArch64(Addr addr, int  
currPhysAddrRange);

 Fault processWalkAArch64();
 void processWalkWrapper();
-EventWrapper  
doProcessEvent;

+EventFunctionWrapper doProcessEvent;

 void nextWalk(ThreadContext *tc);

diff --git a/src/dev/arm/energy_ctrl.cc b/src/dev/arm/energy_ctrl.cc
index 9efdeb1..9cfce3a 100644
--- a/src/dev/arm/energy_ctrl.cc
+++ b/src/dev/arm/energy_ctrl.cc
@@ -54,7 +54,7 @@
   domainIDIndexToRead(0),
   perfLevelAck(0),
   perfLevelToRead(0),
-  updateAckEvent(this)
+  updateAckEvent([this]{ updatePLAck(); }, name())
 {
 fatal_if(!p->dvfs_handler, "EnergyCtrl: Needs a DVFSHandler for a "
  "functioning system.\n");
diff --git a/src/dev/arm/energy_ctrl.hh b/src/dev/arm/energy_ctrl.hh
index ddfd8d7..2c7eb85 100644
--- 

[gem5-dev] Change in public/gem5[master]: mem: Move the Rank construction logic to the Rank constructor

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3742 )


Change subject: mem: Move the Rank construction logic to the Rank  
constructor

..

mem: Move the Rank construction logic to the Rank constructor

This change was made so Rank objects have their name assigned
when they are instantiated. Therefore, they can initialize their
member objects with their name and it is less likely to change during
runtime.

(NOTE: I would recommend hiding the fields which would cause the name to
change behind getters. Since modification of `Rank.rank` during runtime
will cause the `name()` to change.)

Change-Id: Id51c3553b40e489792c57950e18b8ce927e43173
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3742
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Jason Lowe-Power 
Maintainer: Nikos Nikoleris 
---
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
2 files changed, 27 insertions(+), 30 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 4398611..9e5c00b 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -104,32 +104,8 @@
  "must be a power of two\n", burstSize);

 for (int i = 0; i < ranksPerChannel; i++) {
-Rank* rank = new Rank(*this, p);
+Rank* rank = new Rank(*this, p, i);
 ranks.push_back(rank);
-
-rank->actTicks.resize(activationLimit, 0);
-rank->banks.resize(banksPerRank);
-rank->rank = i;
-
-for (int b = 0; b < banksPerRank; b++) {
-rank->banks[b].bank = b;
-// GDDR addressing of banks to BG is linear.
-// Here we assume that all DRAM generations address bank  
groups as

-// follows:
-if (bankGroupArch) {
-// Simply assign lower bits to bank group in order to
-// rotate across bank groups as banks are incremented
-// e.g. with 4 banks per bank group and 16 banks total:
-//banks 0,4,8,12  are in bank group 0
-//banks 1,5,9,13  are in bank group 1
-//banks 2,6,10,14 are in bank group 2
-//banks 3,7,11,15 are in bank group 3
-rank->banks[b].bankgr = b % bankGroupsPerRank;
-} else {
-// No bank groups; simply assign to bank number
-rank->banks[b].bankgr = b;
-}
-}
 }

 // perform a basic check of the write thresholds
@@ -1626,16 +1602,37 @@
 return make_pair(bank_mask, hidden_bank_prep);
 }

-DRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p)
+DRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank)
 : EventManager(&_memory), memory(_memory),
   pwrStateTrans(PWR_IDLE), pwrStatePostRefresh(PWR_IDLE),
   pwrStateTick(0), refreshDueAt(0), pwrState(PWR_IDLE),
-  refreshState(REF_IDLE), inLowPowerState(false), rank(0),
+  refreshState(REF_IDLE), inLowPowerState(false), rank(rank),
   readEntries(0), writeEntries(0), outstandingEvents(0),
-  wakeUpAllowedAt(0), power(_p, false), numBanksActive(0),
+  wakeUpAllowedAt(0), power(_p, false), banks(_p->banks_per_rank),
+  numBanksActive(0), actTicks(_p->activation_limit, 0),
   writeDoneEvent(*this), activateEvent(*this), prechargeEvent(*this),
   refreshEvent(*this), powerEvent(*this), wakeUpEvent(*this)
-{ }
+{
+for (int b = 0; b < _p->banks_per_rank; b++) {
+banks[b].bank = b;
+// GDDR addressing of banks to BG is linear.
+// Here we assume that all DRAM generations address bank groups as
+// follows:
+if (_p->bank_groups_per_rank > 0) {
+// Simply assign lower bits to bank group in order to
+// rotate across bank groups as banks are incremented
+// e.g. with 4 banks per bank group and 16 banks total:
+//banks 0,4,8,12  are in bank group 0
+//banks 1,5,9,13  are in bank group 1
+//banks 2,6,10,14 are in bank group 2
+//banks 3,7,11,15 are in bank group 3
+banks[b].bankgr = b % _p->bank_groups_per_rank;
+} else {
+// No bank groups; simply assign to bank number
+banks[b].bankgr = b;
+}
+}
+}

 void
 DRAMCtrl::Rank::startup(Tick ref_tick)
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index 12cb0e9..1883041 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -451,7 +451,7 @@
 /** List to keep track of activate ticks */
 std::deque actTicks;

-Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p);
+

[gem5-dev] Change in public/gem5[master]: cpu, gpu-compute: Replace EventWrapper use with EventFunctio...

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3746 )


Change subject: cpu, gpu-compute: Replace EventWrapper use with  
EventFunctionWrapper

..

cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapper

Change-Id: Idd5992463bcf9154f823b82461070d1f1842cea3
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3746
Reviewed-by: Anthony Gutierrez 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/cpu/base.cc
M src/cpu/kvm/base.cc
M src/cpu/o3/probe/elastic_trace.cc
M src/cpu/o3/probe/elastic_trace.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/memtest/memtest.hh
M src/cpu/testers/traffic_gen/traffic_gen.cc
M src/cpu/testers/traffic_gen/traffic_gen.hh
M src/cpu/trace/trace_cpu.cc
M src/cpu/trace/trace_cpu.hh
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
14 files changed, 29 insertions(+), 29 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved



diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 08f95ea..6f460d3 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -229,8 +229,8 @@
 if (p->function_trace_start == 0) {
 functionTracingEnabled = true;
 } else {
-typedef EventWrapper  
wrap;

-Event *event = new wrap(this, true);
+Event *event = new EventFunctionWrapper(
+[this]{ enableFunctionTrace(); }, name(), true);
 schedule(event, p->function_trace_start);
 }
 }
diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index 6ae3c7d..23a4080 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -164,8 +164,7 @@
 thread->startup();

 Event *startupEvent(
-new EventWrapper(this, true));
+new EventFunctionWrapper([this]{ startupThread(); }, name(),  
true));

 schedule(startupEvent, curTick());
 }

diff --git a/src/cpu/o3/probe/elastic_trace.cc  
b/src/cpu/o3/probe/elastic_trace.cc

index bf6b6f0..c97bf78 100644
--- a/src/cpu/o3/probe/elastic_trace.cc
+++ b/src/cpu/o3/probe/elastic_trace.cc
@@ -50,7 +50,7 @@

 ElasticTrace::ElasticTrace(const ElasticTraceParams* params)
 :  ProbeListenerObject(params),
-   regEtraceListenersEvent(this),
+   regEtraceListenersEvent([this]{ regEtraceListeners(); }, name()),
firstWin(true),
lastClearedSeqNum(0),
depWindowSize(params->depWindowSize),
diff --git a/src/cpu/o3/probe/elastic_trace.hh  
b/src/cpu/o3/probe/elastic_trace.hh

index 584cdf1..08e02da 100644
--- a/src/cpu/o3/probe/elastic_trace.hh
+++ b/src/cpu/o3/probe/elastic_trace.hh
@@ -182,8 +182,7 @@
 void regStats();

 /** Event to trigger registering this listener for all probe points. */
-EventWrapper  
regEtraceListenersEvent;

+EventFunctionWrapper regEtraceListenersEvent;

   private:
 /**
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 1c468dc..d2cb6ee 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -80,7 +80,7 @@
 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
   dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL),  
previousCycle(0),

-  fetchEvent(this)
+  fetchEvent([this]{ fetch(); }, name())
 {
 _status = Idle;
 }
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index eebf884..8498630 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -159,7 +159,8 @@
   public:

 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
-: MasterPort(_name, _cpu), cpu(_cpu), retryRespEvent(this)
+: MasterPort(_name, _cpu), cpu(_cpu),
+  retryRespEvent([this]{ sendRetryResp(); }, name())
 { }

   protected:
@@ -176,7 +177,7 @@
 void schedule(PacketPtr _pkt, Tick t);
 };

-EventWrapper  
retryRespEvent;

+EventFunctionWrapper retryRespEvent;
 };

 class IcachePort : public TimingCPUPort
@@ -315,8 +316,7 @@

   private:

-typedef EventWrapper  
FetchEvent;

-FetchEvent fetchEvent;
+EventFunctionWrapper fetchEvent;

 struct IprEvent : Event {
 Packet *pkt;
diff --git a/src/cpu/testers/memtest/memtest.cc  
b/src/cpu/testers/memtest/memtest.cc

index 46387fa..6f3f9b3 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -86,9 +86,9 @@

 MemTest::MemTest(const Params 

[gem5-dev] Change in public/gem5[master]: sim, x86: Replace EventWrapper use with EventFunctionWrapper

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3749 )


Change subject: sim, x86: Replace EventWrapper use with EventFunctionWrapper
..

sim, x86: Replace EventWrapper use with EventFunctionWrapper

Change-Id: Ie1df07b70776208fc3631a73d403024636fc05a9
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3749
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Anthony Gutierrez 
Maintainer: Anthony Gutierrez 
---
M src/arch/x86/pagetable_walker.hh
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
M src/sim/root.cc
M src/sim/root.hh
5 files changed, 8 insertions(+), 8 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/x86/pagetable_walker.hh  
b/src/arch/x86/pagetable_walker.hh

index 9be35e6..d71db7e 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -178,7 +178,7 @@
 /**
  * Event used to call startWalkWrapper.
  **/
-EventWrapper  
startWalkWrapperEvent;

+EventFunctionWrapper startWalkWrapperEvent;

 // Functions for dealing with packets.
 bool recvTimingResp(PacketPtr pkt);
@@ -205,7 +205,7 @@
 funcState(this, NULL, NULL, true), tlb(NULL),  
sys(params->system),

 masterId(sys->getMasterId(name())),
 numSquashable(params->num_squash_per_cycle),
-startWalkWrapperEvent(this)
+startWalkWrapperEvent([this]{ startWalkWrapper(); }, name())
 {
 }
 };
diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index 05ce42b..d362da6 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -194,7 +194,7 @@
  * ThermalModel
  */
 ThermalModel::ThermalModel(const Params *p)
-: ClockedObject(p), stepEvent(this), _step(p->step)
+: ClockedObject(p), stepEvent([this]{ doStep(); }, name()),  
_step(p->step)

 {
 }

diff --git a/src/sim/power/thermal_model.hh b/src/sim/power/thermal_model.hh
index 7ee4ffd..b47061d 100644
--- a/src/sim/power/thermal_model.hh
+++ b/src/sim/power/thermal_model.hh
@@ -179,7 +179,7 @@
 std::vector  eq_nodes;

 /** Stepping event to update the model values */
-EventWrapper stepEvent;
+EventFunctionWrapper stepEvent;

 /** Step in seconds for thermal updates */
 double _step;
diff --git a/src/sim/root.cc b/src/sim/root.cc
index 752632b..f4aabad 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -104,8 +104,9 @@
 timeSyncEnable(en);
 }

-Root::Root(RootParams *p) : SimObject(p), _enabled(false),
-_periodTick(p->time_sync_period), syncEvent(this)
+Root::Root(RootParams *p)
+: SimObject(p), _enabled(false), _periodTick(p->time_sync_period),
+  syncEvent([this]{ timeSync(); }, name())
 {
 _period.setTick(p->time_sync_period);
 _spinThreshold.setTick(p->time_sync_spin_threshold);
diff --git a/src/sim/root.hh b/src/sim/root.hh
index 7273a07..db207a7 100644
--- a/src/sim/root.hh
+++ b/src/sim/root.hh
@@ -60,8 +60,7 @@
 Time lastTime;

 void timeSync();
-EventWrapper syncEvent;
-friend class EventWrapper;
+EventFunctionWrapper syncEvent;

   public:
 /**

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ie1df07b70776208fc3631a73d403024636fc05a9
Gerrit-Change-Number: 3749
Gerrit-PatchSet: 5
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Sean Wilson 
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[gem5-dev] Change in public/gem5[master]: mem: Replace EventWrapper in PacketQueue with EventFunctionW...

[Sean Wilson (Gerrit)]

Hello Anthony Gutierrez, Jason Lowe-Power, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/3744

to look at the new patch set (#3).

Change subject: mem: Replace EventWrapper in PacketQueue with  
EventFunctionWrapper

..

mem: Replace EventWrapper in PacketQueue with EventFunctionWrapper

In order to replicate the same `name()` output with `PacketQueue`,  
subclasses
using EventFunctionWrapper must initialize PacketQueue with their own name  
so

the sendEvent holds the name of the subclass.

Change-Id: Ib091e118bab8858192e1d1370d61def42958ec29
Signed-off-by: Sean Wilson 
---
M src/mem/packet_queue.cc
M src/mem/packet_queue.hh
2 files changed, 32 insertions(+), 8 deletions(-)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ib091e118bab8858192e1d1370d61def42958ec29
Gerrit-Change-Number: 3744
Gerrit-PatchSet: 3
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Sean Wilson 
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[gem5-dev] Change in public/gem5[master]: dev: Replace EventWrapper use with EventFunctionWrapper

[Sean Wilson (Gerrit)]

Hello Anthony Gutierrez, Jason Lowe-Power, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/3748

to look at the new patch set (#3).

Change subject: dev: Replace EventWrapper use with EventFunctionWrapper
..

dev: Replace EventWrapper use with EventFunctionWrapper

Change-Id: I6b03cc6f67e76dffb79940431711ae6171901c6a
Signed-off-by: Sean Wilson 
---
M src/dev/arm/ufs_device.cc
M src/dev/arm/ufs_device.hh
M src/dev/dma_device.cc
M src/dev/dma_device.hh
M src/dev/net/dist_etherlink.hh
M src/dev/net/etherlink.cc
M src/dev/net/etherlink.hh
M src/dev/net/etherswitch.cc
M src/dev/net/etherswitch.hh
M src/dev/net/i8254xGBe.cc
M src/dev/net/i8254xGBe.hh
M src/dev/net/ns_gige.cc
M src/dev/net/ns_gige.hh
M src/dev/net/sinic.cc
M src/dev/net/sinic.hh
M src/dev/pci/copy_engine.cc
M src/dev/pci/copy_engine.hh
M src/dev/storage/ide_disk.cc
M src/dev/storage/ide_disk.hh
19 files changed, 123 insertions(+), 135 deletions(-)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I6b03cc6f67e76dffb79940431711ae6171901c6a
Gerrit-Change-Number: 3748
Gerrit-PatchSet: 3
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: tests: Fix a typo for the default MI_example protocol

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3795 )


Change subject: tests: Fix a typo for the default MI_example protocol
..

tests: Fix a typo for the default MI_example protocol

Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3795
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Nikos Nikoleris 
Maintainer: Jason Lowe-Power 
---
M tests/testing/tests.py
1 file changed, 1 insertion(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved



diff --git a/tests/testing/tests.py b/tests/testing/tests.py
index a83f598..839eb96 100755
--- a/tests/testing/tests.py
+++ b/tests/testing/tests.py
@@ -166,10 +166,7 @@
 }

 def get_default_protocol(arch):
-try:
-return default_ruby_protocol[arch]
-except KeyError:
-return 'MI-example'
+return default_ruby_protocol.get(arch, 'MI_example')

 all_categories = ("quick", "long")
 all_modes = ("fs", "se")

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524
Gerrit-Change-Number: 3795
Gerrit-PatchSet: 6
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Sean Wilson 
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[gem5-dev] Change in public/gem5[master]: tests: Fix a typo for the default MI_example protocol

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power, Nikos Nikoleris, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/3795

to look at the new patch set (#5).

Change subject: tests: Fix a typo for the default MI_example protocol
..

tests: Fix a typo for the default MI_example protocol

Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524
Signed-off-by: Sean Wilson 
---
M tests/testing/tests.py
1 file changed, 1 insertion(+), 4 deletions(-)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524
Gerrit-Change-Number: 3795
Gerrit-PatchSet: 5
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Sean Wilson 
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[gem5-dev] Change in public/gem5[master]: tests: Fix a typo for the default MI_example protocol

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power, Nikos Nikoleris, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/3795

to look at the new patch set (#4).

Change subject: tests: Fix a typo for the default MI_example protocol
..

tests: Fix a typo for the default MI_example protocol

Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524
Signed-off-by: Sean Wilson 
---
M tests/testing/tests.py
1 file changed, 1 insertion(+), 4 deletions(-)


--
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Gerrit-Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524
Gerrit-Change-Number: 3795
Gerrit-PatchSet: 4
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: tests: Fix a typo for the default MI_example protocol

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power, Nikos Nikoleris, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/3795

to look at the new patch set (#3).

Change subject: tests: Fix a typo for the default MI_example protocol
..

tests: Fix a typo for the default MI_example protocol

Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524
Signed-off-by: Sean Wilson 
---
M tests/testing/tests.py
1 file changed, 1 insertion(+), 4 deletions(-)


--
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Gerrit-Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524
Gerrit-Change-Number: 3795
Gerrit-PatchSet: 3
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: x86: Add consistent overrides to process.hh

[Sean Wilson (Gerrit)]

Sean Wilson has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3720 )


Change subject: x86: Add consistent overrides to process.hh
..

x86: Add consistent overrides to process.hh

Change-Id: I912601b6f781a0bbedd06583c059589374f6d5c6
Signed-off-by: Sean Wilson 
Reviewed-on: https://gem5-review.googlesource.com/3720
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Joe Gross 
Reviewed-by: Gabe Black 
Reviewed-by: Brandon Potter 
Maintainer: Jason Lowe-Power 
---
M src/arch/x86/process.hh
1 file changed, 14 insertions(+), 9 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Brandon Potter: Looks good to me, approved
  Gabe Black: Looks good to me, but someone else must approve
  Joe Gross: Looks good to me, but someone else must approve



diff --git a/src/arch/x86/process.hh b/src/arch/x86/process.hh
index fe31348..9cd5378 100644
--- a/src/arch/x86/process.hh
+++ b/src/arch/x86/process.hh
@@ -79,9 +79,10 @@
 Addr gdtSize()
 { return _gdtSize; }

-SyscallDesc* getDesc(int callnum);
+SyscallDesc* getDesc(int callnum) override;

-void setSyscallReturn(ThreadContext *tc, SyscallReturn  
return_value);

+void setSyscallReturn(ThreadContext *tc,
+  SyscallReturn return_value) override;
 void clone(ThreadContext *old_tc, ThreadContext *new_tc,
Process *process, TheISA::IntReg flags);

@@ -131,12 +132,13 @@

   public:
 void argsInit(int pageSize);
-void initState();
+void initState() override;

-X86ISA::IntReg getSyscallArg(ThreadContext *tc, int );
+X86ISA::IntReg getSyscallArg(ThreadContext *tc, int ) override;
 /// Explicitly import the otherwise hidden getSyscallArg
 using Process::getSyscallArg;
-void setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val);
+void setSyscallArg(ThreadContext *tc, int i,
+   X86ISA::IntReg val) override;
 void clone(ThreadContext *old_tc, ThreadContext *new_tc,
Process *process, TheISA::IntReg flags);
 };
@@ -173,13 +175,16 @@

   public:
 void argsInit(int pageSize);
-void initState();
+void initState() override;

 void syscall(int64_t callnum, ThreadContext *tc,
  Fault *fault) override;
-X86ISA::IntReg getSyscallArg(ThreadContext *tc, int );
-X86ISA::IntReg getSyscallArg(ThreadContext *tc, int , int width);
-void setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val);
+X86ISA::IntReg getSyscallArg(ThreadContext *tc,
+ int ) override;
+X86ISA::IntReg getSyscallArg(ThreadContext *tc, int ,
+ int width) override;
+void setSyscallArg(ThreadContext *tc, int i,
+   X86ISA::IntReg val) override;
 void clone(ThreadContext *old_tc, ThreadContext *new_tc,
Process *process, TheISA::IntReg flags);
 };

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I912601b6f781a0bbedd06583c059589374f6d5c6
Gerrit-Change-Number: 3720
Gerrit-PatchSet: 2
Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Joe Gross 
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[gem5-dev] Change in public/gem5[master]: tests: Restore x86 tests and support for arm quick tests.

[Sean Wilson (Gerrit)]

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/3795

to look at the new patch set (#2).

Change subject: tests: Restore x86 tests and support for arm quick tests.
..

tests: Restore x86 tests and support for arm quick tests.

A lot of the x86 test refs are do not use the ruby modeler. Simply
ignoring all other test systems results in lots of x86 tests going
undetected.

Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524
Signed-off-by: Sean Wilson 
---
M tests/testing/tests.py
1 file changed, 5 insertions(+), 11 deletions(-)


--
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Gerrit-Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524
Gerrit-Change-Number: 3795
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Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: tests: Add back in x86 tests and support for existing arm qu...

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3795



Change subject: tests: Add back in x86 tests and support for existing arm  
quick tests.

..

tests: Add back in x86 tests and support for existing arm quick tests.

A lot of the x86 test refs are do not use the ruby modeler. Simply
ignoring all other test systems results in lots of x86 tests going
undetected.

Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524
Signed-off-by: Sean Wilson 
---
M tests/testing/tests.py
1 file changed, 5 insertions(+), 11 deletions(-)



diff --git a/tests/testing/tests.py b/tests/testing/tests.py
index a83f598..6845b7f 100755
--- a/tests/testing/tests.py
+++ b/tests/testing/tests.py
@@ -165,11 +165,6 @@
 "arm" : "MOESI_CMP_directory",
 }

-def get_default_protocol(arch):
-try:
-return default_ruby_protocol[arch]
-except KeyError:
-return 'MI-example'

 all_categories = ("quick", "long")
 all_modes = ("fs", "se")
@@ -347,17 +342,16 @@
 else:
 configs += generic_configs

-if ruby_protocol == get_default_protocol(isa):
-if ruby_protocol == 'MI_example':
-configs += [ "%s-ruby" % (c, ) for c in configs ]
-else:
-configs += [ "%s-ruby-%s" % (c, ruby_protocol) for c in  
configs ]

+ruby_protocol = default_ruby_protocol.get(isa, 'MI-example')
+
+if ruby_protocol == 'MI_example':
+configs += [ "%s-ruby" % (c, ) for c in configs ]
 elif ruby_protocol is not None:
 # Override generic ISA configs when using Ruby (excluding
 # MI_example which is included in all ISAs by default). This
 # reduces the number of generic tests we re-run for when
 # compiling Ruby targets.
-configs = [ "%s-ruby-%s" % (c, ruby_protocol) for c in configs ]
+configs += [ "%s-ruby-%s" % (c, ruby_protocol) for c in configs ]

 # /(quick|long)/(fs|se)/workload/ref/arch/guest/config/
 for conf_script in configs:

--
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[gem5-dev] Change in public/gem5[master]: tests: Skip tests that error when loading system files

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3790



Change subject: tests: Skip tests that error when loading system files
..

tests: Skip tests that error when loading system files

Change-Id: Ic3fef3f3a7aaf8d3fae9b1d9d28b1c14dc1bad86
Signed-off-by: Sean Wilson 
---
M tests/testing/units.py
1 file changed, 12 insertions(+), 1 deletion(-)



diff --git a/tests/testing/units.py b/tests/testing/units.py
index e8b87a0..8a9d307 100644
--- a/tests/testing/units.py
+++ b/tests/testing/units.py
@@ -159,12 +159,14 @@
 except OSError as ose:
 return self.error("Failed to launch gem5: %s" % ose)

+m5_stderr = self._read_output("simerr")
+
 stderr = "\n".join([
 "*** gem5 stderr ***",
 gem5_stderr,
 "",
 "*** m5out/simerr ***",
-self._read_output("simerr"),
+m5_stderr
 ])

 stdout = "\n".join([
@@ -182,6 +184,14 @@
 elif status == 2:
 return self.skip(stdout=stdout, stderr=stderr)
 elif status > 0:
+m5_stderr_split = m5_stderr.splitlines()
+
+if m5_stderr_split and  m5_stderr_split[-1] == \
+"IOError: Can't find a path to system files.":
+
+return self.skip(stdout="Unable to find a required file  
for"

+"this test.")
+
 return self.error("gem5 exited with non-zero status: %i" %  
status,

   stdout=stdout, stderr=stderr)
 else:
@@ -257,6 +267,7 @@
 if diff:
 return self.error("ref/%s and out/%s differ" % (fname, fname),
   stderr="".join(diff))
+
 else:
 return self.ok(stdout="-- ref/%s and out/%s are identical --" \
% (fname, fname))

--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic3fef3f3a7aaf8d3fae9b1d9d28b1c14dc1bad86
Gerrit-Change-Number: 3790
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[gem5-dev] Change in public/gem5[master]: tests: jenkins script auto-accept apt-get [Y/n] prompt

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3786



Change subject: tests: jenkins script auto-accept apt-get [Y/n] prompt
..

tests: jenkins script auto-accept apt-get [Y/n] prompt

Change-Id: I147dd9aaf4258d6a526235dd2f1c36d3913a31ea
---
M tests/jenkins/continuous.sh
M tests/jenkins/presubmit.sh
2 files changed, 2 insertions(+), 2 deletions(-)



diff --git a/tests/jenkins/continuous.sh b/tests/jenkins/continuous.sh
index 9290476..2f86cd3 100755
--- a/tests/jenkins/continuous.sh
+++ b/tests/jenkins/continuous.sh
@@ -39,7 +39,7 @@

 set -e

-sudo apt-get install cpu-checker curl g++ gcc-arm-linux-gnueabi git-core \
+sudo apt-get -y install cpu-checker curl g++ gcc-arm-linux-gnueabi  
git-core \

 git-gui gitk libboost-all-dev libgoogle-perftools-dev libprotobuf-dev \
 libprotoc-dev libssl-dev m4 parallel pigz protobuf-compiler python  \
 python-pip scons subversion swig zlib1g-dev
diff --git a/tests/jenkins/presubmit.sh b/tests/jenkins/presubmit.sh
index 9290476..2f86cd3 100755
--- a/tests/jenkins/presubmit.sh
+++ b/tests/jenkins/presubmit.sh
@@ -39,7 +39,7 @@

 set -e

-sudo apt-get install cpu-checker curl g++ gcc-arm-linux-gnueabi git-core \
+sudo apt-get -y install cpu-checker curl g++ gcc-arm-linux-gnueabi  
git-core \

 git-gui gitk libboost-all-dev libgoogle-perftools-dev libprotobuf-dev \
 libprotoc-dev libssl-dev m4 parallel pigz protobuf-compiler python  \
 python-pip scons subversion swig zlib1g-dev

--
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Gerrit-Change-Id: I147dd9aaf4258d6a526235dd2f1c36d3913a31ea
Gerrit-Change-Number: 3786
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[gem5-dev] Change in public/gem5[master]: tests: Re-write jenkins scripts to parse test output for fai...

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3791



Change subject: tests: Re-write jenkins scripts to parse test output for  
failures

..

tests: Re-write jenkins scripts to parse test output for failures

Change-Id: Ic9adb25a7fa3bfdafa42e3ce3c2b23ce844a
Signed-off-by: Sean Wilson 
---
M tests/jenkins/continuous.sh
M tests/jenkins/presubmit.sh
2 files changed, 56 insertions(+), 28 deletions(-)



diff --git a/tests/jenkins/continuous.sh b/tests/jenkins/continuous.sh
index daa2040..82fb1b0 100755
--- a/tests/jenkins/continuous.sh
+++ b/tests/jenkins/continuous.sh
@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
 #
 # Copyright (c) 2016 ARM Limited
 # All rights reserved
@@ -36,36 +36,50 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Andreas Sandberg
+#  Sean Wilson

 set -e
+set -o pipefail
+
+# Use ccache with the default directory for caching
+export PATH="/usr/lib/ccache:$PATH"
+
+export LOGFILE="continuous-output"
+rm -f "${LOGFILE}"

 cd git/jenkins-gem5-prod

 BUILD_JOBS=4

 GEM5_ARCH="ALPHA ARM MIPS NULL POWER SPARC X86"
-GEM5_MODE=opt
+GEM5_VARIANT="opt"

 TARGETS=
 for A in ${GEM5_ARCH}; do
-TARGETS="${TARGETS} build/${A}/gem5.${GEM5_MODE}"
+TARGETS="${TARGETS} build/${A}/gem5.${GEM5_VARIANT}"
 done

-TEST_TARGETS=
+export TEST_TARGETS=""
 for A in ${GEM5_ARCH}; do
-TEST_TARGETS="${TEST_TARGETS} build/${A}/tests/${GEM5_MODE}/quick"
+TEST_TARGETS="${TEST_TARGETS} build/${A}/tests/${GEM5_VARIANT}\
+/quick/"
 done

+runtests () {
+   scons --ignore-style ${TARGETS} -j${BUILD_JOBS} &>> "${LOGFILE}"

-scons --ignore-style $TARGETS -j${BUILD_JOBS}
+# Run the tests and check for a failure, return "0" for success
+scons --ignore-style ${TEST_TARGETS} -j${BUILD_JOBS} |\
+tee -a "${LOGFILE}" | grep 'FAILED!' | wc -l

-if [ "$?" = "0" ]; then
-  echo "SUCCESS"
-  cd ../..
-  exit 0
+   exit 0
+}
+
+# Check that there were zero failed tests and the subcommand was successful
+if [ "$(runtests 2>> ${LOGFILE})" = "0" -a "$?" = "0" ]; then
+echo "SUCCESS"
+exit 0
 else
-  echo "FAIL"
-  cd ../..
-  exit 1
+echo "FAIL"
+exit 1
 fi
-
diff --git a/tests/jenkins/presubmit.sh b/tests/jenkins/presubmit.sh
index d5eaaa6..79a9648 100755
--- a/tests/jenkins/presubmit.sh
+++ b/tests/jenkins/presubmit.sh
@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
 #
 # Copyright (c) 2016 ARM Limited
 # All rights reserved
@@ -36,36 +36,50 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Andreas Sandberg
+#  Sean Wilson

 set -e
+set -o pipefail
+
+# Use ccache with the default directory for caching
+export PATH="/usr/lib/ccache:$PATH"
+
+export LOGFILE="presubmit-output"
+rm -f "${LOGFILE}"

 cd git/jenkins-gem5-prod

 BUILD_JOBS=4

-GEM5_ARCH="ALPHA ARM MIPS NULL POWER SPARC X86"
-GEM5_MODE=opt
+GEM5_ARCH="ARM NULL X86"
+GEM5_VARIANT="opt"

 TARGETS=
 for A in ${GEM5_ARCH}; do
-TARGETS="${TARGETS} build/${A}/gem5.${GEM5_MODE}"
+TARGETS="${TARGETS} build/${A}/gem5.${GEM5_VARIANT}"
 done

-TEST_TARGETS=
+export TEST_TARGETS=""
 for A in ${GEM5_ARCH}; do
-TEST_TARGETS="${TEST_TARGETS} build/${A}/tests/${GEM5_MODE}/quick"
+TEST_TARGETS="${TEST_TARGETS} build/${A}/tests/${GEM5_VARIANT}\
+/quick/se/00.hello"
 done

+runtests () {
+   scons --ignore-style ${TARGETS} -j${BUILD_JOBS} &>> "${LOGFILE}"

-scons --ignore-style $TARGETS -j${BUILD_JOBS}
+# Run the tests and check for a failure, return "0" for success
+scons --ignore-style ${TEST_TARGETS} -j${BUILD_JOBS} |\
+tee -a "${LOGFILE}" | grep 'FAILED!' | wc -l

+   exit 0
+}

-if [ "$?" = "0" ]; then
-  echo "SUCCESS"
-  cd ../..
-  exit 0
+# Check that there were zero failed tests and the subcommand was successful
+if [ "$(runtests 2>> ${LOGFILE})" = "0" -a "$?" = "0" ]; then
+echo "SUCCESS"
+exit 0
 else
-  echo "FAIL"
-  cd ../..
-  exit 1
+echo "FAIL"
+exit 1
 fi

--
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Gerrit-Change-Id: Ic9adb25a7fa3bfdafa42e3ce3c2b23ce844a
Gerrit-Change-Number: 3791
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[gem5-dev] Change in public/gem5[master]: tests: Fix dir paths for jenkins script running on GCP

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3787



Change subject: tests: Fix dir paths for jenkins script running on GCP
..

tests: Fix dir paths for jenkins script running on GCP

Change-Id: I0a76c6963618b40a23963740ac701a2e3aab5efe
---
M tests/jenkins/continuous.sh
M tests/jenkins/presubmit.sh
2 files changed, 9 insertions(+), 1 deletion(-)



diff --git a/tests/jenkins/continuous.sh b/tests/jenkins/continuous.sh
index 2f86cd3..7e34a3c 100755
--- a/tests/jenkins/continuous.sh
+++ b/tests/jenkins/continuous.sh
@@ -44,6 +44,8 @@
 libprotoc-dev libssl-dev m4 parallel pigz protobuf-compiler python  \
 python-pip scons subversion swig zlib1g-dev

+pushd git/jenkins-gem5-prod
+
 BUILD_JOBS=4

 GEM5_ARCH="ALPHA ARM MIPS NULL POWER SPARC X86"
@@ -62,11 +64,13 @@

 scons --ignore-style $TARGETS -j${BUILD_JOBS}

-
 if [ "$?" = "0" ]; then
   echo "SUCCESS"
+  popd
   exit 0
 else
   echo "FAIL"
+  popd
   exit 1
 fi
+
diff --git a/tests/jenkins/presubmit.sh b/tests/jenkins/presubmit.sh
index 2f86cd3..022a6a1 100755
--- a/tests/jenkins/presubmit.sh
+++ b/tests/jenkins/presubmit.sh
@@ -44,6 +44,8 @@
 libprotoc-dev libssl-dev m4 parallel pigz protobuf-compiler python  \
 python-pip scons subversion swig zlib1g-dev

+pushd git/jenkins-gem5-prod
+
 BUILD_JOBS=4

 GEM5_ARCH="ALPHA ARM MIPS NULL POWER SPARC X86"
@@ -65,8 +67,10 @@

 if [ "$?" = "0" ]; then
   echo "SUCCESS"
+  popd
   exit 0
 else
   echo "FAIL"
+  popd
   exit 1
 fi

--
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[gem5-dev] Change in public/gem5[master]: tests: Add sudo to jenkins script apt-get cmd line

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3785



Change subject: tests: Add sudo to jenkins script apt-get cmd line
..

tests: Add sudo to jenkins script apt-get cmd line

Change-Id: I3c6ddebb0872b174e4351b91a0433b83477ec494
---
M tests/jenkins/continuous.sh
M tests/jenkins/presubmit.sh
2 files changed, 2 insertions(+), 2 deletions(-)



diff --git a/tests/jenkins/continuous.sh b/tests/jenkins/continuous.sh
index 58afdbb..9290476 100755
--- a/tests/jenkins/continuous.sh
+++ b/tests/jenkins/continuous.sh
@@ -39,7 +39,7 @@

 set -e

-apt-get install cpu-checker curl g++ gcc-arm-linux-gnueabi git-core \
+sudo apt-get install cpu-checker curl g++ gcc-arm-linux-gnueabi git-core \
 git-gui gitk libboost-all-dev libgoogle-perftools-dev libprotobuf-dev \
 libprotoc-dev libssl-dev m4 parallel pigz protobuf-compiler python  \
 python-pip scons subversion swig zlib1g-dev
diff --git a/tests/jenkins/presubmit.sh b/tests/jenkins/presubmit.sh
index 58afdbb..9290476 100755
--- a/tests/jenkins/presubmit.sh
+++ b/tests/jenkins/presubmit.sh
@@ -39,7 +39,7 @@

 set -e

-apt-get install cpu-checker curl g++ gcc-arm-linux-gnueabi git-core \
+sudo apt-get install cpu-checker curl g++ gcc-arm-linux-gnueabi git-core \
 git-gui gitk libboost-all-dev libgoogle-perftools-dev libprotobuf-dev \
 libprotoc-dev libssl-dev m4 parallel pigz protobuf-compiler python  \
 python-pip scons subversion swig zlib1g-dev

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[gem5-dev] Change in public/gem5[master]: tests: Remove package install step in jenkins test scripts

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3789



Change subject: tests: Remove package install step in jenkins test scripts
..

tests: Remove package install step in jenkins test scripts

Change-Id: I0af93a74e8c53c3bf3403152d83989292e27b4a3
---
M tests/jenkins/continuous.sh
M tests/jenkins/presubmit.sh
2 files changed, 0 insertions(+), 10 deletions(-)



diff --git a/tests/jenkins/continuous.sh b/tests/jenkins/continuous.sh
index 3e670af..daa2040 100755
--- a/tests/jenkins/continuous.sh
+++ b/tests/jenkins/continuous.sh
@@ -39,11 +39,6 @@

 set -e

-sudo apt-get -y install cpu-checker curl g++ gcc-arm-linux-gnueabi  
git-core \

-git-gui gitk libboost-all-dev libgoogle-perftools-dev libprotobuf-dev \
-libprotoc-dev libssl-dev m4 parallel pigz protobuf-compiler python  \
-python-pip scons subversion swig zlib1g-dev
-
 cd git/jenkins-gem5-prod

 BUILD_JOBS=4
diff --git a/tests/jenkins/presubmit.sh b/tests/jenkins/presubmit.sh
index 7892aa6..d5eaaa6 100755
--- a/tests/jenkins/presubmit.sh
+++ b/tests/jenkins/presubmit.sh
@@ -39,11 +39,6 @@

 set -e

-sudo apt-get -y install cpu-checker curl g++ gcc-arm-linux-gnueabi  
git-core \

-git-gui gitk libboost-all-dev libgoogle-perftools-dev libprotobuf-dev \
-libprotoc-dev libssl-dev m4 parallel pigz protobuf-compiler python  \
-python-pip scons subversion swig zlib1g-dev
-
 cd git/jenkins-gem5-prod

 BUILD_JOBS=4

--
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[gem5-dev] Change in public/gem5[master]: tests: Add gem5 pre-requisite package installation in jenkin...

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3784



Change subject: tests: Add gem5 pre-requisite package installation in  
jenkins scripts

..

tests: Add gem5 pre-requisite package installation in jenkins scripts

Change-Id: I08878c95f80b3a2312623cfdf99353b0d03649d1
---
M tests/jenkins/continuous.sh
M tests/jenkins/presubmit.sh
2 files changed, 10 insertions(+), 0 deletions(-)



diff --git a/tests/jenkins/continuous.sh b/tests/jenkins/continuous.sh
index 5bfea29..58afdbb 100755
--- a/tests/jenkins/continuous.sh
+++ b/tests/jenkins/continuous.sh
@@ -39,6 +39,11 @@

 set -e

+apt-get install cpu-checker curl g++ gcc-arm-linux-gnueabi git-core \
+git-gui gitk libboost-all-dev libgoogle-perftools-dev libprotobuf-dev \
+libprotoc-dev libssl-dev m4 parallel pigz protobuf-compiler python  \
+python-pip scons subversion swig zlib1g-dev
+
 BUILD_JOBS=4

 GEM5_ARCH="ALPHA ARM MIPS NULL POWER SPARC X86"
diff --git a/tests/jenkins/presubmit.sh b/tests/jenkins/presubmit.sh
index 5bfea29..58afdbb 100755
--- a/tests/jenkins/presubmit.sh
+++ b/tests/jenkins/presubmit.sh
@@ -39,6 +39,11 @@

 set -e

+apt-get install cpu-checker curl g++ gcc-arm-linux-gnueabi git-core \
+git-gui gitk libboost-all-dev libgoogle-perftools-dev libprotobuf-dev \
+libprotoc-dev libssl-dev m4 parallel pigz protobuf-compiler python  \
+python-pip scons subversion swig zlib1g-dev
+
 BUILD_JOBS=4

 GEM5_ARCH="ALPHA ARM MIPS NULL POWER SPARC X86"

--
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[gem5-dev] Change in public/gem5[master]: tests: Add a jenkins test script

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3781



Change subject: tests: Add a jenkins test script
..

tests: Add a jenkins test script

Change-Id: I7470b5c5856d039f33d99b45582dc4f2cc06b921
---
A tests/jenkins.sh
1 file changed, 67 insertions(+), 0 deletions(-)



diff --git a/tests/jenkins.sh b/tests/jenkins.sh
new file mode 100755
index 000..5bfea29
--- /dev/null
+++ b/tests/jenkins.sh
@@ -0,0 +1,67 @@
+#!/bin/sh
+#
+# Copyright (c) 2016 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+set -e
+
+BUILD_JOBS=4
+
+GEM5_ARCH="ALPHA ARM MIPS NULL POWER SPARC X86"
+GEM5_MODE=opt
+
+TARGETS=
+for A in ${GEM5_ARCH}; do
+TARGETS="${TARGETS} build/${A}/gem5.${GEM5_MODE}"
+done
+
+TEST_TARGETS=
+for A in ${GEM5_ARCH}; do
+TEST_TARGETS="${TEST_TARGETS} build/${A}/tests/${GEM5_MODE}/quick"
+done
+
+
+scons --ignore-style $TARGETS -j${BUILD_JOBS}
+
+
+if [ "$?" = "0" ]; then
+  echo "SUCCESS"
+  exit 0
+else
+  echo "FAIL"
+  exit 1
+fi

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[gem5-dev] Change in public/gem5[master]: tests: Add presubmit and continuous jenkins config files

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3783



Change subject: tests: Add presubmit and continuous jenkins config files
..

tests: Add presubmit and continuous jenkins config files

Change-Id: I0e838b3c831908136bb981df4865aeef8c6c6970
---
A tests/jenkins/continuous.cfg
A tests/jenkins/presubmit.cfg
2 files changed, 8 insertions(+), 0 deletions(-)



diff --git a/tests/jenkins/continuous.cfg b/tests/jenkins/continuous.cfg
new file mode 100644
index 000..6b0d85a
--- /dev/null
+++ b/tests/jenkins/continuous.cfg
@@ -0,0 +1,4 @@
+# Format: //devtools/kokoro/config/proto/build.proto
+
+# Location of the continuous batch script in repository.
+build_file: "jenkins-gem5-prod/tests/jenkins/continuous.sh"
diff --git a/tests/jenkins/presubmit.cfg b/tests/jenkins/presubmit.cfg
new file mode 100644
index 000..742a6fc
--- /dev/null
+++ b/tests/jenkins/presubmit.cfg
@@ -0,0 +1,4 @@
+# Format: //devtools/kokoro/config/proto/build.proto
+
+# Location of the continuous batch script in repository.
+build_file: "jenkins-gem5-prod/tests/jenkins/presubmit.sh"

--
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[gem5-dev] Change in public/gem5[master]: tests: remove all spec tests

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3780



Change subject: tests: remove all spec tests
..

tests: remove all spec tests

Change-Id: I1b03dd48e1e75d8a510c7943dea4cd2a087f5951
---
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt
D  
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini
D  
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json

D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout
D  
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt

D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout
D tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt
D  
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini
D  
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json

D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout
D  
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt

D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout
D tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt
D  
tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini
D  
tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json

D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout
D  
tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt

D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini
D tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json
D 

[gem5-dev] Change in public/gem5[master]: mem: Replace EventWrapper use with EventFunctionWrapper

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/3745 )


Change subject: mem: Replace EventWrapper use with EventFunctionWrapper
..

mem: Replace EventWrapper use with EventFunctionWrapper

NOTE: With this change there is a possibility for `DRAMCtrl::Rank`s
event names to not properly match the rank they were generated by. This
could occur if the public rank member is modified after the Rank's
construction. A patch would mean refactoring Rank and `DRAMCtrl`b to
privatize many of the members of Rank behind getters.

Change-Id: I7b8bd15086f4ffdfd3f40be4aeddac5e786fd78e
Signed-off-by: Sean Wilson 
---
M src/mem/bridge.cc
M src/mem/bridge.hh
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
M src/mem/comm_monitor.cc
M src/mem/comm_monitor.hh
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
M src/mem/dramsim2.cc
M src/mem/dramsim2.hh
M src/mem/serial_link.cc
M src/mem/serial_link.hh
M src/mem/simple_mem.cc
M src/mem/simple_mem.hh
M src/mem/xbar.cc
M src/mem/xbar.hh
18 files changed, 45 insertions(+), 46 deletions(-)


--
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Gerrit-Change-Id: I7b8bd15086f4ffdfd3f40be4aeddac5e786fd78e
Gerrit-Change-Number: 3745
Gerrit-PatchSet: 2
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[gem5-dev] Change in public/gem5[master]: sim: Remove DelayFunction

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3741



Change subject: sim: Remove DelayFunction
..

sim: Remove DelayFunction

`DelayFunction` is unused.

Change-Id: I28aa756054c9b121fe4cfa65c393366f26ccb128
Signed-off-by: Sean Wilson 
---
M src/sim/eventq.hh
1 file changed, 0 insertions(+), 20 deletions(-)



diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index b138f56..9d3c5c3 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -769,26 +769,6 @@
 };

 template 
-void
-DelayFunction(EventQueue *eventq, Tick when, T *object)
-{
-class DelayEvent : public Event
-{
-  private:
-T *object;
-
-  public:
-DelayEvent(T *o)
-: Event(Default_Pri, AutoDelete), object(o)
-{ }
-void process() { (object->*F)(); }
-const char *description() const { return "delay"; }
-};
-
-eventq->schedule(new DelayEvent(object), when);
-}
-
-template 
 class EventWrapper : public Event
 {
   private:

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[gem5-dev] Change in public/gem5[master]: sim, x86: Replace EventWrapper use with EventFunctionWrapper

[Sean Wilson (Gerrit)]

Sean Wilson has uploaded this change for review. (  
https://gem5-review.googlesource.com/3749



Change subject: sim, x86: Replace EventWrapper use with EventFunctionWrapper
..

sim, x86: Replace EventWrapper use with EventFunctionWrapper

Change-Id: Ie1df07b70776208fc3631a73d403024636fc05a9
Signed-off-by: Sean Wilson 
---
M src/arch/x86/pagetable_walker.hh
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
M src/sim/root.cc
M src/sim/root.hh
5 files changed, 8 insertions(+), 8 deletions(-)



diff --git a/src/arch/x86/pagetable_walker.hh  
b/src/arch/x86/pagetable_walker.hh

index 9be35e6..d71db7e 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -178,7 +178,7 @@
 /**
  * Event used to call startWalkWrapper.
  **/
-EventWrapper  
startWalkWrapperEvent;

+EventFunctionWrapper startWalkWrapperEvent;

 // Functions for dealing with packets.
 bool recvTimingResp(PacketPtr pkt);
@@ -205,7 +205,7 @@
 funcState(this, NULL, NULL, true), tlb(NULL),  
sys(params->system),

 masterId(sys->getMasterId(name())),
 numSquashable(params->num_squash_per_cycle),
-startWalkWrapperEvent(this)
+startWalkWrapperEvent([this]{ startWalkWrapper(); }, name())
 {
 }
 };
diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index 05ce42b..d362da6 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -194,7 +194,7 @@
  * ThermalModel
  */
 ThermalModel::ThermalModel(const Params *p)
-: ClockedObject(p), stepEvent(this), _step(p->step)
+: ClockedObject(p), stepEvent([this]{ doStep(); }, name()),  
_step(p->step)

 {
 }

diff --git a/src/sim/power/thermal_model.hh b/src/sim/power/thermal_model.hh
index 7ee4ffd..b47061d 100644
--- a/src/sim/power/thermal_model.hh
+++ b/src/sim/power/thermal_model.hh
@@ -179,7 +179,7 @@
 std::vector  eq_nodes;

 /** Stepping event to update the model values */
-EventWrapper stepEvent;
+EventFunctionWrapper stepEvent;

 /** Step in seconds for thermal updates */
 double _step;
diff --git a/src/sim/root.cc b/src/sim/root.cc
index 752632b..f4aabad 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -104,8 +104,9 @@
 timeSyncEnable(en);
 }

-Root::Root(RootParams *p) : SimObject(p), _enabled(false),
-_periodTick(p->time_sync_period), syncEvent(this)
+Root::Root(RootParams *p)
+: SimObject(p), _enabled(false), _periodTick(p->time_sync_period),
+  syncEvent([this]{ timeSync(); }, name())
 {
 _period.setTick(p->time_sync_period);
 _spinThreshold.setTick(p->time_sync_spin_threshold);
diff --git a/src/sim/root.hh b/src/sim/root.hh
index 7273a07..db207a7 100644
--- a/src/sim/root.hh
+++ b/src/sim/root.hh
@@ -60,8 +60,7 @@
 Time lastTime;

 void timeSync();
-EventWrapper syncEvent;
-friend class EventWrapper;
+EventFunctionWrapper syncEvent;

   public:
 /**

--
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Gerrit-Change-Id: Ie1df07b70776208fc3631a73d403024636fc05a9
Gerrit-Change-Number: 3749
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