Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround

[Tapani Pälli]

On 14.02.2018 09:54, Tapani Pälli wrote:



On 14.02.2018 09:38, Rogovin, Kevin wrote:

Hi,

  The 3rd patch, "i965: use ASTC5x5 workaround in 
intel_miptree_texture_aux_usage has issues:
    1. Definitely: brw_draw lacks the call to 
gen9_astc5x5_perform_wa() which generates the needed flush between 
batchbuffers


Now it happens via intel_miptree_prepare_texture (in 
intel_miptree_texture_aux_usage).


No it does not, sorry for that :) Yeah I believe I need to restore that.




    2.  Uneasy: I am nervous about hitting 
intel_miptree_texture_aux_usage() as it is used in lots of places 
directly and indirectly. The interaction with blorp resolve makes me 
very uneasy  I would rather restore the bool argument disable_aux  
to intel_miptree_prepare_render() to keep the ASTC evil a little more 
localized (the function is used only in brw_draw.c for resolving inputs).


IMO it feels more centralized .. but no strong opinions here. I haven't 
spotted any regressions because of this.




-Kevin


-Original Message-
From: Palli, Tapani
Sent: Monday, February 12, 2018 10:14 AM
To: Rogovin, Kevin ; Jason Ekstrand 


Cc: ML mesa-dev 
Subject: Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround



On 02/12/2018 09:44 AM, Tapani Pälli wrote:

Hi;

On 02/08/2018 09:50 AM, Rogovin, Kevin wrote:

Hi,

I gave it a whirl of setting the .mocs field set to 0 passed to
isl_surf_fill_state() ALWAYS. Sadly CarChase GLES continued to hang
(where as the GL did not because it does not use ASTC). This makes
sense since MOCS (atleast last time I looked at it) only really
controls cache usage for L3 and eLLC (please anyone correct me if I
am wrong in this) whereas the issue is that the samplers mess up how
they deal with its own (private) cache.

It really is nasty that it appears (as of now) that this complicated
work around is needed and needs to somehow be re-implemented in anv
as well.


It seems surrounding code has changed so that these patches need some
changes. Kevin, are you planning to rebase/refactor these changes?


FYI I've rebased the patches and did additional porting (because of 
commit df13588d21) here:


https://cgit.freedesktop.org/~tpalli/mesa/log/?h=astc5x5

Let me know if this looks OK for you.




-Kevin

*From:*Jason Ekstrand [mailto:ja...@jlekstrand.net]
*Sent:* Thursday, February 8, 2018 2:47 AM
*To:* Rogovin, Kevin 
*Cc:* ML mesa-dev 
*Subject:* Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround

Random thought:

Nanley and I were talking about this just now and I was complaining
about how much I hate the fact that this workaround exists because we
can't implement it in Vulkan.  Then I got an idea.  What would happen
if we just set MOCS to zero (uncached) for ASTC 5x5 textures?  Does
that make the hang go away?  How bad is the car chase performance
with that compared to this series?  It's a bit of a big hammer but
has the advantage of simplicity.  If it causes performance to tank on
anything then then the more complex solution is probably worth it but
I thought it was worth a try.

--Jason

On Thu, Dec 14, 2017 at 9:39 AM, > wrote:

 From: Kevin Rogovin >

 This patch series implements a needed workaround for Gen9 for
ASTC5x5
 sampler reads. The crux of the work around is to make sure that
the
 sampler does not read an ASTC5x5 texture and a surface with an
auxilary
 buffer without having a texture cache invalidate and command
streamer
 stall between such accesses.

 With this patch series applied to the (current) master branch of
mesa,
 carchase works on my SKL GT4.

 v2:
    Rename workaround functions from brw_ to gen9_
    (suggested/requested by Topi Pohjolainen).

    Place texture resolve to avoid using auxilary surface
    when ASTC5x5 is detected in brw_predraw_resolve_inputs()
    instead of another detected function; doing so allows
    one to avoid walking the textures again.
    (suggested/requested by Topi Pohjolainen).

    Emit command streamer stall in addition to texture
    invalidate.
    (original short-coming caught by Jason Ekstrand)

    Place workaround function in (new) dedicated file.

    Minor path re-ordering to accomodate changes.

 Kevin Rogovin (5):
    i965: define astx5x5 workaround infrastructure
    i965: set ASTC5x5 workaround texture type tracking on texture
 validate
    i965: use ASTC5x5 workaround in brw_draw
    i965: use ASTC5x5 workaround in brw_compute
    i965: ASTC5x5 workaround logic for blorp

   src/mesa/drivers/dri/i965/Makefile.sources       |  1 +
   src/mesa/drivers/dri/i965/brw_compute.c          |  6 
   src/mesa/drivers/dri/i965/brw_context.c          

Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround

[Tapani Pälli]

On 14.02.2018 09:38, Rogovin, Kevin wrote:

Hi,

  The 3rd patch, "i965: use ASTC5x5 workaround in 
intel_miptree_texture_aux_usage has issues:
   
1. Definitely: brw_draw lacks the call to gen9_astc5x5_perform_wa() which generates the needed flush between batchbuffers


Now it happens via intel_miptree_prepare_texture (in 
intel_miptree_texture_aux_usage).




2.  Uneasy: I am nervous about hitting intel_miptree_texture_aux_usage() as 
it is used in lots of places directly and indirectly. The interaction with 
blorp resolve makes me very uneasy  I would rather restore the bool 
argument disable_aux  to intel_miptree_prepare_render() to keep the ASTC evil a 
little more localized (the function is used only in brw_draw.c for resolving 
inputs).


IMO it feels more centralized .. but no strong opinions here. I haven't 
spotted any regressions because of this.




-Kevin


-Original Message-
From: Palli, Tapani
Sent: Monday, February 12, 2018 10:14 AM
To: Rogovin, Kevin ; Jason Ekstrand 

Cc: ML mesa-dev 
Subject: Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround



On 02/12/2018 09:44 AM, Tapani Pälli wrote:

Hi;

On 02/08/2018 09:50 AM, Rogovin, Kevin wrote:

Hi,

I gave it a whirl of setting the .mocs field set to 0 passed to
isl_surf_fill_state() ALWAYS. Sadly CarChase GLES continued to hang
(where as the GL did not because it does not use ASTC). This makes
sense since MOCS (atleast last time I looked at it) only really
controls cache usage for L3 and eLLC (please anyone correct me if I
am wrong in this) whereas the issue is that the samplers mess up how
they deal with its own (private) cache.

It really is nasty that it appears (as of now) that this complicated
work around is needed and needs to somehow be re-implemented in anv
as well.


It seems surrounding code has changed so that these patches need some
changes. Kevin, are you planning to rebase/refactor these changes?


FYI I've rebased the patches and did additional porting (because of commit 
df13588d21) here:

https://cgit.freedesktop.org/~tpalli/mesa/log/?h=astc5x5

Let me know if this looks OK for you.




-Kevin

*From:*Jason Ekstrand [mailto:ja...@jlekstrand.net]
*Sent:* Thursday, February 8, 2018 2:47 AM
*To:* Rogovin, Kevin 
*Cc:* ML mesa-dev 
*Subject:* Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround

Random thought:

Nanley and I were talking about this just now and I was complaining
about how much I hate the fact that this workaround exists because we
can't implement it in Vulkan.  Then I got an idea.  What would happen
if we just set MOCS to zero (uncached) for ASTC 5x5 textures?  Does
that make the hang go away?  How bad is the car chase performance
with that compared to this series?  It's a bit of a big hammer but
has the advantage of simplicity.  If it causes performance to tank on
anything then then the more complex solution is probably worth it but
I thought it was worth a try.

--Jason

On Thu, Dec 14, 2017 at 9:39 AM, > wrote:

     From: Kevin Rogovin >

     This patch series implements a needed workaround for Gen9 for
ASTC5x5
     sampler reads. The crux of the work around is to make sure that
the
     sampler does not read an ASTC5x5 texture and a surface with an
auxilary
     buffer without having a texture cache invalidate and command
streamer
     stall between such accesses.

     With this patch series applied to the (current) master branch of
mesa,
     carchase works on my SKL GT4.

     v2:
    Rename workaround functions from brw_ to gen9_
    (suggested/requested by Topi Pohjolainen).

    Place texture resolve to avoid using auxilary surface
    when ASTC5x5 is detected in brw_predraw_resolve_inputs()
    instead of another detected function; doing so allows
    one to avoid walking the textures again.
    (suggested/requested by Topi Pohjolainen).

    Emit command streamer stall in addition to texture
    invalidate.
    (original short-coming caught by Jason Ekstrand)

    Place workaround function in (new) dedicated file.

    Minor path re-ordering to accomodate changes.

     Kevin Rogovin (5):
    i965: define astx5x5 workaround infrastructure
    i965: set ASTC5x5 workaround texture type tracking on texture
     validate
    i965: use ASTC5x5 workaround in brw_draw
    i965: use ASTC5x5 workaround in brw_compute
    i965: ASTC5x5 workaround logic for blorp

   src/mesa/drivers/dri/i965/Makefile.sources       |  1 +
   src/mesa/drivers/dri/i965/brw_compute.c          |  6 
   src/mesa/drivers/dri/i965/brw_context.c          |  6 
   src/mesa/drivers/dri/i965/brw_context.h          | 24

   

Re: [Mesa-dev] [PATCH v3] intel/tools: new intel_sanitize_gpu tool

[Rogovin, Kevin]

Reviewed by: kevin.rogovin [at] intel.com

-Original Message-
From: Phillips, Scott D 
Sent: Friday, February 9, 2018 3:11 AM
To: mesa-dev@lists.freedesktop.org; Rogovin, Kevin 
Subject: [PATCH v3] intel/tools: new intel_sanitize_gpu tool

From: Kevin Rogovin 

Adds a new debug tool to pad each GEM BO allocated with (weak) pseudo-random 
noise values which are then checked after each batchbuffer dispatch to the 
kernel. This can be quite valuable to find diffucult to track down heisenberg 
style bugs.

[scott.d.phill...@intel.com: split to separate tool]

v2: (by Scott D Phillips)
- track gem handles per fd (Kevin)
- remove handles on GEM_CLOSE (Kevin)
- ignore prime handles
- meson & shell script

v3: (by Scott D Phillips)
- don't track prime bos at all (Kevin)
- protect the hash table with a mutex (Kevin)
- hook fds by drm_version.name, not path (Chris Wilson)
---
 src/intel/tools/intel_sanitize_gpu.c  | 430 ++
 src/intel/tools/intel_sanitize_gpu.in |   4 +
 src/intel/tools/meson.build   |  25 ++
 3 files changed, 459 insertions(+)
 create mode 100644 src/intel/tools/intel_sanitize_gpu.c
 create mode 100755 src/intel/tools/intel_sanitize_gpu.in

diff --git a/src/intel/tools/intel_sanitize_gpu.c 
b/src/intel/tools/intel_sanitize_gpu.c
new file mode 100644
index 000..9b49b0bbf22
--- /dev/null
+++ b/src/intel/tools/intel_sanitize_gpu.c
@@ -0,0 +1,430 @@
+/*
+ * Copyright © 2015-2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person 
+obtaining a
+ * copy of this software and associated documentation files (the 
+"Software"),
+ * to deal in the Software without restriction, including without 
+limitation
+ * the rights to use, copy, modify, merge, publish, distribute, 
+sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom 
+the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the 
+next
+ * paragraph) shall be included in all copies or substantial portions 
+of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
+MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT 
+SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 
+OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 
+ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
+DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#undef _FILE_OFFSET_BITS /* prevent #define open open64 */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "util/hash_table.h"
+
+#define INTEL_LOG_TAG "INTEL-SANITIZE-GPU"
+#include "common/intel_log.h"
+#include "common/gen_clflush.h"
+
+static int (*libc_open)(const char *pathname, int flags, mode_t mode); 
+static int (*libc_close)(int fd); static int (*libc_ioctl)(int fd, 
+unsigned long request, void *argp); static int (*libc_fcntl)(int fd, 
+int cmd, int param);
+
+#define DRM_MAJOR 226
+
+/* TODO: we want to make sure that the padding forces
+ * the BO to take another page on the (PP)GTT; 4KB
+ * may or may not be the page size for the BO. Indeed,
+ * depending on GPU, kernel version and GEM size, the
+ * page size can be one of 4KB, 64KB or 2M.
+ */
+#define PADDING_SIZE 4096
+
+struct refcnt_hash_table {
+   struct hash_table *t;
+   int refcnt;
+};
+
+pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
+#define MUTEX_LOCK() do {\
+   if (unlikely(pthread_mutex_lock())) {   \
+  intel_loge("mutex_lock failed");   \
+  abort();   \
+   } \
+} while (0)
+#define MUTEX_UNLOCK() do {  \
+   if (unlikely(pthread_mutex_unlock())) { \
+  intel_loge("mutex_unlock failed"); \
+  abort();   \
+   } \
+} while (0)
+
+static struct hash_table *fds_to_bo_sizes = NULL;
+
+static inline struct hash_table*
+bo_size_table(int fd)
+{
+   struct hash_entry *e = _mesa_hash_table_search(fds_to_bo_sizes,
+  (void*)(uintptr_t)fd);
+   return e ? ((struct refcnt_hash_table*)e->data)->t : NULL; }
+
+static inline uint64_t
+bo_size(int fd, uint32_t handle)
+{
+   struct hash_table *t = bo_size_table(fd);
+   if (!t)
+  return UINT64_MAX;
+   struct hash_entry *e = _mesa_hash_table_search(t, (void*)(uintptr_t)handle);
+   return e ? (uint64_t)e->data : UINT64_MAX; }
+
+static inline bool
+is_drm_fd(int fd)
+{
+   return !!bo_size_table(fd);
+}
+
+static inline 

Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround

[Rogovin, Kevin]

Hi,

 The 3rd patch, "i965: use ASTC5x5 workaround in 
intel_miptree_texture_aux_usage has issues:
  
   1. Definitely: brw_draw lacks the call to gen9_astc5x5_perform_wa() which 
generates the needed flush between batchbuffers

   2.  Uneasy: I am nervous about hitting intel_miptree_texture_aux_usage() as 
it is used in lots of places directly and indirectly. The interaction with 
blorp resolve makes me very uneasy  I would rather restore the bool 
argument disable_aux  to intel_miptree_prepare_render() to keep the ASTC evil a 
little more localized (the function is used only in brw_draw.c for resolving 
inputs).

-Kevin


-Original Message-
From: Palli, Tapani 
Sent: Monday, February 12, 2018 10:14 AM
To: Rogovin, Kevin ; Jason Ekstrand 

Cc: ML mesa-dev 
Subject: Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround



On 02/12/2018 09:44 AM, Tapani Pälli wrote:
> Hi;
> 
> On 02/08/2018 09:50 AM, Rogovin, Kevin wrote:
>> Hi,
>>
>> I gave it a whirl of setting the .mocs field set to 0 passed to
>> isl_surf_fill_state() ALWAYS. Sadly CarChase GLES continued to hang 
>> (where as the GL did not because it does not use ASTC). This makes 
>> sense since MOCS (atleast last time I looked at it) only really 
>> controls cache usage for L3 and eLLC (please anyone correct me if I 
>> am wrong in this) whereas the issue is that the samplers mess up how 
>> they deal with its own (private) cache.
>>
>> It really is nasty that it appears (as of now) that this complicated 
>> work around is needed and needs to somehow be re-implemented in anv 
>> as well.
> 
> It seems surrounding code has changed so that these patches need some 
> changes. Kevin, are you planning to rebase/refactor these changes?

FYI I've rebased the patches and did additional porting (because of commit 
df13588d21) here:

https://cgit.freedesktop.org/~tpalli/mesa/log/?h=astc5x5

Let me know if this looks OK for you.

> 
>> -Kevin
>>
>> *From:*Jason Ekstrand [mailto:ja...@jlekstrand.net]
>> *Sent:* Thursday, February 8, 2018 2:47 AM
>> *To:* Rogovin, Kevin 
>> *Cc:* ML mesa-dev 
>> *Subject:* Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround
>>
>> Random thought:
>>
>> Nanley and I were talking about this just now and I was complaining 
>> about how much I hate the fact that this workaround exists because we 
>> can't implement it in Vulkan.  Then I got an idea.  What would happen 
>> if we just set MOCS to zero (uncached) for ASTC 5x5 textures?  Does 
>> that make the hang go away?  How bad is the car chase performance 
>> with that compared to this series?  It's a bit of a big hammer but 
>> has the advantage of simplicity.  If it causes performance to tank on 
>> anything then then the more complex solution is probably worth it but 
>> I thought it was worth a try.
>>
>> --Jason
>>
>> On Thu, Dec 14, 2017 at 9:39 AM, > > wrote:
>>
>>     From: Kevin Rogovin >     >
>>
>>     This patch series implements a needed workaround for Gen9 for 
>> ASTC5x5
>>     sampler reads. The crux of the work around is to make sure that 
>> the
>>     sampler does not read an ASTC5x5 texture and a surface with an 
>> auxilary
>>     buffer without having a texture cache invalidate and command 
>> streamer
>>     stall between such accesses.
>>
>>     With this patch series applied to the (current) master branch of 
>> mesa,
>>     carchase works on my SKL GT4.
>>
>>     v2:
>>    Rename workaround functions from brw_ to gen9_
>>    (suggested/requested by Topi Pohjolainen).
>>
>>    Place texture resolve to avoid using auxilary surface
>>    when ASTC5x5 is detected in brw_predraw_resolve_inputs()
>>    instead of another detected function; doing so allows
>>    one to avoid walking the textures again.
>>    (suggested/requested by Topi Pohjolainen).
>>
>>    Emit command streamer stall in addition to texture
>>    invalidate.
>>    (original short-coming caught by Jason Ekstrand)
>>
>>    Place workaround function in (new) dedicated file.
>>
>>    Minor path re-ordering to accomodate changes.
>>
>>     Kevin Rogovin (5):
>>    i965: define astx5x5 workaround infrastructure
>>    i965: set ASTC5x5 workaround texture type tracking on texture
>>     validate
>>    i965: use ASTC5x5 workaround in brw_draw
>>    i965: use ASTC5x5 workaround in brw_compute
>>    i965: ASTC5x5 workaround logic for blorp
>>
>>   src/mesa/drivers/dri/i965/Makefile.sources       |  1 +
>>   src/mesa/drivers/dri/i965/brw_compute.c          |  6 
>>   src/mesa/drivers/dri/i965/brw_context.c          |  6 
>>   src/mesa/drivers/dri/i965/brw_context.h          | 24
>> 
>>   src/mesa/drivers/dri/i965/brw_draw.c         

Re: [Mesa-dev] [PATCH 1/5] i965/tiled_memcpy: change linear pointer from (0, 0) to (xt1, yt1)

[Kenneth Graunke]

On Tuesday, January 9, 2018 11:16:58 PM PST Scott D Phillips wrote:
> In all current uses, the linear surface is only allocated starting
> at (xt1, yt1) anyway, so this improves the calling ergonomics.
> ---
>  src/mesa/drivers/dri/i965/intel_pixel_read.c   |  2 +-
>  src/mesa/drivers/dri/i965/intel_tex_image.c|  4 ++--
>  src/mesa/drivers/dri/i965/intel_tiled_memcpy.c | 16 
>  3 files changed, 11 insertions(+), 11 deletions(-)

Patches 1 and 3 are:
Reviewed-by: Kenneth Graunke 

Feel free to push those two (assuming you've tested them on Jenkins).



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[Mesa-dev] [PATCH] r600/sb: fix rotated register in while loop

[Dave Airlie]

From: Dave Airlie 

A bunch of CTS tests led me to write
tests/shaders/ssa/fs-while-loop-rotate-value.shader_test
which r600/sb always fell over on.

This patch fixes it, but I'll probably never be 100% sure why.

Anyways what appears to be happening is when gcm is scheduling
the copy_movs used for phis, we have 4 copy_movs in the scheduling
queue, one of them releases a new copy_mov and it gets pushed
to the the front of the scheduling queue, but for correctness
we rely on the previous copy_movs getting emitted first. This
places copy_movs in order on the list.

So if the list is empty, it puts it at the front, if the list
has just copy_movs in it, it goes to the end, otherwise
we iterate the list and insert it between the copy_movs and
subsequent instructions.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/sb/sb_gcm.cpp | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/sb/sb_gcm.cpp 
b/src/gallium/drivers/r600/sb/sb_gcm.cpp
index 7776a10fc8..7b4df8bd52 100644
--- a/src/gallium/drivers/r600/sb/sb_gcm.cpp
+++ b/src/gallium/drivers/r600/sb/sb_gcm.cpp
@@ -637,8 +637,23 @@ void gcm::add_ready(node *n) {
sched_queue_id sq = sh.get_queue_id(n);
if (n->flags & NF_SCHEDULE_EARLY)
bu_ready_early[sq].push_back(n);
-   else if (sq == SQ_ALU && n->is_copy_mov())
-   bu_ready[sq].push_front(n);
+   else if (sq == SQ_ALU && n->is_copy_mov()) {
+   if (bu_ready[sq].empty())
+   bu_ready[sq].push_front(n);
+   else {
+   bool inserted = false;
+   for (sched_queue::iterator I = bu_ready[sq].begin(), E 
= bu_ready[sq].end(); I != E; I++) {
+   node *a = *I;
+   if (!a->is_copy_mov()) {
+   bu_ready[sq].insert(I, n);
+   inserted = true;
+   break;
+   }
+   }
+   if (!inserted)
+   bu_ready[sq].push_back(n);
+   }
+   }
else if (n->is_alu_inst()) {
alu_node *a = static_cast(n);
if (a->bc.op_ptr->flags & AF_PRED && a->dst[2]) {
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 1/2] intel/aubinator: Correctly decode INTERFACE_DESCRIPTOR_DATA

[Kenneth Graunke]

On Monday, February 12, 2018 7:35:04 PM PST Jason Ekstrand wrote:
> ---
>  src/intel/tools/gen_batch_decoder.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/intel/tools/gen_batch_decoder.c 
> b/src/intel/tools/gen_batch_decoder.c
> index 78db83b..1a8794c 100644
> --- a/src/intel/tools/gen_batch_decoder.c
> +++ b/src/intel/tools/gen_batch_decoder.c
> @@ -285,7 +285,7 @@ handle_media_interface_descriptor_load(struct 
> gen_batch_decode_ctx *ctx,
> for (int i = 0; i < descriptor_count; i++) {
>fprintf(ctx->fp, "descriptor %d: %08x\n", i, descriptor_offset);
>  
> -  ctx_print_group(ctx, inst, desc_addr, desc_map);
> +  ctx_print_group(ctx, desc, desc_addr, desc_map);
>  
>gen_field_iterator_init(, desc, desc_map, 0, false);
>uint64_t ksp;
> 

This patch is:
Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 2/2] anv/pipeline: Set the correct binding count for compute shaders

[Kenneth Graunke]

On Monday, February 12, 2018 7:35:05 PM PST Jason Ekstrand wrote:
> ---
>  src/intel/vulkan/genX_pipeline.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/intel/vulkan/genX_pipeline.c 
> b/src/intel/vulkan/genX_pipeline.c
> index 45ebe31..4aee9ec 100644
> --- a/src/intel/vulkan/genX_pipeline.c
> +++ b/src/intel/vulkan/genX_pipeline.c
> @@ -1836,7 +1836,7 @@ compute_pipeline_create(
>.KernelStartPointer = cs_bin->kernel.offset,
>  
>.SamplerCount   = get_sampler_count(cs_bin),
> -  .BindingTableEntryCount = get_binding_table_entry_count(cs_bin),
> +  .BindingTableEntryCount = 1 + MIN2(cs_bin->bind_map.surface_count, 30),
>.BarrierEnable  = cs_prog_data->uses_barrier,
>.SharedLocalMemorySize  =
>   encode_slm_size(GEN_GEN, cs_prog_data->base.total_shared),
> 

Shouldn't this be MIN2(cs_bin->bind_map.surface_count, 31)?  It's simply
a U5 value, not a U5-1 value...and says there are a maximum of 31 things
that can be prefetched.

While we're here, I don't understand why get_binding_table_entry_count
is DIV_ROUND_UP(bin->bind_map.surface_count, 32)...the docs for
3DSTATE_VS indicate that it's simply a 0..255 value.


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Re: [Mesa-dev] [PATCH] i965: Add gl_state_index casts for PATCH_VERTICES_IN

[Kenneth Graunke]

On Tuesday, February 13, 2018 2:57:07 PM PST Jason Ekstrand wrote:
> This fixes the build in clang
> ---
>  src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp 
> b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
> index 10a4ff4..69da83a 100644
> --- a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
> @@ -254,7 +254,8 @@ brw_nir_lower_patch_vertices_in_to_uniform(nir_shader 
> *nir)
>gl_state_index16 tokens[STATE_LENGTH] = {
>   STATE_INTERNAL,
>   nir->info.stage == MESA_SHADER_TESS_CTRL ?
> -STATE_TCS_PATCH_VERTICES_IN : STATE_TES_PATCH_VERTICES_IN,
> +(gl_state_index16)STATE_TCS_PATCH_VERTICES_IN :
> +(gl_state_index16)STATE_TES_PATCH_VERTICES_IN,
>};
>var->num_state_slots = 1;
>var->state_slots =
> 

This is fine, but I prefer your plan from IRC:

1. Add STATE_MAX_VALUE = 0x to the enum.
2. Mark the enum PACKED.
3. Drop gl_state_index16 again, since gl_state_index should now be the
   desired size, and also an actual enum so it follows the actual C++
   enum rules.

I suppose the downside is that it could cause "case not handled in
switch" warnings...

--Ken


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Re: [Mesa-dev] [PATCH 1/2] nir: retain pixel_center_integer information when lowering gl_FragCoord

[Kenneth Graunke]

On Tuesday, February 13, 2018 10:00:44 PM PST Timothy Arceri wrote:
> On 14/02/18 16:24, Jason Ekstrand wrote:
> > First off, you should add an index to the intrinsic if you're going to 
> > do this and it should probably be set elsewhere.  Otherwise, it becomes 
> > this magic secret radeonsi thing.
> 
> Ah yes that's how it's done, I thought there was a better way to do this 
> thanks.
> 
> Although what do you mean by set it elsewhere? This is where the 
> intrinsic is created and the system variable goes away I don't see how 
> it can be set elsewhere.

Basically, add a shader_info::pixel_center_integer flag, and have
glsl_to_nir() look for the decorated fragcoord variable and set that.

Honestly, it might make sense to set a global shader_info field in
the GLSL frontend itself, and stop storing decorations on the fragcoord
variable in the first place.  Make NIR and the backends follow the new
SPIR-V convention and make the GLSL frontend deal with GLSL oddities.

It looks like the radeonsi backend sees this and sets a global flag,
so global would probably be a better fit anyway...


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[Mesa-dev] [PATCH 5/5] ac: use correct LLVM opcodes for ordered comparisons

[Timothy Arceri]

Fixes glsl-1.30/execution/isinf-and-isnan* piglit tests for
radeonsi and should fix SPIRV errors when LLVM optimises away
the workarounds in vtn_handle_alu() for handling ordered
comparisons.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104905
---
 src/amd/common/ac_nir_to_llvm.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index a0c5680205..e81f86bb08 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1792,16 +1792,16 @@ static void visit_alu(struct ac_nir_context *ctx, const 
nir_alu_instr *instr)
result = emit_int_cmp(>ac, LLVMIntUGE, src[0], src[1]);
break;
case nir_op_feq:
-   result = emit_float_cmp(>ac, LLVMRealUEQ, src[0], src[1]);
+   result = emit_float_cmp(>ac, LLVMRealOEQ, src[0], src[1]);
break;
case nir_op_fne:
-   result = emit_float_cmp(>ac, LLVMRealUNE, src[0], src[1]);
+   result = emit_float_cmp(>ac, LLVMRealONE, src[0], src[1]);
break;
case nir_op_flt:
-   result = emit_float_cmp(>ac, LLVMRealULT, src[0], src[1]);
+   result = emit_float_cmp(>ac, LLVMRealOLT, src[0], src[1]);
break;
case nir_op_fge:
-   result = emit_float_cmp(>ac, LLVMRealUGE, src[0], src[1]);
+   result = emit_float_cmp(>ac, LLVMRealOGE, src[0], src[1]);
break;
case nir_op_ufeq:
result = emit_float_cmp(>ac, LLVMRealUEQ, src[0], src[1]);
-- 
2.14.3

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[Mesa-dev] [RFC 1/5] nir: add unordered opcode variants of float comparisons

[Timothy Arceri]

This will enable the nir->llvm translation to work correctly.
---
 src/compiler/nir/nir_opcodes.py | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py
index 278562b2bd..61c004c6f8 100644
--- a/src/compiler/nir/nir_opcodes.py
+++ b/src/compiler/nir/nir_opcodes.py
@@ -445,6 +445,10 @@ binop_compare("flt", tfloat, "", "src0 < src1")
 binop_compare("fge", tfloat, "", "src0 >= src1")
 binop_compare("feq", tfloat, commutative, "src0 == src1")
 binop_compare("fne", tfloat, commutative, "src0 != src1")
+binop_compare("uflt", tfloat, "", "src0 < src1")
+binop_compare("ufge", tfloat, "", "src0 >= src1")
+binop_compare("ufeq", tfloat, commutative, "src0 == src1")
+binop_compare("ufne", tfloat, commutative, "src0 != src1")
 binop_compare("ilt", tint, "", "src0 < src1")
 binop_compare("ige", tint, "", "src0 >= src1")
 binop_compare("ieq", tint, commutative, "src0 == src1")
-- 
2.14.3

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[Mesa-dev] [RFC 2/5] i965: add support for unordered float comparison opcodes

[Timothy Arceri]

---
 src/intel/compiler/brw_fs_nir.cpp   | 10 +-
 src/intel/compiler/brw_vec4_nir.cpp |  4 
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index 0d77564930..cf3df75cd5 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1011,7 +1011,11 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
case nir_op_flt:
case nir_op_fge:
case nir_op_feq:
-   case nir_op_fne: {
+   case nir_op_fne:
+   case nir_op_uflt:
+   case nir_op_ufge:
+   case nir_op_ufeq:
+   case nir_op_ufne: {
   fs_reg dest = result;
   if (nir_src_bit_size(instr->src[0].src) > 32) {
  dest = bld.vgrf(BRW_REGISTER_TYPE_DF, 1);
@@ -1019,15 +1023,19 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
   brw_conditional_mod cond;
   switch (instr->op) {
   case nir_op_flt:
+  case nir_op_uflt:
  cond = BRW_CONDITIONAL_L;
  break;
   case nir_op_fge:
+  case nir_op_ufge:
  cond = BRW_CONDITIONAL_GE;
  break;
   case nir_op_feq:
+  case nir_op_ufeq:
  cond = BRW_CONDITIONAL_Z;
  break;
   case nir_op_fne:
+  case nir_op_ufne:
  cond = BRW_CONDITIONAL_NZ;
  break;
   default:
diff --git a/src/intel/compiler/brw_vec4_nir.cpp 
b/src/intel/compiler/brw_vec4_nir.cpp
index 7131fa06b4..1b50d4265a 100644
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -967,16 +967,19 @@ brw_conditional_for_nir_comparison(nir_op op)
 {
switch (op) {
case nir_op_flt:
+   case nir_op_uflt:
case nir_op_ilt:
case nir_op_ult:
   return BRW_CONDITIONAL_L;
 
case nir_op_fge:
+   case nir_op_ufge:
case nir_op_ige:
case nir_op_uge:
   return BRW_CONDITIONAL_GE;
 
case nir_op_feq:
+   case nir_op_ufeq:
case nir_op_ieq:
case nir_op_ball_fequal2:
case nir_op_ball_iequal2:
@@ -987,6 +990,7 @@ brw_conditional_for_nir_comparison(nir_op op)
   return BRW_CONDITIONAL_Z;
 
case nir_op_fne:
+   case nir_op_ufne:
case nir_op_ine:
case nir_op_bany_fnequal2:
case nir_op_bany_inequal2:
-- 
2.14.3

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[Mesa-dev] [RFC 3/5] ac: add support for unordered float comparison opcodes

[Timothy Arceri]

---
 src/amd/common/ac_nir_to_llvm.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 8d1eed241f..a0c5680205 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1803,6 +1803,18 @@ static void visit_alu(struct ac_nir_context *ctx, const 
nir_alu_instr *instr)
case nir_op_fge:
result = emit_float_cmp(>ac, LLVMRealUGE, src[0], src[1]);
break;
+   case nir_op_ufeq:
+   result = emit_float_cmp(>ac, LLVMRealUEQ, src[0], src[1]);
+   break;
+   case nir_op_ufne:
+   result = emit_float_cmp(>ac, LLVMRealUNE, src[0], src[1]);
+   break;
+   case nir_op_uflt:
+   result = emit_float_cmp(>ac, LLVMRealULT, src[0], src[1]);
+   break;
+   case nir_op_ufge:
+   result = emit_float_cmp(>ac, LLVMRealUGE, src[0], src[1]);
+   break;
case nir_op_fabs:
result = emit_intrin_1f_param(>ac, "llvm.fabs",
  ac_to_float_type(>ac, 
def_type), src[0]);
-- 
2.14.3

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[Mesa-dev] [RFC 4/5] spirv: make use of unordered float comparison opcodes

[Timothy Arceri]

---
 src/compiler/spirv/vtn_alu.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index d0c9e31693..fd36c6537b 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -326,26 +326,26 @@ vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b,
 * ordered.
 */
case SpvOpFOrdEqual:return nir_op_feq;
-   case SpvOpFUnordEqual:  return nir_op_feq;
+   case SpvOpFUnordEqual:  return nir_op_ufeq;
case SpvOpINotEqual:return nir_op_ine;
case SpvOpFOrdNotEqual: return nir_op_fne;
-   case SpvOpFUnordNotEqual:   return nir_op_fne;
+   case SpvOpFUnordNotEqual:   return nir_op_ufne;
case SpvOpULessThan:return nir_op_ult;
case SpvOpSLessThan:return nir_op_ilt;
case SpvOpFOrdLessThan: return nir_op_flt;
-   case SpvOpFUnordLessThan:   return nir_op_flt;
+   case SpvOpFUnordLessThan:   return nir_op_uflt;
case SpvOpUGreaterThan:  *swap = true;  return nir_op_ult;
case SpvOpSGreaterThan:  *swap = true;  return nir_op_ilt;
case SpvOpFOrdGreaterThan:   *swap = true;  return nir_op_flt;
-   case SpvOpFUnordGreaterThan: *swap = true;  return nir_op_flt;
+   case SpvOpFUnordGreaterThan: *swap = true;  return nir_op_uflt;
case SpvOpULessThanEqual:*swap = true;  return nir_op_uge;
case SpvOpSLessThanEqual:*swap = true;  return nir_op_ige;
case SpvOpFOrdLessThanEqual: *swap = true;  return nir_op_fge;
-   case SpvOpFUnordLessThanEqual:   *swap = true;  return nir_op_fge;
+   case SpvOpFUnordLessThanEqual:   *swap = true;  return nir_op_ufge;
case SpvOpUGreaterThanEqual:return nir_op_uge;
case SpvOpSGreaterThanEqual:return nir_op_ige;
case SpvOpFOrdGreaterThanEqual: return nir_op_fge;
-   case SpvOpFUnordGreaterThanEqual:   return nir_op_fge;
+   case SpvOpFUnordGreaterThanEqual:   return nir_op_ufge;
 
/* Conversions: */
case SpvOpQuantizeToF16: return nir_op_fquantize2f16;
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 1/2] nir: retain pixel_center_integer information when lowering gl_FragCoord

[Timothy Arceri]

On 14/02/18 16:24, Jason Ekstrand wrote:
First off, you should add an index to the intrinsic if you're going to 
do this and it should probably be set elsewhere.  Otherwise, it becomes 
this magic secret radeonsi thing.


Ah yes that's how it's done, I thought there was a better way to do this 
thanks.


Although what do you mean by set it elsewhere? This is where the 
intrinsic is created and the system variable goes away I don't see how 
it can be set elsewhere.




Second, do you really want this on the intrinsic or would it be better 
as part of shader_info?  It's always been weird to me that it's a layout 
qualifier on gl_FragCoord.  In SPIR-V, it comes in as an execution mode 
which is a very global thing.


On Tue, Feb 13, 2018 at 9:02 PM, Timothy Arceri > wrote:


radeonsi needs to gather this information.
---
  src/compiler/nir/nir_lower_system_values.c | 9 +
  1 file changed, 9 insertions(+)

diff --git a/src/compiler/nir/nir_lower_system_values.c
b/src/compiler/nir/nir_lower_system_values.c
index 3594f4ae5c..f8d8463f7f 100644
--- a/src/compiler/nir/nir_lower_system_values.c
+++ b/src/compiler/nir/nir_lower_system_values.c
@@ -133,6 +133,15 @@ convert_block(nir_block *block, nir_builder *b)
           break;
        }

+      case SYSTEM_VALUE_FRAG_COORD: {
+         nir_intrinsic_op sysval_op =
+            nir_intrinsic_from_system_value(var->data.location);
+         int idx = 0;
+         if (var->data.pixel_center_integer) {
+            idx = 1;
+         }
+         sysval = nir_load_system_value(b, sysval_op, idx);
+      }
        default:
           break;
        }
--
2.14.3

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Re: [Mesa-dev] [PATCH] i965: Add gl_state_index casts for PATCH_VERTICES_IN

[Tapani Pälli]

Reviewed-by: Tapani Pälli 

On 14.02.2018 00:57, Jason Ekstrand wrote:

This fixes the build in clang
---
  src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp 
b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
index 10a4ff4..69da83a 100644
--- a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
+++ b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
@@ -254,7 +254,8 @@ brw_nir_lower_patch_vertices_in_to_uniform(nir_shader *nir)
gl_state_index16 tokens[STATE_LENGTH] = {
   STATE_INTERNAL,
   nir->info.stage == MESA_SHADER_TESS_CTRL ?
-STATE_TCS_PATCH_VERTICES_IN : STATE_TES_PATCH_VERTICES_IN,
+(gl_state_index16)STATE_TCS_PATCH_VERTICES_IN :
+(gl_state_index16)STATE_TES_PATCH_VERTICES_IN,
};
var->num_state_slots = 1;
var->state_slots =


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Re: [Mesa-dev] [PATCH 1/2] nir: retain pixel_center_integer information when lowering gl_FragCoord

[Jason Ekstrand]

First off, you should add an index to the intrinsic if you're going to do
this and it should probably be set elsewhere.  Otherwise, it becomes this
magic secret radeonsi thing.

Second, do you really want this on the intrinsic or would it be better as
part of shader_info?  It's always been weird to me that it's a layout
qualifier on gl_FragCoord.  In SPIR-V, it comes in as an execution mode
which is a very global thing.

On Tue, Feb 13, 2018 at 9:02 PM, Timothy Arceri 
wrote:

> radeonsi needs to gather this information.
> ---
>  src/compiler/nir/nir_lower_system_values.c | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/src/compiler/nir/nir_lower_system_values.c
> b/src/compiler/nir/nir_lower_system_values.c
> index 3594f4ae5c..f8d8463f7f 100644
> --- a/src/compiler/nir/nir_lower_system_values.c
> +++ b/src/compiler/nir/nir_lower_system_values.c
> @@ -133,6 +133,15 @@ convert_block(nir_block *block, nir_builder *b)
>   break;
>}
>
> +  case SYSTEM_VALUE_FRAG_COORD: {
> + nir_intrinsic_op sysval_op =
> +nir_intrinsic_from_system_value(var->data.location);
> + int idx = 0;
> + if (var->data.pixel_center_integer) {
> +idx = 1;
> + }
> + sysval = nir_load_system_value(b, sysval_op, idx);
> +  }
>default:
>   break;
>}
> --
> 2.14.3
>
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[Mesa-dev] [Bug 104915] Indexed SHADING_LANGUAGE_VERSION query not supported

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104915

Tapani Pälli  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #1 from Tapani Pälli  ---
Fixed in Mesa master. Thanks for top quality bug report!

--- 8< ---
commit a553c54abf92533daf442073dd3408c35f57d8ba
Author: Vadym Shovkoplias 
Date:   Tue Feb 13 11:38:22 2018 -0700

mesa: add glsl version query (v4)

Add support for GL_NUM_SHADING_LANGUAGE_VERSIONS
and glGetStringi for GL_SHADING_LANGUAGE_VERSION

v2:
  - Combine similar functionality into
_mesa_get_shading_language_version() function.
  - Change GLSL version return mechanism.
v3:
  - Add return of empty string for GLSL ver 1.10.
  - Move _mesa_get_shading_language_version() function
to src/mesa/main/version.c.
v4:
  - Add OpenGL version check.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104915
Signed-off-by: Andriy Khulap 
Signed-off-by: Vadym Shovkoplias 
Reviewed-by: Brian Paul 

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[Mesa-dev] [PATCH 2/2] radeonsi/nir: fix gl_FragCoord for pixel_center_integer

[Timothy Arceri]

---
 src/gallium/drivers/radeonsi/si_shader_nir.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index b46c7dca86..cb4f8e9255 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -77,6 +77,12 @@ static void scan_instruction(struct tgsi_shader_info *info,
nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
 
switch (intr->intrinsic) {
+   case nir_intrinsic_load_frag_coord:
+   if (intr->const_index[0] == 1) {
+   
info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
+   TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
+   }
+   break;
case nir_intrinsic_load_front_face:
info->uses_frontface = 1;
break;
-- 
2.14.3

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[Mesa-dev] [PATCH 1/2] nir: retain pixel_center_integer information when lowering gl_FragCoord

[Timothy Arceri]

radeonsi needs to gather this information.
---
 src/compiler/nir/nir_lower_system_values.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/compiler/nir/nir_lower_system_values.c 
b/src/compiler/nir/nir_lower_system_values.c
index 3594f4ae5c..f8d8463f7f 100644
--- a/src/compiler/nir/nir_lower_system_values.c
+++ b/src/compiler/nir/nir_lower_system_values.c
@@ -133,6 +133,15 @@ convert_block(nir_block *block, nir_builder *b)
  break;
   }
 
+  case SYSTEM_VALUE_FRAG_COORD: {
+ nir_intrinsic_op sysval_op =
+nir_intrinsic_from_system_value(var->data.location);
+ int idx = 0;
+ if (var->data.pixel_center_integer) {
+idx = 1;
+ }
+ sysval = nir_load_system_value(b, sysval_op, idx);
+  }
   default:
  break;
   }
-- 
2.14.3

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[Mesa-dev] [PATCH] virgl: remap query types to hw support.

[Dave Airlie]

From: Dave Airlie 

The gallium query types changed, so we need to remap from the
gallium ones to the virgl ones.

Fixes:
dEQP-GLES3.functional.transform_feedback.basic_types*

Fixes: 3f6b3d9db (gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE)

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/virgl/virgl_query.c | 37 +++--
 1 file changed, 35 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_query.c 
b/src/gallium/drivers/virgl/virgl_query.c
index e6ca4609c03..3a930d29666 100644
--- a/src/gallium/drivers/virgl/virgl_query.c
+++ b/src/gallium/drivers/virgl/virgl_query.c
@@ -37,6 +37,39 @@ struct virgl_query {
unsigned result_size;
unsigned result_gotten_sent;
 };
+#define VIRGL_QUERY_OCCLUSION_COUNTER 0
+#define VIRGL_QUERY_OCCLUSION_PREDICATE   1
+#define VIRGL_QUERY_TIMESTAMP 2
+#define VIRGL_QUERY_TIMESTAMP_DISJOINT3
+#define VIRGL_QUERY_TIME_ELAPSED  4
+#define VIRGL_QUERY_PRIMITIVES_GENERATED  5
+#define VIRGL_QUERY_PRIMITIVES_EMITTED6
+#define VIRGL_QUERY_SO_STATISTICS 7
+#define VIRGL_QUERY_SO_OVERFLOW_PREDICATE 8
+#define VIRGL_QUERY_GPU_FINISHED  9
+#define VIRGL_QUERY_PIPELINE_STATISTICS  10
+
+static const int pquery_map[] =
+{
+   VIRGL_QUERY_OCCLUSION_COUNTER,
+   VIRGL_QUERY_OCCLUSION_PREDICATE,
+   -1,
+   VIRGL_QUERY_TIMESTAMP,
+   VIRGL_QUERY_TIMESTAMP_DISJOINT,
+   VIRGL_QUERY_TIME_ELAPSED,
+   VIRGL_QUERY_PRIMITIVES_GENERATED,
+   VIRGL_QUERY_PRIMITIVES_EMITTED,
+   VIRGL_QUERY_SO_STATISTICS,
+   VIRGL_QUERY_SO_OVERFLOW_PREDICATE,
+   -1,
+   VIRGL_QUERY_GPU_FINISHED,
+   VIRGL_QUERY_PIPELINE_STATISTICS,
+};
+
+static int pipe_to_virgl_query(enum pipe_query_type ptype)
+{
+   return pquery_map[ptype];
+}
 
 static inline struct virgl_query *virgl_query(struct pipe_query *q)
 {
@@ -75,11 +108,11 @@ static struct pipe_query *virgl_create_query(struct 
pipe_context *ctx,
}
 
handle = virgl_object_assign_handle();
-   query->type = query_type;
+   query->type = pipe_to_virgl_query(query_type);
query->index = index;
query->handle = handle;
query->buf->clean = FALSE;
-   virgl_encoder_create_query(vctx, handle, query_type, index, query->buf, 0);
+   virgl_encoder_create_query(vctx, handle, query->type, index, query->buf, 0);
 
return (struct pipe_query *)query;
 }
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 13/14] anv/cmd_buffer: Do subpass image transitions in begin/end_subpass

[Jason Ekstrand]

On Tue, Feb 13, 2018 at 5:34 PM, Nanley Chery  wrote:

> On Mon, Feb 05, 2018 at 02:35:02PM -0800, Jason Ekstrand wrote:
> > ---
> >  src/intel/vulkan/genX_cmd_buffer.c | 190 +-
> ---
> >  1 file changed, 68 insertions(+), 122 deletions(-)
> >
> > diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer.c
> > index 2d17c28..2732ef3 100644
> > --- a/src/intel/vulkan/genX_cmd_buffer.c
> > +++ b/src/intel/vulkan/genX_cmd_buffer.c
> > @@ -3257,120 +3257,6 @@ cmd_buffer_emit_depth_stencil(struct
> anv_cmd_buffer *cmd_buffer)
> > cmd_buffer->state.hiz_enabled = info.hiz_usage == ISL_AUX_USAGE_HIZ;
> >  }
> >
> > -
> > -/**
> > - * @brief Perform any layout transitions required at the beginning
> and/or end
> > - *of the current subpass for depth buffers.
> > - *
> > - * TODO: Consider preprocessing the attachment reference array at
> render pass
> > - *   create time to determine if no layout transition is needed at
> the
> > - *   beginning and/or end of each subpass.
> > - *
> > - * @param cmd_buffer The command buffer the transition is happening
> within.
> > - * @param subpass_end If true, marks that the transition is happening
> at the
> > - *end of the subpass.
> > - */
> > -static void
> > -cmd_buffer_subpass_transition_layouts(struct anv_cmd_buffer * const
> cmd_buffer,
> > -  const bool subpass_end)
> > -{
> > -   /* We need a non-NULL command buffer. */
> > -   assert(cmd_buffer);
> > -
> > -   const struct anv_cmd_state * const cmd_state = _buffer->state;
> > -   const struct anv_subpass * const subpass = cmd_state->subpass;
> > -
> > -   /* This function must be called within a subpass. */
> > -   assert(subpass);
> > -
> > -   /* If there are attachment references, the array shouldn't be NULL.
> > -*/
> > -   if (subpass->attachment_count > 0)
> > -  assert(subpass->attachments);
> > -
> > -   /* Iterate over the array of attachment references. */
> > -   for (const struct anv_subpass_attachment *att_ref =
> subpass->attachments;
> > -att_ref < subpass->attachments + subpass->attachment_count;
> att_ref++) {
> > -
> > -  /* If the attachment is unused, we can't perform a layout
> transition. */
> > -  if (att_ref->attachment == VK_ATTACHMENT_UNUSED)
> > - continue;
> > -
> > -  /* This attachment index shouldn't go out of bounds. */
> > -  assert(att_ref->attachment < cmd_state->pass->attachment_count);
> > -
> > -  const struct anv_render_pass_attachment * const att_desc =
> > - _state->pass->attachments[att_ref->attachment];
> > -  struct anv_attachment_state * const att_state =
> > - _buffer->state.attachments[att_ref->attachment];
> > -
> > -  /* The attachment should not be used in a subpass after its last.
> */
> > -  assert(att_desc->last_subpass_idx >=
> anv_get_subpass_id(cmd_state));
> > -
> > -  if (subpass_end && anv_get_subpass_id(cmd_state) <
> > -  att_desc->last_subpass_idx) {
> > - /* We're calling this function on a buffer twice in one
> subpass and
> > -  * this is not the last use of the buffer. The layout should
> not have
> > -  * changed from the first call and no transition is necessary.
> > -  */
> > - assert(att_state->current_layout == att_ref->layout ||
> > -att_state->current_layout ==
> > -VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL);
> > - continue;
> > -  }
> > -
> > -  /* The attachment index must be less than the number of
> attachments
> > -   * within the framebuffer.
> > -   */
> > -  assert(att_ref->attachment < cmd_state->framebuffer->
> attachment_count);
> > -
> > -  const struct anv_image_view * const iview =
> > - cmd_state->framebuffer->attachments[att_ref->attachment];
> > -  const struct anv_image * const image = iview->image;
> > -
> > -  /* Get the appropriate target layout for this attachment. */
> > -  VkImageLayout target_layout;
> > -
> > -  /* A resolve is necessary before use as an input attachment if
> the clear
> > -   * color or auxiliary buffer usage isn't supported by the sampler.
> > -   */
> > -  const bool input_needs_resolve =
> > -(att_state->fast_clear && !att_state->clear_color_is_zero_one)
> ||
> > -att_state->input_aux_usage != att_state->aux_usage;
> > -  if (subpass_end) {
> > - target_layout = att_desc->final_layout;
> > -  } else if (iview->aspect_mask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
> &&
> > - !input_needs_resolve) {
> > - /* Layout transitions before the final only help to enable
> sampling as
> > -  * an input attachment. If the input attachment supports
> sampling
> > -  * using the auxiliary surface, we can skip such transitions
> by making
> > -  * the target 

Re: [Mesa-dev] [PATCH 07/14] anv/cmd_buffer: Decide whether or not to HiZ clear up-front

[Jason Ekstrand]

You're going to want to re-review this one when I send the v2.  It changed
quite a bit.

On Tue, Feb 13, 2018 at 2:44 PM, Jason Ekstrand 
wrote:

> On Tue, Feb 13, 2018 at 11:02 AM, Nanley Chery 
> wrote:
>
>> On Mon, Feb 05, 2018 at 02:34:56PM -0800, Jason Ekstrand wrote:
>> > This moves the decision out of begin_subpass and into BeginRenderPass
>> > like the decision for color clears.  We use a similar name for the
>> > function for depth/stencil as for color even though no aux usage is
>> > really getting computed.
>> > ---
>> >  src/intel/vulkan/genX_cmd_buffer.c | 84 +++---
>> 
>> >  1 file changed, 50 insertions(+), 34 deletions(-)
>> >
>> > diff --git a/src/intel/vulkan/genX_cmd_buffer.c
>> b/src/intel/vulkan/genX_cmd_buffer.c
>> > index 21fdc6b..ab79fbf 100644
>> > --- a/src/intel/vulkan/genX_cmd_buffer.c
>> > +++ b/src/intel/vulkan/genX_cmd_buffer.c
>> > @@ -350,6 +350,52 @@ color_attachment_compute_aux_usage(struct
>> anv_device * device,
>> > }
>> >  }
>> >
>> > +static void
>> > +depth_stencil_attachment_compute_aux_usage(struct anv_device *device,
>> > +   struct anv_cmd_state
>> *cmd_state,
>> > +   uint32_t att, VkRect2D
>> render_area)
>> > +{
>> > +   struct anv_attachment_state *att_state =
>> _state->attachments[att];
>> > +   struct anv_image_view *iview = cmd_state->framebuffer->attach
>> ments[att];
>> > +
>> > +   /* These will be initialized after the first subpass transition. */
>> > +   att_state->aux_usage = ISL_AUX_USAGE_NONE;
>> > +   att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
>> > +
>> > +   if (att_state->aux_usage != ISL_AUX_USAGE_HIZ) {
>>
>> We set this to NONE 3 lines above. I think you meant to have your
>> variable be: iview->image->planes[plane].aux_usage ?
>>
>
> Yup.  You're right.  Fixed locally.
>
> This means I accidentally disabled HiZ clears entirely. :(  This is going
> to need another jenkins run.
>
>
>> This is a nice cleanup. With the above fixed, this patch is
>> Reviewed-by: Nanley Chery 
>>
>>
>> > +  att_state->fast_clear = false;
>> > +  return;
>> > +   } else if (!(att_state->pending_clear_aspects &
>> VK_IMAGE_ASPECT_DEPTH_BIT)) {
>> > +  /* If we're just clearing stencil, we can always HiZ clear */
>> > +  att_state->fast_clear = true;
>> > +  return;
>> > +   }
>> > +
>> > +   if (!blorp_can_hiz_clear_depth(GEN_GEN,
>> > +  iview->planes[0].isl.format,
>> > +  iview->image->samples,
>> > +  render_area.offset.x,
>> > +  render_area.offset.y,
>> > +  render_area.offset.x +
>> > +  render_area.extent.width,
>> > +  render_area.offset.y +
>> > +  render_area.extent.height)) {
>> > +  att_state->fast_clear = false;
>> > +   } else if (att_state->clear_value.depthStencil.depth !=
>> ANV_HZ_FC_VAL) {
>> > +  att_state->fast_clear = false;
>> > +   } else if (GEN_GEN == 8 &&
>> > +  anv_can_sample_with_hiz(>info, iview->image)) {
>> > +  /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
>> > +   * fast-cleared portion of a HiZ buffer. Testing has revealed
>> that Gen8
>> > +   * only supports returning 0.0f. Gens prior to gen8 do not
>> support this
>> > +   * feature at all.
>> > +   */
>> > +  att_state->fast_clear = false;
>> > +   } else {
>> > +  att_state->fast_clear = true;
>> > +   }
>> > +}
>> > +
>> >  static bool
>> >  need_input_attachment_state(const struct anv_render_pass_attachment
>> *att)
>> >  {
>> > @@ -1125,12 +1171,9 @@ genX(cmd_buffer_setup_attachments)(struct
>> anv_cmd_buffer *cmd_buffer,
>> >  add_image_view_relocs(cmd_buffer, iview, 0,
>> >state->attachments[i].color);
>> >   } else {
>> > -/* This field will be initialized after the first subpass
>> > - * transition.
>> > - */
>> > -state->attachments[i].aux_usage = ISL_AUX_USAGE_NONE;
>> > -
>> > -state->attachments[i].input_aux_usage =
>> ISL_AUX_USAGE_NONE;
>> > +depth_stencil_attachment_compu
>> te_aux_usage(cmd_buffer->device,
>> > +   state, i,
>> > +
>>  begin->renderArea);
>> >   }
>> >
>> >   if (need_input_attachment_state(>attachments[i])) {
>> > @@ -3541,34 +3584,7 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer
>> *cmd_buffer,
>> > VK_IMAGE_ASPECT_STENCIL_BIT));
>> >
>> >if (att_state->pending_clear_aspects) {
>> > - bool clear_with_hiz = att_state->aux_usage ==
>> ISL_AUX_USAGE_HIZ;
>> > - if 

Re: [Mesa-dev] [PATCH 05/16] intel/isl/icl: Build and use gen11 surface state emit functions

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:05 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat 
> ---
>  src/intel/Android.isl.mk   | 20 
>  src/intel/Makefile.isl.am  |  4 
>  src/intel/Makefile.sources |  4 
>  src/intel/isl/isl.c|  3 +++
>  src/intel/isl/isl_priv.h   |  3 +++
>  src/intel/isl/meson.build  |  2 +-
>  6 files changed, 35 insertions(+), 1 deletion(-)

I barely skimmed this, trusting that Dylan had looked in more detail,
but since I reviewed the rest of the series, you may as well have a

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 03/16] intel/genxml/icl: Update genx_bits header

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:03 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat 
> ---
>  src/intel/genxml/gen_bits_header.py | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/intel/genxml/gen_bits_header.py 
> b/src/intel/genxml/gen_bits_header.py
> index 1b3504073b..965a74ed89 100644
> --- a/src/intel/genxml/gen_bits_header.py
> +++ b/src/intel/genxml/gen_bits_header.py
> @@ -80,6 +80,7 @@ static inline uint32_t ATTRIBUTE_PURE
>  ${item.token_name}_${prop}(const struct gen_device_info *devinfo)
>  {
> switch (devinfo->gen) {
> +   case 11: return ${item.get_prop(prop, 11)};
> case 10: return ${item.get_prop(prop, 10)};
> case 9: return ${item.get_prop(prop, 9)};
> case 8: return ${item.get_prop(prop, 8)};
> 

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 08/16] i965/icl: Build and use gen11 functions for genxml state-upload and blorp

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:08 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat 

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 07/16] i965/icl: Don't set ResetGatewayTimer

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:07 AM PST Anuj Phogat wrote:
> This field is removed in gen11+
> 
> Signed-off-by: Anuj Phogat 
> ---
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
> b/src/mesa/drivers/dri/i965/genX_state_upload.c
> index 67fb328dbc..29739ba051 100644
> --- a/src/mesa/drivers/dri/i965/genX_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
> @@ -4215,8 +4215,10 @@ genX(upload_cs_state)(struct brw_context *brw)
>const uint32_t subslices = MAX2(brw->screen->subslice_total, 1);
>vfe.MaximumNumberofThreads = devinfo->max_cs_threads * subslices - 1;
>vfe.NumberofURBEntries = GEN_GEN >= 8 ? 2 : 0;
> +#if GEN_GEN < 11
>vfe.ResetGatewayTimer =
>   Resettingrelativetimerandlatchingtheglobaltimestamp;
> +#endif
>  #if GEN_GEN < 9
>vfe.BypassGatewayControl = BypassingOpenGatewayCloseGatewayprotocol;
>  #endif
> 

So it is.  I wonder why we set this on older platforms.  I'm guessing
we don't need to, and could have just used the "keep the timestamp"
value...deleting this code entirely.  But, I'm not sure either.

For now, this seems like a good plan.

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 10/16] i965/icl: Define and use icl mocs settings

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:10 AM PST Anuj Phogat wrote:
> Gen11 MOCS settings are duplicate of Gen10 MOCS settings.
> 
> Signed-off-by: Anuj Phogat 
> ---
>  src/mesa/drivers/dri/i965/brw_state.h| 6 ++
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 ++
>  src/mesa/drivers/dri/i965/genX_state_upload.c| 4 +++-
>  3 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
> b/src/mesa/drivers/dri/i965/brw_state.h
> index 709896be3e..3602e3dd6e 100644
> --- a/src/mesa/drivers/dri/i965/brw_state.h
> +++ b/src/mesa/drivers/dri/i965/brw_state.h
> @@ -386,6 +386,12 @@ void gen11_init_atoms(struct brw_context *brw);
>  /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
>  #define CNL_MOCS_PTE (1 << 1)
>  
> +/* Ice Lake uses same MOCS settings as Cannonlake */
> +/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
> +#define ICL_MOCS_WB  (2 << 1)
> +/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
> +#define ICL_MOCS_PTE (1 << 1)
> +

This is all a bit silly now that MOCS is just an index into a table
set by the kernel...we were already relying on the fact that SKL_MOCS_*
== CNL_MOCS_* in some places...

But, we can clean it up later...so...

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 11/16] i965/icl: Update the assert in brw_memory_barrier()

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:11 AM PST Anuj Phogat wrote:
> Nothing is changed here from gen10 to gen11. So, just update
> the assert.
> 
> Signed-off-by: Anuj Phogat 
> ---
>  src/mesa/drivers/dri/i965/brw_program.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
> b/src/mesa/drivers/dri/i965/brw_program.c
> index 7fae22c620..381cc2887d 100644
> --- a/src/mesa/drivers/dri/i965/brw_program.c
> +++ b/src/mesa/drivers/dri/i965/brw_program.c
> @@ -280,7 +280,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield 
> barriers)
> unsigned bits = (PIPE_CONTROL_DATA_CACHE_FLUSH |
>  PIPE_CONTROL_NO_WRITE |
>  PIPE_CONTROL_CS_STALL);
> -   assert(devinfo->gen >= 7 && devinfo->gen <= 10);
> +   assert(devinfo->gen >= 7 && devinfo->gen <= 11);
>  
> if (barriers & (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT |
> GL_ELEMENT_ARRAY_BARRIER_BIT |
> 

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Re: [Mesa-dev] [PATCH 02/16] intel/genxml/icl: Generate packing headers

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:02 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat 
> ---
>  src/intel/Android.genxml.mk   | 5 +
>  src/intel/Makefile.sources| 3 ++-
>  src/intel/genxml/genX_pack.h  | 2 ++
>  src/intel/genxml/gen_macros.h | 3 +++
>  4 files changed, 12 insertions(+), 1 deletion(-)

No Meson changes in this patch.  It looks like the addition in the
previous patch may have been sufficient.  It's kind of weird to have
the build systems in different patches.  I might squash this, but it's
up to you.

Either way,
Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 13/14] anv/cmd_buffer: Do subpass image transitions in begin/end_subpass

[Nanley Chery]

On Mon, Feb 05, 2018 at 02:35:02PM -0800, Jason Ekstrand wrote:
> ---
>  src/intel/vulkan/genX_cmd_buffer.c | 190 
> +
>  1 file changed, 68 insertions(+), 122 deletions(-)
> 
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
> b/src/intel/vulkan/genX_cmd_buffer.c
> index 2d17c28..2732ef3 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -3257,120 +3257,6 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer 
> *cmd_buffer)
> cmd_buffer->state.hiz_enabled = info.hiz_usage == ISL_AUX_USAGE_HIZ;
>  }
>  
> -
> -/**
> - * @brief Perform any layout transitions required at the beginning and/or end
> - *of the current subpass for depth buffers.
> - *
> - * TODO: Consider preprocessing the attachment reference array at render pass
> - *   create time to determine if no layout transition is needed at the
> - *   beginning and/or end of each subpass.
> - *
> - * @param cmd_buffer The command buffer the transition is happening within.
> - * @param subpass_end If true, marks that the transition is happening at the
> - *end of the subpass.
> - */
> -static void
> -cmd_buffer_subpass_transition_layouts(struct anv_cmd_buffer * const 
> cmd_buffer,
> -  const bool subpass_end)
> -{
> -   /* We need a non-NULL command buffer. */
> -   assert(cmd_buffer);
> -
> -   const struct anv_cmd_state * const cmd_state = _buffer->state;
> -   const struct anv_subpass * const subpass = cmd_state->subpass;
> -
> -   /* This function must be called within a subpass. */
> -   assert(subpass);
> -
> -   /* If there are attachment references, the array shouldn't be NULL.
> -*/
> -   if (subpass->attachment_count > 0)
> -  assert(subpass->attachments);
> -
> -   /* Iterate over the array of attachment references. */
> -   for (const struct anv_subpass_attachment *att_ref = subpass->attachments;
> -att_ref < subpass->attachments + subpass->attachment_count; 
> att_ref++) {
> -
> -  /* If the attachment is unused, we can't perform a layout transition. 
> */
> -  if (att_ref->attachment == VK_ATTACHMENT_UNUSED)
> - continue;
> -
> -  /* This attachment index shouldn't go out of bounds. */
> -  assert(att_ref->attachment < cmd_state->pass->attachment_count);
> -
> -  const struct anv_render_pass_attachment * const att_desc =
> - _state->pass->attachments[att_ref->attachment];
> -  struct anv_attachment_state * const att_state =
> - _buffer->state.attachments[att_ref->attachment];
> -
> -  /* The attachment should not be used in a subpass after its last. */
> -  assert(att_desc->last_subpass_idx >= anv_get_subpass_id(cmd_state));
> -
> -  if (subpass_end && anv_get_subpass_id(cmd_state) <
> -  att_desc->last_subpass_idx) {
> - /* We're calling this function on a buffer twice in one subpass and
> -  * this is not the last use of the buffer. The layout should not 
> have
> -  * changed from the first call and no transition is necessary.
> -  */
> - assert(att_state->current_layout == att_ref->layout ||
> -att_state->current_layout ==
> -VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL);
> - continue;
> -  }
> -
> -  /* The attachment index must be less than the number of attachments
> -   * within the framebuffer.
> -   */
> -  assert(att_ref->attachment < cmd_state->framebuffer->attachment_count);
> -
> -  const struct anv_image_view * const iview =
> - cmd_state->framebuffer->attachments[att_ref->attachment];
> -  const struct anv_image * const image = iview->image;
> -
> -  /* Get the appropriate target layout for this attachment. */
> -  VkImageLayout target_layout;
> -
> -  /* A resolve is necessary before use as an input attachment if the 
> clear
> -   * color or auxiliary buffer usage isn't supported by the sampler.
> -   */
> -  const bool input_needs_resolve =
> -(att_state->fast_clear && !att_state->clear_color_is_zero_one) ||
> -att_state->input_aux_usage != att_state->aux_usage;
> -  if (subpass_end) {
> - target_layout = att_desc->final_layout;
> -  } else if (iview->aspect_mask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV &&
> - !input_needs_resolve) {
> - /* Layout transitions before the final only help to enable sampling 
> as
> -  * an input attachment. If the input attachment supports sampling
> -  * using the auxiliary surface, we can skip such transitions by 
> making
> -  * the target layout one that is CCS-aware.
> -  */
> - target_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
> -  } else {
> - target_layout = att_ref->layout;
> -  }
> -
> -  /* Perform the layout transition. */
> -  if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) 

[Mesa-dev] [PATCH] radeonsi/nir: fix si_nir_load_tcs_varyings() for outputs

[Timothy Arceri]

We were incorrectly using the input info for outputs.
---
 src/gallium/drivers/radeonsi/si_shader.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 825cb9dd0e..ec03f537d0 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1254,11 +1254,20 @@ static LLVMValueRef si_nir_load_tcs_varyings(struct 
ac_shader_abi *abi,
param_index = LLVMConstInt(ctx->i32, const_index, 0);
}
 
+   ubyte *names;
+   ubyte *indices;
+   if (load_input) {
+   names = info->input_semantic_name;
+   indices = info->input_semantic_index;
+   } else {
+   names = info->output_semantic_name;
+   indices = info->output_semantic_index;
+   }
+
dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
  vertex_index, param_index,
  driver_location,
- info->input_semantic_name,
- 
info->input_semantic_index,
+ names, indices,
  is_patch);
 
LLVMValueRef value[4];
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 12/14] anv/cmd_buffer: Mark depth/stencil surfaces written in begin_subpass

[Jason Ekstrand]

On Tue, Feb 13, 2018 at 4:47 PM, Nanley Chery  wrote:

> On Mon, Feb 05, 2018 at 02:35:01PM -0800, Jason Ekstrand wrote:
> > ---
> >  src/intel/vulkan/genX_cmd_buffer.c | 50 ++
> 
> >  1 file changed, 29 insertions(+), 21 deletions(-)
> >
> > diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer.c
> > index 4eee85a..2d17c28 100644
> > --- a/src/intel/vulkan/genX_cmd_buffer.c
> > +++ b/src/intel/vulkan/genX_cmd_buffer.c
> > @@ -3255,27 +3255,6 @@ cmd_buffer_emit_depth_stencil(struct
> anv_cmd_buffer *cmd_buffer)
> > isl_emit_depth_stencil_hiz_s(>isl_dev, dw, );
> >
> > cmd_buffer->state.hiz_enabled = info.hiz_usage == ISL_AUX_USAGE_HIZ;
> > -
> > -   /* We may be writing depth or stencil so we need to mark the surface.
> > -* Unfortunately, there's no way to know at this point whether the
> depth or
> > -* stencil tests used will actually write to the surface.
> > -*/
> > -   if (image && (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
> > -  genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
> > -  VK_IMAGE_ASPECT_DEPTH_BIT,
> > -  info.hiz_usage,
> > -  info.view->base_level,
> > -  info.view->base_array_layer,
> > -  info.view->array_len);
> > -   }
> > -   if (image && (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT)) {
> > -  genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
> > -  VK_IMAGE_ASPECT_STENCIL_BIT,
> > -  ISL_AUX_USAGE_NONE,
> > -  info.view->base_level,
> > -  info.view->base_array_layer,
> > -  info.view->array_len);
> > -   }
> >  }
> >
> >
> > @@ -3550,6 +3529,35 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer
> *cmd_buffer,
> >   iview->planes[0].isl.base_
> level,
> >   iview->planes[0].isl.base_
> array_layer,
> >   fb->layers);
> > +  } else if (subpass->attachments[i].usage ==
> > + VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT) {
> > + /* We may be writing depth or stencil so we need to mark the
> surface.
> > +  * Unfortunately, there's no way to know at this point whether
> the
> > +  * depth or stencil tests used will actually write to the
> surface.
> > +  *
> > +  * Even though stencil may be plane 1, it always shares a
> base_level
> > +  * with depth.
> > +  */
> > + const struct isl_view *ds_view = >planes[0].isl;
> > + if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
>
> I think this should be iview->aspect_mask.
>

Done.


> > +genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
> > +
> VK_IMAGE_ASPECT_DEPTH_BIT,
> > +att_state->aux_usage,
> > +ds_view->base_level,
> > +
> ds_view->base_array_layer,
> > +fb->layers);
> > + }
> > + if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
>
> Same comment as above.
>

Done.


> With those two issues fixed, this patch is
> Reviewed-by: Nanley Chery 
>

Thanks!


>
> > +/* Even though stencil may be plane 1, it always shares a
> > + * base_level with depth.
> > + */
> > +genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
> > +
> VK_IMAGE_ASPECT_STENCIL_BIT,
> > +ISL_AUX_USAGE_NONE,
> > +ds_view->base_level,
> > +
> ds_view->base_array_layer,
> > +fb->layers);
> > + }
> >}
> >
> >att_state->pending_clear_aspects = 0;
> > --
> > 2.5.0.400.gff86faf
> >
> > ___
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> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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Re: [Mesa-dev] [PATCH 11/14] anv/cmd_buffer: Sync clear values in begin_subpass

[Jason Ekstrand]

On Tue, Feb 13, 2018 at 4:35 PM, Nanley Chery  wrote:

> On Mon, Feb 05, 2018 at 02:35:00PM -0800, Jason Ekstrand wrote:
> > This is quite a bit cleaner because we now sync the clear values at the
> > same time as we do the fast clear.  For loading the clear values into
> > the surface state, we now do it once when we handle the LOAD_OP_LOAD
> > instead of every subpass.
> > ---
> >  src/intel/vulkan/genX_cmd_buffer.c | 148 --
> ---
> >  1 file changed, 48 insertions(+), 100 deletions(-)
> >
> > diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer.c
> > index f92e86f..4eee85a 100644
> > --- a/src/intel/vulkan/genX_cmd_buffer.c
> > +++ b/src/intel/vulkan/genX_cmd_buffer.c
> > @@ -3392,97 +3392,6 @@ cmd_buffer_subpass_transition_layouts(struct
> anv_cmd_buffer * const cmd_buffer,
> > }
> >  }
> >
> > -/* Update the clear value dword(s) in surface state objects or the fast
> clear
> > - * state buffer entry for the color attachments used in this subpass.
> > - */
> > -static void
> > -cmd_buffer_subpass_sync_fast_clear_values(struct anv_cmd_buffer
> *cmd_buffer)
> > -{
> > -   assert(cmd_buffer && cmd_buffer->state.subpass);
> > -
> > -   const struct anv_cmd_state *state = _buffer->state;
> > -
> > -   /* Iterate through every color attachment used in this subpass. */
> > -   for (uint32_t i = 0; i < state->subpass->color_count; ++i) {
> > -
> > -  /* The attachment should be one of the attachments described in
> the
> > -   * render pass and used in the subpass.
> > -   */
> > -  const uint32_t a = state->subpass->color_
> attachments[i].attachment;
> > -  if (a == VK_ATTACHMENT_UNUSED)
> > - continue;
> > -
> > -  assert(a < state->pass->attachment_count);
> > -
> > -  /* Store some information regarding this attachment. */
> > -  const struct anv_attachment_state *att_state =
> >attachments[a];
> > -  const struct anv_image_view *iview = state->framebuffer->
> attachments[a];
> > -  const struct anv_render_pass_attachment *rp_att =
> > - >pass->attachments[a];
> > -
> > -  if (att_state->aux_usage == ISL_AUX_USAGE_NONE)
> > - continue;
> > -
> > -  /* The fast clear state entry must be updated if a fast clear is
> going to
> > -   * happen. The surface state must be updated if the clear value
> from a
> > -   * prior fast clear may be needed.
> > -   */
> > -  if (att_state->pending_clear_aspects && att_state->fast_clear) {
> > - /* Update the fast clear state entry. */
> > - genX(copy_fast_clear_dwords)(cmd_buffer,
> att_state->color.state,
> > -  iview->image,
> > -  VK_IMAGE_ASPECT_COLOR_BIT,
> > -  true /* copy from ss */);
> > -
> > - /* Fast-clears impact whether or not a resolve will be
> necessary. */
> > - if (att_state->clear_color_is_zero) {
> > -/* This image always has the auxiliary buffer enabled. We
> can mark
> > - * the subresource as not needing a resolve because the
> clear color
> > - * will match what's in every RENDER_SURFACE_STATE object
> when it's
> > - * being used for sampling.
> > - */
> > -set_image_fast_clear_state(cmd_buffer, iview->image,
> > -   VK_IMAGE_ASPECT_COLOR_BIT,
> > -   ANV_FAST_CLEAR_DEFAULT_VALUE);
> > - } else {
> > -set_image_fast_clear_state(cmd_buffer, iview->image,
> > -   VK_IMAGE_ASPECT_COLOR_BIT,
> > -   ANV_FAST_CLEAR_ANY);
> > - }
> > -  } else if (rp_att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD &&
> > - iview->planes[0].isl.base_level == 0 &&
> > - iview->planes[0].isl.base_array_layer == 0) {
> > - /* The attachment may have been fast-cleared in a previous
> render
> > -  * pass and the value is needed now. Update the surface
> state(s).
> > -  *
> > -  * TODO: Do this only once per render pass instead of every
> subpass.
> > -  */
> > - genX(copy_fast_clear_dwords)(cmd_buffer,
> att_state->color.state,
> > -  iview->image,
> > -  VK_IMAGE_ASPECT_COLOR_BIT,
> > -  false /* copy to ss */);
> > -
> > - if (need_input_attachment_state(rp_att) &&
> > - att_state->input_aux_usage != ISL_AUX_USAGE_NONE) {
> > -genX(copy_fast_clear_dwords)(cmd_buffer,
> att_state->input.state,
> > - iview->image,
> > - VK_IMAGE_ASPECT_COLOR_BIT,
> > - false /* copy to ss */);
> > -

[Mesa-dev] [AppVeyor] mesa master #6908 completed

[AppVeyor]

Build mesa 6908 completed



Commit f6718baabc by Roland Scheidegger on 2/13/2018 5:56 PM:

tgsi: Recognize RET in main for tgsi_transform\n\nShaders coming from dx10 state trackers have a RET before the END.\nAnd the epilog needs to be placed before the RET (otherwise it will\nget ignored).\nHence figure out if a RET is in main, in this case we'll place\nthe epilog there rather than before the END.\n(At a closer look, there actually seem to be problems with control\nflow in general with output redirection, that would need another\nlook. It's enough however to fix draw's aa line emulation in some\ninternal bug - lines tend to be drawn with trivial shaders, moving\neither a constant color or a vertex color directly to the output).\n\nv2: add assert so buggy handling of RET in main is detected\n\nReviewed-by: Brian Paul \nReviewed-by: Jose Fonseca 


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Re: [Mesa-dev] [PATCH 12/14] anv/cmd_buffer: Mark depth/stencil surfaces written in begin_subpass

[Nanley Chery]

On Mon, Feb 05, 2018 at 02:35:01PM -0800, Jason Ekstrand wrote:
> ---
>  src/intel/vulkan/genX_cmd_buffer.c | 50 
> ++
>  1 file changed, 29 insertions(+), 21 deletions(-)
> 
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
> b/src/intel/vulkan/genX_cmd_buffer.c
> index 4eee85a..2d17c28 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -3255,27 +3255,6 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer 
> *cmd_buffer)
> isl_emit_depth_stencil_hiz_s(>isl_dev, dw, );
>  
> cmd_buffer->state.hiz_enabled = info.hiz_usage == ISL_AUX_USAGE_HIZ;
> -
> -   /* We may be writing depth or stencil so we need to mark the surface.
> -* Unfortunately, there's no way to know at this point whether the depth 
> or
> -* stencil tests used will actually write to the surface.
> -*/
> -   if (image && (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
> -  genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
> -  VK_IMAGE_ASPECT_DEPTH_BIT,
> -  info.hiz_usage,
> -  info.view->base_level,
> -  info.view->base_array_layer,
> -  info.view->array_len);
> -   }
> -   if (image && (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT)) {
> -  genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
> -  VK_IMAGE_ASPECT_STENCIL_BIT,
> -  ISL_AUX_USAGE_NONE,
> -  info.view->base_level,
> -  info.view->base_array_layer,
> -  info.view->array_len);
> -   }
>  }
>  
>  
> @@ -3550,6 +3529,35 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer 
> *cmd_buffer,
>   iview->planes[0].isl.base_level,
>   
> iview->planes[0].isl.base_array_layer,
>   fb->layers);
> +  } else if (subpass->attachments[i].usage ==
> + VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT) {
> + /* We may be writing depth or stencil so we need to mark the 
> surface.
> +  * Unfortunately, there's no way to know at this point whether the
> +  * depth or stencil tests used will actually write to the surface.
> +  *
> +  * Even though stencil may be plane 1, it always shares a base_level
> +  * with depth.
> +  */
> + const struct isl_view *ds_view = >planes[0].isl;
> + if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {

I think this should be iview->aspect_mask.

> +genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
> +VK_IMAGE_ASPECT_DEPTH_BIT,
> +att_state->aux_usage,
> +ds_view->base_level,
> +ds_view->base_array_layer,
> +fb->layers);
> + }
> + if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {

Same comment as above.

With those two issues fixed, this patch is
Reviewed-by: Nanley Chery 


> +/* Even though stencil may be plane 1, it always shares a
> + * base_level with depth.
> + */
> +genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
> +VK_IMAGE_ASPECT_STENCIL_BIT,
> +ISL_AUX_USAGE_NONE,
> +ds_view->base_level,
> +ds_view->base_array_layer,
> +fb->layers);
> + }
>}
>  
>att_state->pending_clear_aspects = 0;
> -- 
> 2.5.0.400.gff86faf
> 
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[Mesa-dev] [AppVeyor] mesa master #6907 failed

[AppVeyor]

Build mesa 6907 failed


Commit 7461bd5b8f by Bas Nieuwenhuizen on 2/13/2018 10:25 PM:

ac: Use the renumbered const address space for LLVM 7.\n\nThe LLVM AMDGPU backend decided to renumber the constant address\nspace \n\nReviewed-by: Samuel Pitoiset 


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Re: [Mesa-dev] [PATCH 11/14] anv/cmd_buffer: Sync clear values in begin_subpass

[Nanley Chery]

On Mon, Feb 05, 2018 at 02:35:00PM -0800, Jason Ekstrand wrote:
> This is quite a bit cleaner because we now sync the clear values at the
> same time as we do the fast clear.  For loading the clear values into
> the surface state, we now do it once when we handle the LOAD_OP_LOAD
> instead of every subpass.
> ---
>  src/intel/vulkan/genX_cmd_buffer.c | 148 
> -
>  1 file changed, 48 insertions(+), 100 deletions(-)
> 
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
> b/src/intel/vulkan/genX_cmd_buffer.c
> index f92e86f..4eee85a 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -3392,97 +3392,6 @@ cmd_buffer_subpass_transition_layouts(struct 
> anv_cmd_buffer * const cmd_buffer,
> }
>  }
>  
> -/* Update the clear value dword(s) in surface state objects or the fast clear
> - * state buffer entry for the color attachments used in this subpass.
> - */
> -static void
> -cmd_buffer_subpass_sync_fast_clear_values(struct anv_cmd_buffer *cmd_buffer)
> -{
> -   assert(cmd_buffer && cmd_buffer->state.subpass);
> -
> -   const struct anv_cmd_state *state = _buffer->state;
> -
> -   /* Iterate through every color attachment used in this subpass. */
> -   for (uint32_t i = 0; i < state->subpass->color_count; ++i) {
> -
> -  /* The attachment should be one of the attachments described in the
> -   * render pass and used in the subpass.
> -   */
> -  const uint32_t a = state->subpass->color_attachments[i].attachment;
> -  if (a == VK_ATTACHMENT_UNUSED)
> - continue;
> -
> -  assert(a < state->pass->attachment_count);
> -
> -  /* Store some information regarding this attachment. */
> -  const struct anv_attachment_state *att_state = >attachments[a];
> -  const struct anv_image_view *iview = 
> state->framebuffer->attachments[a];
> -  const struct anv_render_pass_attachment *rp_att =
> - >pass->attachments[a];
> -
> -  if (att_state->aux_usage == ISL_AUX_USAGE_NONE)
> - continue;
> -
> -  /* The fast clear state entry must be updated if a fast clear is going 
> to
> -   * happen. The surface state must be updated if the clear value from a
> -   * prior fast clear may be needed.
> -   */
> -  if (att_state->pending_clear_aspects && att_state->fast_clear) {
> - /* Update the fast clear state entry. */
> - genX(copy_fast_clear_dwords)(cmd_buffer, att_state->color.state,
> -  iview->image,
> -  VK_IMAGE_ASPECT_COLOR_BIT,
> -  true /* copy from ss */);
> -
> - /* Fast-clears impact whether or not a resolve will be necessary. */
> - if (att_state->clear_color_is_zero) {
> -/* This image always has the auxiliary buffer enabled. We can 
> mark
> - * the subresource as not needing a resolve because the clear 
> color
> - * will match what's in every RENDER_SURFACE_STATE object when 
> it's
> - * being used for sampling.
> - */
> -set_image_fast_clear_state(cmd_buffer, iview->image,
> -   VK_IMAGE_ASPECT_COLOR_BIT,
> -   ANV_FAST_CLEAR_DEFAULT_VALUE);
> - } else {
> -set_image_fast_clear_state(cmd_buffer, iview->image,
> -   VK_IMAGE_ASPECT_COLOR_BIT,
> -   ANV_FAST_CLEAR_ANY);
> - }
> -  } else if (rp_att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD &&
> - iview->planes[0].isl.base_level == 0 &&
> - iview->planes[0].isl.base_array_layer == 0) {
> - /* The attachment may have been fast-cleared in a previous render
> -  * pass and the value is needed now. Update the surface state(s).
> -  *
> -  * TODO: Do this only once per render pass instead of every subpass.
> -  */
> - genX(copy_fast_clear_dwords)(cmd_buffer, att_state->color.state,
> -  iview->image,
> -  VK_IMAGE_ASPECT_COLOR_BIT,
> -  false /* copy to ss */);
> -
> - if (need_input_attachment_state(rp_att) &&
> - att_state->input_aux_usage != ISL_AUX_USAGE_NONE) {
> -genX(copy_fast_clear_dwords)(cmd_buffer, att_state->input.state,
> - iview->image,
> - VK_IMAGE_ASPECT_COLOR_BIT,
> - false /* copy to ss */);
> - }
> -  }
> -
> -  /* We assume that if we're starting a subpass, we're going to do some
> -   * rendering so we may end up with compressed data.
> -   */
> -  genX(cmd_buffer_mark_image_written)(cmd_buffer, iview->image,
> -   

[Mesa-dev] [PATCH 19/21] vulkan: Add VK_GOOGLE_display_timing extension (x11 and display backends)

[Keith Packard]

This adds support for the VK_GOOGLE_display timing extension, which
provides two things:

 1) Detailed information about when frames are displayed, including
slack time between GPU execution and display frame.

 2) Absolute time control over swapchain queue processing. This allows
the application to request frames be displayed at specific
absolute times, using the same timebase as that provided in vblank
events.

Support for this extension has been implemented for the x11 and
display backends; adding support to other backends should be
reasonable straightforward for one familiar with those systems and
should not require any additional device-specific code.

Signed-off-by: Keith Packard 
---
 src/vulkan/wsi/wsi_common.c | 254 +++-
 src/vulkan/wsi/wsi_common.h |  24 
 src/vulkan/wsi/wsi_common_display.c | 143 +++-
 src/vulkan/wsi/wsi_common_private.h |  35 +
 src/vulkan/wsi/wsi_common_x11.c |  69 +-
 5 files changed, 514 insertions(+), 11 deletions(-)

diff --git a/src/vulkan/wsi/wsi_common.c b/src/vulkan/wsi/wsi_common.c
index 02abc9ef7fb..c36e4ccdcbe 100644
--- a/src/vulkan/wsi/wsi_common.c
+++ b/src/vulkan/wsi/wsi_common.c
@@ -40,11 +40,16 @@ wsi_device_init(struct wsi_device *wsi,
PFN_vk##func func = (PFN_vk##func)proc_addr(pdevice, "vk" #func)
WSI_GET_CB(GetPhysicalDeviceMemoryProperties);
WSI_GET_CB(GetPhysicalDeviceQueueFamilyProperties);
+   WSI_GET_CB(GetPhysicalDeviceProperties);
 #undef WSI_GET_CB
 
GetPhysicalDeviceMemoryProperties(pdevice, >memory_props);
GetPhysicalDeviceQueueFamilyProperties(pdevice, >queue_family_count, 
NULL);
 
+   VkPhysicalDeviceProperties properties;
+   GetPhysicalDeviceProperties(pdevice, );
+   wsi->timestamp_period = properties.limits.timestampPeriod;
+
 #define WSI_GET_CB(func) \
wsi->func = (PFN_vk##func)proc_addr(pdevice, "vk" #func)
WSI_GET_CB(AllocateMemory);
@@ -53,14 +58,18 @@ wsi_device_init(struct wsi_device *wsi,
WSI_GET_CB(BindImageMemory);
WSI_GET_CB(BeginCommandBuffer);
WSI_GET_CB(CmdCopyImageToBuffer);
+   WSI_GET_CB(CmdResetQueryPool);
+   WSI_GET_CB(CmdWriteTimestamp);
WSI_GET_CB(CreateBuffer);
WSI_GET_CB(CreateCommandPool);
WSI_GET_CB(CreateFence);
WSI_GET_CB(CreateImage);
+   WSI_GET_CB(CreateQueryPool);
WSI_GET_CB(DestroyBuffer);
WSI_GET_CB(DestroyCommandPool);
WSI_GET_CB(DestroyFence);
WSI_GET_CB(DestroyImage);
+   WSI_GET_CB(DestroyQueryPool);
WSI_GET_CB(EndCommandBuffer);
WSI_GET_CB(FreeMemory);
WSI_GET_CB(FreeCommandBuffers);
@@ -68,9 +77,13 @@ wsi_device_init(struct wsi_device *wsi,
WSI_GET_CB(GetImageMemoryRequirements);
WSI_GET_CB(GetImageSubresourceLayout);
WSI_GET_CB(GetMemoryFdKHR);
+   WSI_GET_CB(GetPhysicalDeviceProperties);
WSI_GET_CB(GetPhysicalDeviceFormatProperties);
+   WSI_GET_CB(GetPhysicalDeviceQueueFamilyProperties);
+   WSI_GET_CB(GetQueryPoolResults);
WSI_GET_CB(ResetFences);
WSI_GET_CB(QueueSubmit);
+   WSI_GET_CB(QueryCurrentTimestampMESA);
WSI_GET_CB(WaitForFences);
 #undef WSI_GET_CB
 
@@ -136,6 +149,8 @@ wsi_swapchain_init(const struct wsi_device *wsi,
chain->device = device;
chain->alloc = *pAllocator;
chain->use_prime_blit = false;
+   chain->timing_insert = 0;
+   chain->timing_count = 0;
 
chain->cmd_pools =
   vk_zalloc(pAllocator, sizeof(VkCommandPool) * wsi->queue_family_count, 8,
@@ -209,6 +224,60 @@ align_u32(uint32_t v, uint32_t a)
return (v + a - 1) & ~(a - 1);
 }
 
+static VkResult
+wsi_image_init_timestamp(const struct wsi_swapchain *chain,
+ struct wsi_image *image)
+{
+   const struct wsi_device *wsi = chain->wsi;
+   VkResult result;
+   /* Set up command buffer to get timestamp info */
+
+   result = wsi->CreateQueryPool(chain->device,
+ &(const VkQueryPoolCreateInfo) {
+.sType = 
VK_STRUCTURE_TYPE_QUERY_POOL_CREATE_INFO,
+   .queryType = VK_QUERY_TYPE_TIMESTAMP,
+   .queryCount = 1,
+   },
+ NULL,
+ >query_pool);
+
+   if (result != VK_SUCCESS)
+  goto fail;
+
+   result = wsi->AllocateCommandBuffers(chain->device,
+&(const VkCommandBufferAllocateInfo) {
+   .sType = 
VK_STRUCTURE_TYPE_COMMAND_BUFFER_ALLOCATE_INFO,
+  .pNext = NULL,
+  .commandPool = 
chain->cmd_pools[0],
+  .level = 
VK_COMMAND_BUFFER_LEVEL_PRIMARY,
+  .commandBufferCount = 1,
+  },
+

[Mesa-dev] [PATCH 01/21] vulkan: Add KHR_display extension using DRM

[Keith Packard]

This adds support for the KHR_display extension support to the vulkan
WSI layer. Driver support will be added separately.

Signed-off-by: Keith Packard 
---
 configure.ac|1 +
 meson.build |4 +-
 src/amd/vulkan/radv_wsi.c   |3 +-
 src/intel/vulkan/anv_wsi.c  |3 +-
 src/vulkan/Makefile.am  |7 +
 src/vulkan/Makefile.sources |4 +
 src/vulkan/wsi/meson.build  |   10 +
 src/vulkan/wsi/wsi_common.c |   19 +-
 src/vulkan/wsi/wsi_common.h |5 +-
 src/vulkan/wsi/wsi_common_display.c | 1368 +++
 src/vulkan/wsi/wsi_common_display.h |   72 ++
 src/vulkan/wsi/wsi_common_private.h |   10 +
 12 files changed, 1500 insertions(+), 6 deletions(-)
 create mode 100644 src/vulkan/wsi/wsi_common_display.c
 create mode 100644 src/vulkan/wsi/wsi_common_display.h

diff --git a/configure.ac b/configure.ac
index 8ed606c7694..46318365603 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1849,6 +1849,7 @@ fi
 AM_CONDITIONAL(HAVE_PLATFORM_X11, echo "$platforms" | grep -q 'x11')
 AM_CONDITIONAL(HAVE_PLATFORM_WAYLAND, echo "$platforms" | grep -q 'wayland')
 AM_CONDITIONAL(HAVE_PLATFORM_DRM, echo "$platforms" | grep -q 'drm')
+AM_CONDITIONAL(HAVE_PLATFORM_DISPLAY, echo "$platforms" | grep -q 'drm')
 AM_CONDITIONAL(HAVE_PLATFORM_SURFACELESS, echo "$platforms" | grep -q 
'surfaceless')
 AM_CONDITIONAL(HAVE_PLATFORM_ANDROID, echo "$platforms" | grep -q 'android')
 
diff --git a/meson.build b/meson.build
index b39e2f8ab96..aeb7f5e2917 100644
--- a/meson.build
+++ b/meson.build
@@ -239,11 +239,12 @@ with_platform_wayland = false
 with_platform_x11 = false
 with_platform_drm = false
 with_platform_surfaceless = false
+with_platform_display = false
 egl_native_platform = ''
 _platforms = get_option('platforms')
 if _platforms == 'auto'
   if system_has_kms_drm
-_platforms = 'x11,wayland,drm,surfaceless'
+_platforms = 'x11,wayland,drm,surfaceless,display'
   elif ['darwin', 'windows', 'cygwin'].contains(host_machine.system())
 _platforms = 'x11,surfaceless'
   else
@@ -257,6 +258,7 @@ if _platforms != ''
   with_platform_wayland = _split.contains('wayland')
   with_platform_drm = _split.contains('drm')
   with_platform_surfaceless = _split.contains('surfaceless')
+  with_platform_display = _split.contains('display')
   egl_native_platform = _split[0]
 endif
 
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index e016e837102..9bdd55ef11c 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -41,7 +41,8 @@ radv_init_wsi(struct radv_physical_device *physical_device)
return wsi_device_init(_device->wsi_device,
   radv_physical_device_to_handle(physical_device),
   radv_wsi_proc_addr,
-  _device->instance->alloc);
+  _device->instance->alloc,
+  physical_device->local_fd);
 }
 
 void
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index 6082c3dd093..f86d83589ea 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -39,7 +39,8 @@ anv_init_wsi(struct anv_physical_device *physical_device)
return wsi_device_init(_device->wsi_device,
   anv_physical_device_to_handle(physical_device),
   anv_wsi_proc_addr,
-  _device->instance->alloc);
+  _device->instance->alloc,
+  physical_device->local_fd);
 }
 
 void
diff --git a/src/vulkan/Makefile.am b/src/vulkan/Makefile.am
index 037436c1cd7..c33ac5758f7 100644
--- a/src/vulkan/Makefile.am
+++ b/src/vulkan/Makefile.am
@@ -57,6 +57,13 @@ AM_CPPFLAGS += \
 VULKAN_WSI_SOURCES += $(VULKAN_WSI_X11_FILES)
 endif
 
+if HAVE_PLATFORM_DISPLAY
+AM_CPPFLAGS += \
+   -DVK_USE_PLATFORM_DISPLAY_KHR
+
+VULKAN_WSI_SOURCES += $(VULKAN_WSI_DISPLAY_FILES)
+endif
+
 BUILT_SOURCES += $(VULKAN_WSI_WAYLAND_GENERATED_FILES)
 CLEANFILES = $(BUILT_SOURCES)
 
diff --git a/src/vulkan/Makefile.sources b/src/vulkan/Makefile.sources
index a0a24ce7de8..3642c7662c4 100644
--- a/src/vulkan/Makefile.sources
+++ b/src/vulkan/Makefile.sources
@@ -17,6 +17,10 @@ VULKAN_WSI_X11_FILES := \
wsi/wsi_common_x11.c \
wsi/wsi_common_x11.h
 
+VULKAN_WSI_DISPLAY_FILES := \
+   wsi/wsi_common_display.c \
+   wsi/wsi_common_display.h
+
 VULKAN_UTIL_FILES := \
util/vk_alloc.h \
util/vk_debug_report.c \
diff --git a/src/vulkan/wsi/meson.build b/src/vulkan/wsi/meson.build
index bd0fd3cc53e..743631a6113 100644
--- a/src/vulkan/wsi/meson.build
+++ b/src/vulkan/wsi/meson.build
@@ -57,6 +57,16 @@ if with_platform_wayland
   ]
 endif
 
+if with_platform_display
+  vulkan_wsi_args += [
+'-DVK_USE_PLATFORM_DISPLAY_KHR',
+  ]
+  files_vulkan_wsi += files(
+'wsi_common_display.c',
+

[Mesa-dev] [PATCH 20/21] anv: Add VK_GOOGLE_display_timing extension to anv driver

[Keith Packard]

This adds support for the VK_GOOGLE_display timing extension.

Signed-off-by: Keith Packard 
---
 src/intel/vulkan/anv_extensions.py |  1 +
 src/intel/vulkan/anv_wsi.c | 29 +
 2 files changed, 30 insertions(+)

diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 7706ccdb5bb..b441b8e1d8e 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -92,6 +92,7 @@ EXTENSIONS = [
 Extension('VK_EXT_display_surface_counter',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_display_control',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_MESA_query_timestamp',  1, True),
+Extension('VK_GOOGLE_display_timing', 1, True),
 ]
 
 class VkVersion:
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index 52362adfb71..7801a989e0d 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -239,3 +239,32 @@ VkResult anv_QueuePresentKHR(
_queue, 0,
pPresentInfo);
 }
+
+/* VK_GOOGLE_display_timing */
+VkResult
+anv_GetRefreshCycleDurationGOOGLE(VkDevice  _device,
+  VkSwapchainKHRswapchain,
+  VkRefreshCycleDurationGOOGLE  
*pDisplayTimingProperties)
+{
+   ANV_FROM_HANDLE(anv_device, device, _device);
+
+   return 
wsi_common_get_refresh_cycle_duration(>instance->physicalDevice.wsi_device,
+_device,
+swapchain,
+pDisplayTimingProperties);
+}
+
+VkResult
+anv_GetPastPresentationTimingGOOGLE(VkDevice
_device,
+VkSwapchainKHR  
swapchain,
+uint32_t
*pPresentationTimingCount,
+VkPastPresentationTimingGOOGLE  
*pPresentationTimings)
+{
+   ANV_FROM_HANDLE(anv_device, device, _device);
+
+   return 
wsi_common_get_past_presentation_timing(>instance->physicalDevice.wsi_device,
+  _device,
+  swapchain,
+  pPresentationTimingCount,
+  pPresentationTimings);
+}
-- 
2.15.1

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[Mesa-dev] [PATCH 10/21] vulkan: Add VK_EXT_display_surface_counter [v3]

[Keith Packard]

This extension is required to support EXT_display_control as it offers
a way to query whether the vblank counter is supported.

v2: Thanks to kisak

Fix spelling of VkSurfaceCapabilities2EXT in wsi_common_wayland.c,
it was using ext instead of EXT.

Fix spelling of VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES_2_EXT

v3: Fix wayland WSI, regularize spelling

Misspelled 'surface' in get_capabilities2ext
Remove extra _ from get_capabilities_2ext in a couple of places

Signed-off-by: Keith Packard 
---
 src/vulkan/wsi/wsi_common.c | 11 +++
 src/vulkan/wsi/wsi_common.h |  5 +
 src/vulkan/wsi/wsi_common_display.c | 27 +++
 src/vulkan/wsi/wsi_common_private.h |  2 ++
 src/vulkan/wsi/wsi_common_wayland.c | 27 +++
 src/vulkan/wsi/wsi_common_x11.c | 27 +++
 6 files changed, 99 insertions(+)

diff --git a/src/vulkan/wsi/wsi_common.c b/src/vulkan/wsi/wsi_common.c
index c0a285e5814..02abc9ef7fb 100644
--- a/src/vulkan/wsi/wsi_common.c
+++ b/src/vulkan/wsi/wsi_common.c
@@ -579,6 +579,17 @@ wsi_common_get_surface_capabilities2(struct wsi_device 
*wsi_device,
pSurfaceCapabilities);
 }
 
+VkResult
+wsi_common_get_surface_capabilities2ext(struct wsi_device *wsi_device,
+VkSurfaceKHR _surface,
+VkSurfaceCapabilities2EXT 
*pSurfaceCapabilities)
+{
+   ICD_FROM_HANDLE(VkIcdSurfaceBase, surface, _surface);
+   struct wsi_interface *iface = wsi_device->wsi[surface->platform];
+
+   return iface->get_capabilities2ext(surface, pSurfaceCapabilities);
+}
+
 VkResult
 wsi_common_get_surface_formats(struct wsi_device *wsi_device,
VkSurfaceKHR _surface,
diff --git a/src/vulkan/wsi/wsi_common.h b/src/vulkan/wsi/wsi_common.h
index 1cb6aaebca0..124d096170a 100644
--- a/src/vulkan/wsi/wsi_common.h
+++ b/src/vulkan/wsi/wsi_common.h
@@ -155,6 +155,11 @@ wsi_common_get_surface_present_modes(struct wsi_device 
*wsi_device,
  uint32_t *pPresentModeCount,
  VkPresentModeKHR *pPresentModes);
 
+VkResult
+wsi_common_get_surface_capabilities2ext(struct wsi_device *wsi_device,
+VkSurfaceKHR surface,
+VkSurfaceCapabilities2EXT 
*pSurfaceCapabilities);
+
 VkResult
 wsi_common_get_images(VkSwapchainKHR _swapchain,
   uint32_t *pSwapchainImageCount,
diff --git a/src/vulkan/wsi/wsi_common_display.c 
b/src/vulkan/wsi/wsi_common_display.c
index 29d64b21aff..e63700e2e65 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -655,6 +655,32 @@ wsi_display_surface_get_capabilities2(VkIcdSurfaceBase 
*icd_surface,
return wsi_display_surface_get_capabilities(icd_surface, 
>surfaceCapabilities);
 }
 
+static VkResult
+wsi_display_surface_get_capabilities2ext(VkIcdSurfaceBase *icd_surface,
+  VkSurfaceCapabilities2EXT *caps)
+{
+   VkSurfaceCapabilitiesKHR khr_caps;
+   VkResult ret;
+
+   assert(caps->sType == VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES_2_EXT);
+   ret = wsi_display_surface_get_capabilities(icd_surface, _caps);
+   if (ret)
+  return ret;
+
+   caps->minImageCount = khr_caps.minImageCount;
+   caps->maxImageCount = khr_caps.maxImageCount;
+   caps->currentExtent = khr_caps.currentExtent;
+   caps->minImageExtent = khr_caps.minImageExtent;
+   caps->maxImageExtent = khr_caps.maxImageExtent;
+   caps->maxImageArrayLayers = khr_caps.maxImageArrayLayers;
+   caps->supportedTransforms = khr_caps.supportedTransforms;
+   caps->currentTransform = khr_caps.currentTransform;
+   caps->supportedCompositeAlpha = khr_caps.supportedCompositeAlpha;
+   caps->supportedUsageFlags = khr_caps.supportedUsageFlags;
+   caps->supportedSurfaceCounters = 0;
+   return ret;
+}
+
 static const VkFormat available_surface_formats[] = {
VK_FORMAT_B8G8R8A8_SRGB,
VK_FORMAT_B8G8R8A8_UNORM,
@@ -1323,6 +1349,7 @@ wsi_display_init_wsi(struct wsi_device *wsi_device,
wsi->base.get_support = wsi_display_surface_get_support;
wsi->base.get_capabilities = wsi_display_surface_get_capabilities;
wsi->base.get_capabilities2 = wsi_display_surface_get_capabilities2;
+   wsi->base.get_capabilities2ext = wsi_display_surface_get_capabilities2ext;
wsi->base.get_formats = wsi_display_surface_get_formats;
wsi->base.get_formats2 = wsi_display_surface_get_formats2;
wsi->base.get_present_modes = wsi_display_surface_get_present_modes;
diff --git a/src/vulkan/wsi/wsi_common_private.h 
b/src/vulkan/wsi/wsi_common_private.h
index d38d2efa116..0d902846238 100644
--- a/src/vulkan/wsi/wsi_common_private.h
+++ b/src/vulkan/wsi/wsi_common_private.h
@@ -103,6 +103,8 @@ struct wsi_interface {
VkResult 

[Mesa-dev] [PATCH 18/21] radv: Add new VK_MESA_query_timestamp extension to radv driver

[Keith Packard]

This extension adds a single function to query the current GPU
timestamp, just like glGetInteger64v(GL_TIMESTAMP, ). This
function is needed to complete the implementation of
GOOGLE_display_timing, which needs to be able to coorelate GPU and CPU
timestamps.

Signed-off-by: Keith Packard 
---
 src/amd/vulkan/Makefile.am| 3 +++
 src/amd/vulkan/meson.build| 8 
 src/amd/vulkan/radv_device.c  | 8 
 src/amd/vulkan/radv_extensions.py | 1 +
 4 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index 94ece06e99e..86dfb0265d6 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -129,12 +129,14 @@ libvulkan_radeon_la_SOURCES = $(VULKAN_GEM_FILES)
 
 vulkan_api_xml = $(top_srcdir)/src/vulkan/registry/vk.xml
 vk_android_native_buffer_xml = 
$(top_srcdir)/src/vulkan/registry/vk_android_native_buffer.xml
+vk_mesa_query_timestamp_xml = 
$(top_srcdir)/src/vulkan/registry/vk_mesa_query_timestamp.xml
 
 radv_entrypoints.c: radv_entrypoints_gen.py radv_extensions.py 
$(vulkan_api_xml)
$(MKDIR_GEN)
$(AM_V_GEN)$(PYTHON2) $(srcdir)/radv_entrypoints_gen.py \
--xml $(vulkan_api_xml) \
--xml $(vk_android_native_buffer_xml) \
+   --xml $(vk_mesa_query_timestamp_xml) \
--outdir $(builddir)
 radv_entrypoints.h: radv_entrypoints.c
 
@@ -144,6 +146,7 @@ radv_extensions.c: radv_extensions.py \
$(AM_V_GEN)$(PYTHON2) $(srcdir)/radv_extensions.py \
--xml $(vulkan_api_xml) \
--xml $(vk_android_native_buffer_xml) \
+   --xml $(vk_mesa_query_timestamp_xml) \
--out $@
 
 vk_format_table.c: vk_format_table.py \
diff --git a/src/amd/vulkan/meson.build b/src/amd/vulkan/meson.build
index 0b92a1763a1..34f578476c0 100644
--- a/src/amd/vulkan/meson.build
+++ b/src/amd/vulkan/meson.build
@@ -20,10 +20,10 @@
 
 radv_entrypoints = custom_target(
   'radv_entrypoints.[ch]',
-  input : ['radv_entrypoints_gen.py', vk_api_xml],
+  input : ['radv_entrypoints_gen.py', vk_api_xml, 
vk_android_native_buffer_xml, vk_mesa_query_timestamp_xml],
   output : ['radv_entrypoints.h', 'radv_entrypoints.c'],
   command : [
-prog_python2, '@INPUT0@', '--xml', '@INPUT1@', '--outdir',
+prog_python2, '@INPUT0@', '--xml', '@INPUT1@', '--xml', '@INPUT2@', 
'--xml', '@INPUT3@', '--outdir',
 meson.current_build_dir()
   ],
   depend_files : files('radv_extensions.py'),
@@ -31,10 +31,10 @@ radv_entrypoints = custom_target(
 
 radv_extensions_c = custom_target(
   'radv_extensions.c',
-  input : ['radv_extensions.py', vk_api_xml, vk_android_native_buffer_xml],
+  input : ['radv_extensions.py', vk_api_xml, vk_android_native_buffer_xml, 
vk_mesa_query_timestamp_xml],
   output : ['radv_extensions.c'],
   command : [
-prog_python2, '@INPUT0@', '--xml', '@INPUT1@', '--xml', '@INPUT2@', 
'--out', '@OUTPUT@',
+prog_python2, '@INPUT0@', '--xml', '@INPUT1@', '--xml', '@INPUT2@', 
'--xml', '@INPUT3@', '--out', '@OUTPUT@',
   ],
 )
 
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 8ae7391c891..09c5ca8edcc 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -4083,3 +4083,11 @@ radv_DebugReportMessageEXT(VkInstance _instance,
vk_debug_report(>debug_report_callbacks, flags, objectType,
object, location, messageCode, pLayerPrefix, pMessage);
 }
+
+VkResult radv_QueryCurrentTimestampMESA(VkDevice _device, uint64_t *timestamp)
+{
+   RADV_FROM_HANDLE(radv_device, device, _device);
+
+   *timestamp = device->ws->query_value(device->ws, RADEON_TIMESTAMP);
+   return VK_SUCCESS;
+}
diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index 42b8d996b6a..0e7b18dc104 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -95,6 +95,7 @@ EXTENSIONS = [
 Extension('VK_AMD_draw_indirect_count',   1, True),
 Extension('VK_AMD_rasterization_order',   1, 
'device->rad_info.chip_class >= VI && device->rad_info.max_se >= 2'),
 Extension('VK_AMD_shader_info',   1, True),
+Extension('VK_MESA_query_timestamp',  1, True),
 ]
 
 class VkVersion:
-- 
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[Mesa-dev] [PATCH 12/21] radv: Add VK_EXT_display_surface_counter to radv driver

[Keith Packard]

This extension is required to support EXT_display_control as it offers
a way to query whether the vblank counter is supported.

Signed-off-by: Keith Packard 
---
 src/amd/vulkan/radv_extensions.py |  1 +
 src/amd/vulkan/radv_wsi.c | 12 
 2 files changed, 13 insertions(+)

diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index df3325d47d4..048192b9e05 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -84,6 +84,7 @@ EXTENSIONS = [
 Extension('VK_KHR_display',  23, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_direct_mode_display',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_acquire_xlib_display',  1, 
'VK_USE_PLATFORM_XLIB_XRANDR_EXT'),
+Extension('VK_EXT_display_surface_counter',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_KHX_multiview', 1, '!ANDROID'),
 Extension('VK_EXT_debug_report',  9, True),
 Extension('VK_EXT_discard_rectangles',1, True),
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index 9bdd55ef11c..2433390562b 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -103,6 +103,18 @@ VkResult radv_GetPhysicalDeviceSurfaceCapabilities2KHR(
pSurfaceCapabilities);
 }
 
+VkResult radv_GetPhysicalDeviceSurfaceCapabilities2EXT(
+   VkPhysicalDevicephysicalDevice,
+   VkSurfaceKHRsurface,
+   VkSurfaceCapabilities2EXT*  pSurfaceCapabilities)
+{
+   RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
+
+   return wsi_common_get_surface_capabilities2ext(>wsi_device,
+  surface,
+  pSurfaceCapabilities);
+}
+
 VkResult radv_GetPhysicalDeviceSurfaceFormatsKHR(
VkPhysicalDevicephysicalDevice,
VkSurfaceKHRsurface,
-- 
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[Mesa-dev] [PATCH 21/21] radv: Add VK_GOOGLE_display_timing extension to radv driver

[Keith Packard]

This adds support for the VK_GOOGLE_display timing extension.

Signed-off-by: Keith Packard 
---
 src/amd/vulkan/radv_extensions.py |  1 +
 src/amd/vulkan/radv_wsi.c | 32 
 2 files changed, 33 insertions(+)

diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index 0e7b18dc104..a8d9c8410e1 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -96,6 +96,7 @@ EXTENSIONS = [
 Extension('VK_AMD_rasterization_order',   1, 
'device->rad_info.chip_class >= VI && device->rad_info.max_se >= 2'),
 Extension('VK_AMD_shader_info',   1, True),
 Extension('VK_MESA_query_timestamp',  1, True),
+Extension('VK_GOOGLE_display_timing', 1, True),
 ]
 
 class VkVersion:
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index 2433390562b..fd26194f6ce 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -247,3 +247,35 @@ VkResult radv_QueuePresentKHR(
queue->queue_family_index,
pPresentInfo);
 }
+
+/* VK_GOOGLE_display_timing */
+VkResult
+radv_GetRefreshCycleDurationGOOGLE(
+   VkDevice  _device,
+   VkSwapchainKHRswapchain,
+   VkRefreshCycleDurationGOOGLE  *pDisplayTimingProperties)
+{
+   RADV_FROM_HANDLE(radv_device, device, _device);
+   struct radv_physical_device *pdevice = device->physical_device;
+
+   return wsi_common_get_refresh_cycle_duration(>wsi_device,
+_device,
+swapchain,
+pDisplayTimingProperties);
+}
+
+VkResult
+radv_GetPastPresentationTimingGOOGLE(VkDevice
_device,
+VkSwapchainKHR  
swapchain,
+uint32_t
*pPresentationTimingCount,
+VkPastPresentationTimingGOOGLE  
*pPresentationTimings)
+{
+   RADV_FROM_HANDLE(radv_device, device, _device);
+   struct radv_physical_device *pdevice = device->physical_device;
+
+   return wsi_common_get_past_presentation_timing(>wsi_device,
+  _device,
+  swapchain,
+  pPresentationTimingCount,
+  pPresentationTimings);
+}
-- 
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[Mesa-dev] [PATCH 09/21] radv: Add EXT_acquire_xlib_display to radv driver

[Keith Packard]

This extension adds the ability to borrow an X RandR output for
temporary use directly by a Vulkan application to the radv driver.

Signed-off-by: Keith Packard 
---
 src/amd/vulkan/Makefile.am|  7 +++
 src/amd/vulkan/meson.build|  7 +++
 src/amd/vulkan/radv_extensions.py | 11 ++-
 src/amd/vulkan/radv_wsi_display.c | 30 ++
 4 files changed, 50 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index 061b8144b88..94ece06e99e 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -81,7 +81,14 @@ AM_CPPFLAGS += \
-DVK_USE_PLATFORM_DISPLAY_KHR
 
 VULKAN_SOURCES += $(VULKAN_WSI_DISPLAY_FILES)
+endif
+
+if HAVE_XLIB_LEASE
+AM_CPPFLAGS += \
+   -DVK_USE_PLATFORM_XLIB_XRANDR_EXT \
+   $(XCB_RANDR_CFLAGS)
 
+VULKAN_LIB_DEPS += $(XCB_RANDR_LIBS)
 endif
 
 if HAVE_PLATFORM_X11
diff --git a/src/amd/vulkan/meson.build b/src/amd/vulkan/meson.build
index b7bb1075e7d..0b92a1763a1 100644
--- a/src/amd/vulkan/meson.build
+++ b/src/amd/vulkan/meson.build
@@ -119,6 +119,13 @@ if with_platform_display
   libradv_files += files('radv_wsi_display.c')
 endif
 
+if with_xlib_lease
+  radv_deps += dep_xcb_xrandr
+  radv_flags += [
+'-DVK_USE_PLATFORM_XLIB_XRANDR_EXT',
+  ]
+endif
+
 libvulkan_radeon = shared_library(
   'vulkan_radeon',
   [libradv_files, radv_entrypoints, radv_extensions_c, vk_format_table_c],
diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index b04b9bf87b0..df3325d47d4 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -83,6 +83,7 @@ EXTENSIONS = [
 Extension('VK_KHR_xlib_surface',  6, 
'VK_USE_PLATFORM_XLIB_KHR'),
 Extension('VK_KHR_display',  23, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_direct_mode_display',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
+Extension('VK_EXT_acquire_xlib_display',  1, 
'VK_USE_PLATFORM_XLIB_XRANDR_EXT'),
 Extension('VK_KHX_multiview', 1, '!ANDROID'),
 Extension('VK_EXT_debug_report',  9, True),
 Extension('VK_EXT_discard_rectangles',1, True),
@@ -170,12 +171,12 @@ _TEMPLATE = Template(COPYRIGHT + """
 #include "vk_util.h"
 
 /* Convert the VK_USE_PLATFORM_* defines to booleans */
-%for platform in ['ANDROID', 'WAYLAND', 'XCB', 'XLIB', 'DISPLAY']:
-#ifdef VK_USE_PLATFORM_${platform}_KHR
-#   undef VK_USE_PLATFORM_${platform}_KHR
-#   define VK_USE_PLATFORM_${platform}_KHR true
+%for platform in ['ANDROID_KHR', 'WAYLAND_KHR', 'XCB_KHR', 'XLIB_KHR', 
'DISPLAY_KHR', 'XLIB_XRANDR_EXT']:
+#ifdef VK_USE_PLATFORM_${platform}
+#   undef VK_USE_PLATFORM_${platform}
+#   define VK_USE_PLATFORM_${platform} true
 #else
-#   define VK_USE_PLATFORM_${platform}_KHR false
+#   define VK_USE_PLATFORM_${platform} false
 #endif
 %endfor
 
diff --git a/src/amd/vulkan/radv_wsi_display.c 
b/src/amd/vulkan/radv_wsi_display.c
index deaf61ce0df..d7a5956ad97 100644
--- a/src/amd/vulkan/radv_wsi_display.c
+++ b/src/amd/vulkan/radv_wsi_display.c
@@ -152,3 +152,33 @@ radv_ReleaseDisplayEXT(VkPhysicalDevice physical_device,
   >wsi_device,
   display);
 }
+
+#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT
+VkResult
+radv_AcquireXlibDisplayEXT(VkPhysicalDevice physical_device,
+  Display  *dpy,
+  VkDisplayKHR display)
+{
+   RADV_FROM_HANDLE(radv_physical_device, pdevice, physical_device);
+
+   return wsi_acquire_xlib_display(physical_device,
+   >wsi_device,
+   dpy,
+   display);
+}
+
+VkResult
+radv_GetRandROutputDisplayEXT(VkPhysicalDevice  physical_device,
+ Display   *dpy,
+ RROutput  output,
+ VkDisplayKHR  *display)
+{
+   RADV_FROM_HANDLE(radv_physical_device, pdevice, physical_device);
+
+   return wsi_get_randr_output_display(physical_device,
+   >wsi_device,
+   dpy,
+   output,
+   display);
+}
+#endif /* VK_USE_PLATFORM_XLIB_XRANDR_EXT */
-- 
2.15.1

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[Mesa-dev] [PATCH 13/21] vulkan: add VK_EXT_display_control [v3]

[Keith Packard]

This extension provides fences and frame count information to direct
display contexts. It uses new kernel ioctls to provide 64-bits of
vblank sequence and nanosecond resolution.

v2: Remove DRM_CRTC_SEQUENCE_FIRST_PIXEL_OUT flag. This has
been removed from the proposed kernel API.

Add NULL parameter to drmCrtcQueueSequence ioctl as we
don't care what sequence the event was actually queued to.

v3: Adapt to pthread clock switch to MONOTONIC

Signed-off-by: Keith Packard 
---
 src/vulkan/wsi/wsi_common.h |   9 ++
 src/vulkan/wsi/wsi_common_display.c | 286 +++-
 src/vulkan/wsi/wsi_common_display.h |  29 
 3 files changed, 323 insertions(+), 1 deletion(-)

diff --git a/src/vulkan/wsi/wsi_common.h b/src/vulkan/wsi/wsi_common.h
index 124d096170a..e504f4120ad 100644
--- a/src/vulkan/wsi/wsi_common.h
+++ b/src/vulkan/wsi/wsi_common.h
@@ -48,6 +48,15 @@ struct wsi_memory_allocate_info {
 bool implicit_sync;
 };
 
+struct wsi_fence {
+   VkDevice device;
+   const struct wsi_device  *wsi_device;
+   VkDisplayKHR display;
+   const VkAllocationCallbacks  *alloc;
+   bool (*wait)(struct wsi_fence *fence, bool 
absolute, uint64_t timeout);
+   void (*destroy)(struct wsi_fence *fence);
+};
+
 struct wsi_interface;
 
 #define VK_ICD_WSI_PLATFORM_MAX 6
diff --git a/src/vulkan/wsi/wsi_common_display.c 
b/src/vulkan/wsi/wsi_common_display.c
index e63700e2e65..c3608f13e54 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -77,6 +77,7 @@ typedef struct wsi_display_connector {
bool active;
wsi_display_mode *current_mode;
drmModeModeInfo  current_drm_mode;
+   uint32_t dpms_property;
 #ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT
xcb_randr_output_t   output;
 #endif
@@ -124,6 +125,15 @@ struct wsi_display_swapchain {
struct wsi_display_image images[0];
 };
 
+struct wsi_display_fence {
+   struct wsi_fence base;
+   bool event_received;
+   bool destroyed;
+   uint64_t sequence;
+};
+
+static uint64_t fence_sequence;
+
 ICD_DEFINE_NONDISP_HANDLE_CASTS(wsi_display_mode, VkDisplayModeKHR)
 ICD_DEFINE_NONDISP_HANDLE_CASTS(wsi_display_connector, VkDisplayKHR)
 
@@ -271,6 +281,7 @@ wsi_display_get_connector(struct wsi_device 
*wsi_device,
drmModeConnectorPtr  drm_connector;
VkResult result;
int  m;
+   int  p;
 
if (wsi->master_fd < 0)
   return NULL;
@@ -292,6 +303,18 @@ wsi_display_get_connector(struct wsi_device 
*wsi_device,
 
connector->connected = drm_connector->connection != DRM_MODE_DISCONNECTED;
 
+   /* Look for a DPMS property */
+   for (p = 0; p < drm_connector->count_props; p++) {
+  drmModePropertyPtr prop = drmModeGetProperty(wsi->master_fd, 
drm_connector->props[p]);
+  if (!prop)
+ continue;
+  if (prop->flags & DRM_MODE_PROP_ENUM) {
+ if (!strcmp(prop->name, "DPMS"))
+connector->dpms_property = drm_connector->props[p];
+  }
+  drmModeFreeProperty(prop);
+   }
+
/* Mark all connector modes as invalid */
wsi_display_invalidate_connector_modes(wsi_device, connector);
 
@@ -677,7 +700,7 @@ wsi_display_surface_get_capabilities2ext(VkIcdSurfaceBase 
*icd_surface,
caps->currentTransform = khr_caps.currentTransform;
caps->supportedCompositeAlpha = khr_caps.supportedCompositeAlpha;
caps->supportedUsageFlags = khr_caps.supportedUsageFlags;
-   caps->supportedSurfaceCounters = 0;
+   caps->supportedSurfaceCounters = VK_SURFACE_COUNTER_VBLANK_EXT;
return ret;
 }
 
@@ -865,12 +888,20 @@ static void wsi_display_page_flip_handler(int fd, 
unsigned int frame,
wsi_display_page_flip_handler2(fd, frame, sec, usec, 0, data);
 }
 
+static void wsi_display_vblank_handler(int fd, unsigned int frame,
+   unsigned int sec, unsigned int usec, 
void *data);
+
+static void wsi_display_sequence_handler(int fd, uint64_t frame,
+ uint64_t ns, uint64_t user_data);
+
 static drmEventContext event_context = {
.version = DRM_EVENT_CONTEXT_VERSION,
.page_flip_handler = wsi_display_page_flip_handler,
 #if DRM_EVENT_CONTEXT_VERSION >= 3
.page_flip_handler2 = wsi_display_page_flip_handler2,
 #endif
+   .vblank_handler = wsi_display_vblank_handler,
+   .sequence_handler = wsi_display_sequence_handler,
 };
 
 static void *
@@ -1117,6 +1148,135 @@ bail:
 
 }
 
+static bool
+wsi_display_fence_wait(struct wsi_fence *fence_wsi,
+   bool absolute,
+   uint64_t timeout)
+{
+   const struct wsi_device  *wsi_device = fence_wsi->wsi_device;
+   struct 

[Mesa-dev] [PATCH 06/21] radv: Add EXT_direct_mode_display to radv driver

[Keith Packard]

Add support for the EXT_direct_mode_display extension. This just
provides the vkReleaseDisplayEXT function.

Signed-off-by: Keith Packard 
---
 src/amd/vulkan/radv_extensions.py |  1 +
 src/amd/vulkan/radv_wsi_display.c | 11 +++
 2 files changed, 12 insertions(+)

diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index 8a079595d40..b04b9bf87b0 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -82,6 +82,7 @@ EXTENSIONS = [
 Extension('VK_KHR_xcb_surface',   6, 
'VK_USE_PLATFORM_XCB_KHR'),
 Extension('VK_KHR_xlib_surface',  6, 
'VK_USE_PLATFORM_XLIB_KHR'),
 Extension('VK_KHR_display',  23, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
+Extension('VK_EXT_direct_mode_display',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_KHX_multiview', 1, '!ANDROID'),
 Extension('VK_EXT_debug_report',  9, True),
 Extension('VK_EXT_discard_rectangles',1, True),
diff --git a/src/amd/vulkan/radv_wsi_display.c 
b/src/amd/vulkan/radv_wsi_display.c
index f98a071513d..deaf61ce0df 100644
--- a/src/amd/vulkan/radv_wsi_display.c
+++ b/src/amd/vulkan/radv_wsi_display.c
@@ -141,3 +141,14 @@ radv_CreateDisplayPlaneSurfaceKHR(VkInstance   
 _instanc
 
return wsi_create_display_surface(_instance, alloc, create_info, 
surface);
 }
+
+VkResult
+radv_ReleaseDisplayEXT(VkPhysicalDevice physical_device,
+  VkDisplayKHR display)
+{
+   RADV_FROM_HANDLE(radv_physical_device, pdevice, physical_device);
+
+   return wsi_release_display(physical_device,
+  >wsi_device,
+  display);
+}
-- 
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[Mesa-dev] [PATCH 15/21] radv: add VK_EXT_display_control to radv driver

[Keith Packard]

This extension provides fences and frame count information to direct
display contexts. It uses new kernel ioctls to provide 64-bits of
vblank sequence and nanosecond resolution.

Signed-off-by: Keith Packard 
---
 src/amd/vulkan/radv_extensions.py |   1 +
 src/amd/vulkan/radv_private.h |  11 +++-
 src/amd/vulkan/radv_wsi_display.c | 109 ++
 3 files changed, 120 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index 048192b9e05..42b8d996b6a 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -85,6 +85,7 @@ EXTENSIONS = [
 Extension('VK_EXT_direct_mode_display',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_acquire_xlib_display',  1, 
'VK_USE_PLATFORM_XLIB_XRANDR_EXT'),
 Extension('VK_EXT_display_surface_counter',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
+Extension('VK_EXT_display_control',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_KHX_multiview', 1, '!ANDROID'),
 Extension('VK_EXT_debug_report',  9, True),
 Extension('VK_EXT_discard_rectangles',1, True),
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 1e3719bcc4f..fc6a5781847 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1647,8 +1647,17 @@ void radv_initialise_cmask(struct radv_cmd_buffer 
*cmd_buffer,
 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
 struct radv_image *image, uint32_t value);
 
+enum radv_fence_type {
+   RADV_FENCE_TYPE_WINSYS = 0,
+   RADV_FENCE_TYPE_WSI = 1
+};
+
 struct radv_fence {
-   struct radeon_winsys_fence *fence;
+   enum radv_fence_type type;
+   union {
+   struct radeon_winsys_fence  *fence;
+   struct wsi_fence*fence_wsi;
+   };
bool submitted;
bool signalled;
 
diff --git a/src/amd/vulkan/radv_wsi_display.c 
b/src/amd/vulkan/radv_wsi_display.c
index d7a5956ad97..92d8936bba0 100644
--- a/src/amd/vulkan/radv_wsi_display.c
+++ b/src/amd/vulkan/radv_wsi_display.c
@@ -182,3 +182,112 @@ radv_GetRandROutputDisplayEXT(VkPhysicalDevice  
physical_device,
display);
 }
 #endif /* VK_USE_PLATFORM_XLIB_XRANDR_EXT */
+
+/* VK_EXT_display_control */
+
+VkResult
+radv_DisplayPowerControlEXT(VkDevice_device,
+   VkDisplayKHRdisplay,
+   const VkDisplayPowerInfoEXT *display_power_info)
+{
+   RADV_FROM_HANDLE(radv_device, device, _device);
+
+   return wsi_display_power_control(_device,
+>physical_device->wsi_device,
+display,
+display_power_info);
+}
+
+VkResult
+radv_RegisterDeviceEventEXT(VkDevice_device,
+   const VkDeviceEventInfoEXT  *device_event_info,
+   const VkAllocationCallbacks *allocator,
+   VkFence *_fence)
+{
+   RADV_FROM_HANDLE(radv_device, device, _device);
+   const VkAllocationCallbacks  *alloc;
+   struct radv_fence*fence;
+   VkResult ret;
+
+   if (allocator)
+   alloc = allocator;
+   else
+   alloc = >instance->alloc;
+
+   fence = vk_alloc(alloc, sizeof (*fence), 8,
+VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
+   if (!fence)
+   return VK_ERROR_OUT_OF_HOST_MEMORY;
+
+   fence->type = RADV_FENCE_TYPE_WSI;
+   fence->submitted = true;
+   fence->signalled = false;
+
+   ret = wsi_register_device_event(_device,
+   >physical_device->wsi_device,
+   device_event_info,
+   alloc,
+   >fence_wsi);
+   if (ret == VK_SUCCESS)
+   *_fence = radv_fence_to_handle(fence);
+   else
+   vk_free(alloc, fence);
+   return ret;
+}
+
+VkResult
+radv_RegisterDisplayEventEXT(VkDevice   _device,
+VkDisplayKHR   display,
+const VkDisplayEventInfoEXT
*display_event_info,
+const VkAllocationCallbacks*allocator,
+VkFence*_fence)
+{
+   RADV_FROM_HANDLE(radv_device, device, _device);
+
+   const VkAllocationCallbacks  *alloc;
+   struct radv_fence*fence;
+   VkResult ret;
+
+   if (allocator)
+   alloc = 

[Mesa-dev] [PATCH 17/21] anv: Add new VK_MESA_query_timestamp extension to anv driver

[Keith Packard]

This extension adds a single function to query the current GPU
timestamp, just like glGetInteger64v(GL_TIMESTAMP, ). This
function is needed to complete the implementation of
GOOGLE_display_timing, which needs to be able to coorelate GPU and CPU
timestamps.

Signed-off-by: Keith Packard 
---
 src/intel/Makefile.vulkan.am   |  7 +++
 src/intel/vulkan/anv_extensions.py |  1 +
 src/intel/vulkan/anv_gem.c | 13 +
 src/intel/vulkan/anv_private.h |  1 +
 src/intel/vulkan/genX_query.c  | 15 +++
 src/intel/vulkan/meson.build   | 12 ++--
 6 files changed, 43 insertions(+), 6 deletions(-)

diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
index 0f0d3815097..5d4298c040a 100644
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -24,36 +24,43 @@
 # out and we'll fail at `make dist'
 vulkan_api_xml = $(top_srcdir)/src/vulkan/registry/vk.xml
 vk_android_native_buffer_xml = 
$(top_srcdir)/src/vulkan/registry/vk_android_native_buffer.xml
+vk_mesa_query_timestamp_xml = 
$(top_srcdir)/src/vulkan/registry/vk_mesa_query_timestamp.xml
 
 vulkan/anv_entrypoints.c: vulkan/anv_entrypoints_gen.py \
  vulkan/anv_extensions.py \
  $(vulkan_api_xml) \
+ $(vk_mesa_query_timestamp_xml) \
  $(vk_android_native_buffer_xml)
$(MKDIR_GEN)
$(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_entrypoints_gen.py \
--xml $(vulkan_api_xml) \
--xml $(vk_android_native_buffer_xml) \
+   --xml $(vk_mesa_query_timestamp_xml) \
--outdir $(builddir)/vulkan
 vulkan/anv_entrypoints.h: vulkan/anv_entrypoints.c
 
 vulkan/anv_extensions.c: vulkan/anv_extensions_gen.py \
 vulkan/anv_extensions.py \
 $(vulkan_api_xml) \
+$(vk_mesa_query_timestamp_xml) \
 $(vk_android_native_buffer_xml)
$(MKDIR_GEN)
$(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_extensions_gen.py \
--xml $(vulkan_api_xml) \
--xml $(vk_android_native_buffer_xml) \
+   --xml $(vk_mesa_query_timestamp_xml) \
--out-c $@
 
 vulkan/anv_extensions.h: vulkan/anv_extensions_gen.py \
 vulkan/anv_extensions.py \
 $(vulkan_api_xml) \
+$(vk_mesa_query_timestamp_xml) \
 $(vk_android_native_buffer_xml)
$(MKDIR_GEN)
$(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_extensions_gen.py \
--xml $(vulkan_api_xml) \
--xml $(vk_android_native_buffer_xml) \
+   --xml $(vk_mesa_query_timestamp_xml) \
--out-h $@
 
 BUILT_SOURCES += $(VULKAN_GENERATED_FILES)
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 1c6c4f8e27b..7706ccdb5bb 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -91,6 +91,7 @@ EXTENSIONS = [
 Extension('VK_EXT_external_memory_dma_buf',   1, True),
 Extension('VK_EXT_display_surface_counter',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_display_control',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
+Extension('VK_MESA_query_timestamp',  1, True),
 ]
 
 class VkVersion:
diff --git a/src/intel/vulkan/anv_gem.c b/src/intel/vulkan/anv_gem.c
index 34c09891086..588b323d113 100644
--- a/src/intel/vulkan/anv_gem.c
+++ b/src/intel/vulkan/anv_gem.c
@@ -418,6 +418,19 @@ anv_gem_fd_to_handle(struct anv_device *device, int fd)
return args.handle;
 }
 
+int
+anv_gem_reg_read(struct anv_device *device, uint32_t offset, uint64_t *result)
+{
+   struct drm_i915_reg_read args = {
+  .offset = offset
+   };
+
+   int ret = anv_ioctl(device->fd, DRM_IOCTL_I915_REG_READ, );
+
+   *result = args.val;
+   return ret;
+}
+
 #ifndef SYNC_IOC_MAGIC
 /* duplicated from linux/sync_file.h to avoid build-time dependency
  * on new (v4.7) kernel headers.  Once distro's are mostly using
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 1d3e5fcd921..337d8ca3f15 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -932,6 +932,7 @@ bool anv_gem_supports_48b_addresses(int fd);
 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
 uint32_t *active, uint32_t *pending);
 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
+int anv_gem_reg_read(struct anv_device *device, uint32_t offset, uint64_t 
*result);
 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, 
uint32_t caching);
 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
diff --git 

[Mesa-dev] [PATCH 07/21] vulkan: Add EXT_acquire_xlib_display

[Keith Packard]

This extension adds the ability to borrow an X RandR output for
temporary use directly by a Vulkan application. For DRM, we use the
Linux resource leasing mechanism.

Signed-off-by: Keith Packard 
---
 configure.ac|  32 +++
 meson.build |  17 ++
 meson_options.txt   |   7 +
 src/vulkan/Makefile.am  |   5 +
 src/vulkan/wsi/meson.build  |   7 +
 src/vulkan/wsi/wsi_common_display.c | 472 
 src/vulkan/wsi/wsi_common_display.h |  17 ++
 7 files changed, 557 insertions(+)

diff --git a/configure.ac b/configure.ac
index 46318365603..cf05d049c26 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1547,6 +1547,7 @@ AM_CONDITIONAL(HAVE_APPLEDRI, test "x$enable_dri" = xyes 
-a "x$dri_platform" = x
 AM_CONDITIONAL(HAVE_LMSENSORS, test "x$enable_lmsensors" = xyes )
 AM_CONDITIONAL(HAVE_GALLIUM_EXTRA_HUD, test "x$enable_gallium_extra_hud" = 
xyes )
 AM_CONDITIONAL(HAVE_WINDOWSDRI, test "x$enable_dri" = xyes -a "x$dri_platform" 
= xwindows )
+AM_CONDITIONAL(HAVE_XLEASE, test "x$have_xlease" = xyes )
 
 AC_ARG_ENABLE([shared-glapi],
 [AS_HELP_STRING([--enable-shared-glapi],
@@ -1846,6 +1847,18 @@ if test x"$enable_dri3" = xyes; then
 PKG_CHECK_MODULES([XCB_DRI3], [$dri3_modules])
 fi
 
+
+if echo "$platforms" | grep -q 'x11' && echo "$platforms" | grep -q 'drm'; then
+have_xlease=yes
+else
+have_xlease=no
+fi
+
+if test x"$have_xlease" = xyes; then
+randr_modules="x11-xcb xcb-randr"
+PKG_CHECK_MODULES([XCB_RANDR], [$randr_modules])
+fi
+
 AM_CONDITIONAL(HAVE_PLATFORM_X11, echo "$platforms" | grep -q 'x11')
 AM_CONDITIONAL(HAVE_PLATFORM_WAYLAND, echo "$platforms" | grep -q 'wayland')
 AM_CONDITIONAL(HAVE_PLATFORM_DRM, echo "$platforms" | grep -q 'drm')
@@ -1853,6 +1866,25 @@ AM_CONDITIONAL(HAVE_PLATFORM_DISPLAY, echo "$platforms" 
| grep -q 'drm')
 AM_CONDITIONAL(HAVE_PLATFORM_SURFACELESS, echo "$platforms" | grep -q 
'surfaceless')
 AM_CONDITIONAL(HAVE_PLATFORM_ANDROID, echo "$platforms" | grep -q 'android')
 
+AC_ARG_ENABLE(xlib-lease,
+[AS_HELP_STRING([--enable-xlib-lease]
+[enable VK_acquire_xlib_display using X leases])],
+[enable_xlib_lease=$enableval], [enable_xlib_lease=auto])
+case "x$enable_xlib_lease" in
+xyes)
+;;
+xno)
+;;
+*)
+if echo "$platforms" | grep -q 'x11' && echo "$platforms" | grep -q 'drm'; 
then
+enable_xlib_lease=yes
+else
+enable_xlib_lease=no
+fi
+esac
+
+AM_CONDITIONAL(HAVE_XLIB_LEASE, test "x$enable_xlib_lease" = xyes)
+
 dnl
 dnl More DRI setup
 dnl
diff --git a/meson.build b/meson.build
index aeb7f5e2917..595b0f66cd7 100644
--- a/meson.build
+++ b/meson.build
@@ -262,6 +262,19 @@ if _platforms != ''
   egl_native_platform = _split[0]
 endif
 
+with_xlib_lease = get_option('xlib-lease')
+if with_xlib_lease == 'auto'
+  if with_platform_x11 and with_platform_display
+with_xlib_lease = true
+  else
+with_xlib_lease = false
+  endif
+elif with_xlib_lease == 'true'
+  with_xlib_lease = true
+else
+  with_xlib_lease = false
+endif
+
 with_glx = get_option('glx')
 if with_glx == 'auto'
   if with_dri
@@ -1151,6 +1164,7 @@ dep_xcb_present = []
 dep_xcb_sync = []
 dep_xcb_xfixes = []
 dep_xshmfence = []
+dep_xcb_xrandr = []
 if with_platform_x11
   if with_glx == 'xlib' or with_glx == 'gallium-xlib'
 dep_x11 = dependency('x11')
@@ -1190,6 +1204,9 @@ if with_platform_x11
   if with_egl
 dep_xcb_xfixes = dependency('xcb-xfixes')
   endif
+  if with_xlib_lease
+dep_xcb_xrandr = dependency('xcb-randr', version : '>= 1.12')
+  endif
 endif
 
 if get_option('gallium-extra-hud')
diff --git a/meson_options.txt b/meson_options.txt
index 7fafe2deaac..d38c9aa6149 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -286,3 +286,10 @@ option(
   value : '',
   description : 'Comma delimited list of tools to build. choices : 
freedreno,glsl,intel,nir,nouveau or all'
 )
+option(
+  'xlib-lease',
+  type : 'combo',
+  value : 'auto',
+  choices : ['auto', 'true', 'false'],
+  description : 'Enable VK_EXT_acquire_xlib_display.'
+)
diff --git a/src/vulkan/Makefile.am b/src/vulkan/Makefile.am
index c33ac5758f7..e96ef68972c 100644
--- a/src/vulkan/Makefile.am
+++ b/src/vulkan/Makefile.am
@@ -64,6 +64,11 @@ AM_CPPFLAGS += \
 VULKAN_WSI_SOURCES += $(VULKAN_WSI_DISPLAY_FILES)
 endif
 
+if HAVE_XLIB_LEASE
+AM_CPPFLAGS += \
+   -DVK_USE_PLATFORM_XLIB_XRANDR_EXT
+endif
+
 BUILT_SOURCES += $(VULKAN_WSI_WAYLAND_GENERATED_FILES)
 CLEANFILES = $(BUILT_SOURCES)
 
diff --git a/src/vulkan/wsi/meson.build b/src/vulkan/wsi/meson.build
index 743631a6113..5e3d43a2748 100644
--- a/src/vulkan/wsi/meson.build
+++ b/src/vulkan/wsi/meson.build
@@ -67,6 +67,13 @@ if with_platform_display
   )
 endif
 
+if with_xlib_lease
+  vulkan_wsi_deps += dep_xcb_xrandr
+  vulkan_wsi_args += [
+'-DVK_USE_PLATFORM_XLIB_XRANDR_EXT',
+  ]
+endif
+
 libvulkan_wsi = static_library(
   'vulkan_wsi',
   

[Mesa-dev] [PATCH 11/21] anv: Add VK_EXT_display_surface_counter to anv driver [v4]

[Keith Packard]

This extension is required to support EXT_display_control as it offers
a way to query whether the vblank counter is supported.

v4: Add anv support

Signed-off-by: Keith Packard 
---
 src/intel/vulkan/anv_extensions.py |  1 +
 src/intel/vulkan/anv_wsi.c | 12 
 2 files changed, 13 insertions(+)

diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 47993f45d41..32643e31045 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -89,6 +89,7 @@ EXTENSIONS = [
 Extension('VK_KHX_multiview', 1, True),
 Extension('VK_EXT_debug_report',  8, True),
 Extension('VK_EXT_external_memory_dma_buf',   1, True),
+Extension('VK_EXT_display_surface_counter',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 ]
 
 class VkVersion:
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index f86d83589ea..52362adfb71 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -104,6 +104,18 @@ VkResult anv_GetPhysicalDeviceSurfaceCapabilities2KHR(
pSurfaceCapabilities);
 }
 
+VkResult anv_GetPhysicalDeviceSurfaceCapabilities2EXT(
+   VkPhysicalDevicephysicalDevice,
+   VkSurfaceKHRsurface,
+   VkSurfaceCapabilities2EXT*  pSurfaceCapabilities)
+{
+   ANV_FROM_HANDLE(anv_physical_device, device, physicalDevice);
+
+   return wsi_common_get_surface_capabilities2ext(>wsi_device,
+  surface,
+  pSurfaceCapabilities);
+}
+
 VkResult anv_GetPhysicalDeviceSurfaceFormatsKHR(
 VkPhysicalDevicephysicalDevice,
 VkSurfaceKHRsurface,
-- 
2.15.1

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[Mesa-dev] [PATCH 16/21] vulkan: Define new VK_MESA_query_timestamp extension

[Keith Packard]

This extension adds a single function to query the current GPU
timestamp, just like glGetInteger64v(GL_TIMESTAMP, ). This
function is needed to complete the implementation of
GOOGLE_display_timing, which needs to be able to coorelate GPU and CPU
timestamps.

Signed-off-by: Keith Packard 
---
 include/vulkan/vulkan.h |  6 ++
 src/Makefile.am |  1 +
 src/vulkan/meson.build  |  1 +
 src/vulkan/registry/vk_mesa_query_timestamp.xml | 22 ++
 4 files changed, 30 insertions(+)
 create mode 100644 src/vulkan/registry/vk_mesa_query_timestamp.xml

diff --git a/include/vulkan/vulkan.h b/include/vulkan/vulkan.h
index d3e2e246cf3..5523eb7586f 100644
--- a/include/vulkan/vulkan.h
+++ b/include/vulkan/vulkan.h
@@ -7025,6 +7025,12 @@ VKAPI_ATTR VkResult VKAPI_CALL 
vkGetMemoryHostPointerPropertiesEXT(
 VkMemoryHostPointerPropertiesEXT*   pMemoryHostPointerProperties);
 #endif
 
+typedef VkResult (VKAPI_PTR *PFN_vkQueryCurrentTimestampMESA)(VkDevice device, 
uint64_t *timestamp);
+
+VKAPI_ATTR VkResult VKAPI_CALL vkQueryCurrentTimestampMESA(
+VkDevice_device,
+uint64_t*timestamp);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/Makefile.am b/src/Makefile.am
index 014ffaf3e29..74ff305d7c6 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -68,6 +68,7 @@ endif
 
 EXTRA_DIST += vulkan/registry/vk.xml
 EXTRA_DIST += vulkan/registry/vk_android_native_buffer.xml
+EXTRA_DIST += vulkan/registry/vk_mesa_query_timestamp.xml
 
 if HAVE_AMD_DRIVERS
 SUBDIRS += amd
diff --git a/src/vulkan/meson.build b/src/vulkan/meson.build
index 3908005b8a0..6ab0966b7c5 100644
--- a/src/vulkan/meson.build
+++ b/src/vulkan/meson.build
@@ -20,6 +20,7 @@
 
 vk_api_xml = files('registry/vk.xml')
 vk_android_native_buffer_xml = files('registry/vk_android_native_buffer.xml')
+vk_mesa_query_timestamp_xml = files('registry/vk_mesa_query_timestamp.xml')
 
 inc_vulkan_util = include_directories('util')
 inc_vulkan_wsi = include_directories('wsi')
diff --git a/src/vulkan/registry/vk_mesa_query_timestamp.xml 
b/src/vulkan/registry/vk_mesa_query_timestamp.xml
new file mode 100644
index 000..7fd4d974872
--- /dev/null
+++ b/src/vulkan/registry/vk_mesa_query_timestamp.xml
@@ -0,0 +1,22 @@
+
+
+
+
+VkResult 
vkQueryCurrentTimestampMESA
+VkDevice device
+uint64_t* pTimestamp
+
+
+
+
+
+
+
+
+
+
+
+
-- 
2.15.1

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[Mesa-dev] [PATCH 04/21] vulkan: Add EXT_direct_mode_display

[Keith Packard]

Add support for the EXT_direct_mode_display extension. This just
provides the vkReleaseDisplayEXT function.

Signed-off-by: Keith Packard 
---
 src/vulkan/wsi/wsi_common_display.c | 17 +
 src/vulkan/wsi/wsi_common_display.h |  5 +
 2 files changed, 22 insertions(+)

diff --git a/src/vulkan/wsi/wsi_common_display.c 
b/src/vulkan/wsi/wsi_common_display.c
index 2732b1dd721..5c123e6465e 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -1366,3 +1366,20 @@ wsi_display_finish_wsi(struct wsi_device *wsi_device,
   vk_free(alloc, wsi);
}
 }
+
+/*
+ * Implement vkReleaseDisplay
+ */
+VkResult
+wsi_release_display(VkPhysicalDevicephysical_device,
+struct wsi_device   *wsi_device,
+VkDisplayKHRdisplay)
+{
+   struct wsi_display   *wsi = (struct wsi_display *) 
wsi_device->wsi[VK_ICD_WSI_PLATFORM_DISPLAY];
+
+   if (wsi->master_fd >= 0 && wsi->master_fd != wsi->render_fd) {
+  close(wsi->master_fd);
+  wsi->master_fd = -1;
+   }
+   return VK_SUCCESS;
+}
diff --git a/src/vulkan/wsi/wsi_common_display.h 
b/src/vulkan/wsi/wsi_common_display.h
index b414a226293..5fbb6925e4a 100644
--- a/src/vulkan/wsi/wsi_common_display.h
+++ b/src/vulkan/wsi/wsi_common_display.h
@@ -69,4 +69,9 @@ wsi_create_display_surface(VkInstance instance,
const VkDisplaySurfaceCreateInfoKHR *pCreateInfo,
VkSurfaceKHR *pSurface);
 
+VkResult
+wsi_release_display(VkPhysicalDevicephysical_device,
+struct wsi_device   *wsi_device,
+VkDisplayKHRdisplay);
+
 #endif
-- 
2.15.1

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[Mesa-dev] [PATCH 14/21] anv: add VK_EXT_display_control to anv driver

[Keith Packard]

This extension provides fences and frame count information to direct
display contexts. It uses new kernel ioctls to provide 64-bits of
vblank sequence and nanosecond resolution.

Signed-off-by: Keith Packard 
---
 src/intel/vulkan/anv_extensions.py |   1 +
 src/intel/vulkan/anv_private.h |   4 ++
 src/intel/vulkan/anv_queue.c   |  59 ++---
 src/intel/vulkan/anv_wsi_display.c | 103 +
 4 files changed, 160 insertions(+), 7 deletions(-)

diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 32643e31045..1c6c4f8e27b 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -90,6 +90,7 @@ EXTENSIONS = [
 Extension('VK_EXT_debug_report',  8, True),
 Extension('VK_EXT_external_memory_dma_buf',   1, True),
 Extension('VK_EXT_display_surface_counter',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
+Extension('VK_EXT_display_control',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 ]
 
 class VkVersion:
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index d38dd9e4220..1d3e5fcd921 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1941,6 +1941,7 @@ enum anv_fence_type {
ANV_FENCE_TYPE_NONE = 0,
ANV_FENCE_TYPE_BO,
ANV_FENCE_TYPE_SYNCOBJ,
+   ANV_FENCE_TYPE_WSI,
 };
 
 enum anv_bo_fence_state {
@@ -1975,6 +1976,9 @@ struct anv_fence_impl {
 
   /** DRM syncobj handle for syncobj-based fences */
   uint32_t syncobj;
+
+  /** WSI fence */
+  struct wsi_fence *fence_wsi;
};
 };
 
diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index c6b2e01c628..d0bfad742d7 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -320,6 +320,10 @@ anv_fence_impl_cleanup(struct anv_device *device,
case ANV_FENCE_TYPE_SYNCOBJ:
   anv_gem_syncobj_destroy(device, impl->syncobj);
   return;
+
+   case ANV_FENCE_TYPE_WSI:
+  impl->fence_wsi->destroy(impl->fence_wsi);
+  return;
}
 
unreachable("Invalid fence type");
@@ -465,11 +469,32 @@ anv_wait_for_syncobj_fences(struct anv_device *device,
uint32_t *syncobjs = vk_zalloc(>alloc,
   sizeof(*syncobjs) * fenceCount, 8,
   VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
+   uint32_t syncobjCount = 0;
if (!syncobjs)
   return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
for (uint32_t i = 0; i < fenceCount; i++) {
   ANV_FROM_HANDLE(anv_fence, fence, pFences[i]);
+
+  if (fence->permanent.type == ANV_FENCE_TYPE_WSI) {
+ struct anv_fence_impl *impl = >permanent;
+ bool expired = impl->fence_wsi->wait(impl->fence_wsi, true, _timeout);
+
+ VkResult result;
+
+ if (!expired) {
+result = VK_TIMEOUT;
+goto done;
+ }
+ if (!waitAll) {
+result = VK_SUCCESS;
+goto done;
+ }
+ continue;
+  done:
+ vk_free(>alloc, syncobjs);
+ return result;
+  }
   assert(fence->permanent.type == ANV_FENCE_TYPE_SYNCOBJ);
 
   struct anv_fence_impl *impl =
@@ -477,7 +502,7 @@ anv_wait_for_syncobj_fences(struct anv_device *device,
  >temporary : >permanent;
 
   assert(impl->type == ANV_FENCE_TYPE_SYNCOBJ);
-  syncobjs[i] = impl->syncobj;
+  syncobjs[syncobjCount++] = impl->syncobj;
}
 
int64_t abs_timeout_ns = 0;
@@ -499,7 +524,7 @@ anv_wait_for_syncobj_fences(struct anv_device *device,
 */
int ret;
do {
-  ret = anv_gem_syncobj_wait(device, syncobjs, fenceCount,
+  ret = anv_gem_syncobj_wait(device, syncobjs, syncobjCount,
  abs_timeout_ns, waitAll);
} while (ret == -1 && errno == ETIME && gettime_ns() < abs_timeout_ns);
 
@@ -545,14 +570,33 @@ anv_wait_for_bo_fences(struct anv_device *device,
   for (uint32_t i = 0; i < fenceCount; i++) {
  ANV_FROM_HANDLE(anv_fence, fence, pFences[i]);
 
- /* This function assumes that all fences are BO fences and that they
-  * have no temporary state.  Since BO fences will never be exported,
-  * this should be a safe assumption.
+ /* This function assumes that all fences have no temporary
+  * state.Since BO fences will never be exported, this should be a
+  * safe assumption.
   */
- assert(fence->permanent.type == ANV_FENCE_TYPE_BO);
  assert(fence->temporary.type == ANV_FENCE_TYPE_NONE);
  struct anv_fence_impl *impl = >permanent;
 
+ /* This function assumes that all fences are either BO fences or WSI
+  * fences
+  */
+
+ if (impl->type == ANV_FENCE_TYPE_WSI) {
+bool expired = impl->fence_wsi->wait(impl->fence_wsi, true, 
timeout);
+
+if (!expired) {
+   result = 

[Mesa-dev] [PATCH 05/21] anv: Add EXT_direct_mode_display to anv driver

[Keith Packard]

Add support for the EXT_direct_mode_display extension. This just
provides the vkReleaseDisplayEXT function.

Signed-off-by: Keith Packard 
---
 src/intel/vulkan/anv_extensions.py |  1 +
 src/intel/vulkan/anv_wsi_display.c | 11 +++
 2 files changed, 12 insertions(+)

diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 112dcef5bbd..75b6bf0b41f 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -84,6 +84,7 @@ EXTENSIONS = [
 Extension('VK_KHR_xcb_surface',   6, 
'VK_USE_PLATFORM_XCB_KHR'),
 Extension('VK_KHR_xlib_surface',  6, 
'VK_USE_PLATFORM_XLIB_KHR'),
 Extension('VK_KHR_display',  23, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
+Extension('VK_EXT_direct_mode_display',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_KHX_multiview', 1, True),
 Extension('VK_EXT_debug_report',  8, True),
 Extension('VK_EXT_external_memory_dma_buf',   1, True),
diff --git a/src/intel/vulkan/anv_wsi_display.c 
b/src/intel/vulkan/anv_wsi_display.c
index 9b00d7f02e4..e6f67f7dec9 100644
--- a/src/intel/vulkan/anv_wsi_display.c
+++ b/src/intel/vulkan/anv_wsi_display.c
@@ -127,3 +127,14 @@ anv_CreateDisplayPlaneSurfaceKHR(VkInstance
_instance
 
return wsi_create_display_surface(_instance, alloc, create_info, surface);
 }
+
+VkResult
+anv_ReleaseDisplayEXT(VkPhysicalDevice physical_device,
+   VkDisplayKHR display)
+{
+   ANV_FROM_HANDLE(anv_physical_device, pdevice, physical_device);
+
+   return wsi_release_display(physical_device,
+  >wsi_device,
+  display);
+}
-- 
2.15.1

___
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[Mesa-dev] [PATCH 0/21] Add KHR_display through GOOGLE_display_timing [v2]

[Keith Packard]

Dave Airlie asked me to split these up so that the core and anv/radv
bits were all in separate patches.

There are no code changes here aside from fixing the KHR_display
version from 1 to 23. I also fixed the indentation in the changes to
the radv driver from spaces to tabs as per convention.

-keith

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[Mesa-dev] [PATCH 02/21] anv: Add KHR_display extension to anv

[Keith Packard]

This adds support for the KHR_display extension to the anv Vulkan
driver. The driver now attempts to open the master DRM node when the
KHR_display extension is requested so that the common winsys code can
perform the necessary operations.

Signed-off-by: Keith Packard 
---
 src/intel/Makefile.sources |   3 +
 src/intel/Makefile.vulkan.am   |   7 ++
 src/intel/vulkan/anv_device.c  |  18 -
 src/intel/vulkan/anv_extensions.py |   1 +
 src/intel/vulkan/anv_extensions_gen.py |   5 +-
 src/intel/vulkan/anv_wsi_display.c | 129 +
 src/intel/vulkan/meson.build   |   7 ++
 7 files changed, 165 insertions(+), 5 deletions(-)
 create mode 100644 src/intel/vulkan/anv_wsi_display.c

diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index 9595bf42582..6c142729d94 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -240,6 +240,9 @@ VULKAN_WSI_WAYLAND_FILES := \
 VULKAN_WSI_X11_FILES := \
vulkan/anv_wsi_x11.c
 
+VULKAN_WSI_DISPLAY_FILES := \
+   vulkan/anv_wsi_display.c
+
 VULKAN_GEM_FILES := \
vulkan/anv_gem.c
 
diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
index 23fa877e77d..7c428a799d7 100644
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -187,6 +187,13 @@ VULKAN_SOURCES += $(VULKAN_WSI_WAYLAND_FILES)
 VULKAN_LIB_DEPS += $(WAYLAND_CLIENT_LIBS)
 endif
 
+if HAVE_PLATFORM_DISPLAY
+VULKAN_CPPFLAGS += \
+   -DVK_USE_PLATFORM_DISPLAY_KHR
+
+VULKAN_SOURCES += $(VULKAN_WSI_DISPLAY_FILES)
+endif
+
 noinst_LTLIBRARIES += vulkan/libvulkan_common.la
 vulkan_libvulkan_common_la_SOURCES = $(VULKAN_SOURCES)
 vulkan_libvulkan_common_la_CFLAGS = $(VULKAN_CFLAGS)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 86c1bdc1d51..9614907fda3 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -277,14 +277,25 @@ anv_physical_device_init_uuids(struct anv_physical_device 
*device)
 static VkResult
 anv_physical_device_init(struct anv_physical_device *device,
  struct anv_instance *instance,
- const char *path)
+ const char *primary_path,
+ const char *render_path)
 {
VkResult result;
-   int fd;
+   int fd = -1;
+   const char *path;
 
brw_process_intel_debug_variable();
 
-   fd = open(path, O_RDWR | O_CLOEXEC);
+   if (instance->enabled_extensions.KHR_display) {
+  path = primary_path;
+  fd = open(path, O_RDWR | O_CLOEXEC);
+   }
+
+   if (fd < 0) {
+  path = render_path;
+  fd = open(path, O_RDWR | O_CLOEXEC);
+   }
+
if (fd < 0)
   return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
 
@@ -652,6 +663,7 @@ anv_enumerate_devices(struct anv_instance *instance)
 
  result = anv_physical_device_init(>physicalDevice,
 instance,
+devices[i]->nodes[DRM_NODE_PRIMARY],
 devices[i]->nodes[DRM_NODE_RENDER]);
  if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
 break;
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 581921e62a1..112dcef5bbd 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -83,6 +83,7 @@ EXTENSIONS = [
 Extension('VK_KHR_wayland_surface',   6, 
'VK_USE_PLATFORM_WAYLAND_KHR'),
 Extension('VK_KHR_xcb_surface',   6, 
'VK_USE_PLATFORM_XCB_KHR'),
 Extension('VK_KHR_xlib_surface',  6, 
'VK_USE_PLATFORM_XLIB_KHR'),
+Extension('VK_KHR_display',  23, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_KHX_multiview', 1, True),
 Extension('VK_EXT_debug_report',  8, True),
 Extension('VK_EXT_external_memory_dma_buf',   1, True),
diff --git a/src/intel/vulkan/anv_extensions_gen.py 
b/src/intel/vulkan/anv_extensions_gen.py
index 33827ecd015..84d07f9767a 100644
--- a/src/intel/vulkan/anv_extensions_gen.py
+++ b/src/intel/vulkan/anv_extensions_gen.py
@@ -113,7 +113,7 @@ _TEMPLATE_C = Template(COPYRIGHT + """
 #include "vk_util.h"
 
 /* Convert the VK_USE_PLATFORM_* defines to booleans */
-%for platform in ['ANDROID', 'WAYLAND', 'XCB', 'XLIB']:
+%for platform in ['ANDROID', 'WAYLAND', 'XCB', 'XLIB', 'DISPLAY']:
 #ifdef VK_USE_PLATFORM_${platform}_KHR
 #   undef VK_USE_PLATFORM_${platform}_KHR
 #   define VK_USE_PLATFORM_${platform}_KHR true
@@ -132,7 +132,8 @@ _TEMPLATE_C = Template(COPYRIGHT + """
 
 #define ANV_HAS_SURFACE (VK_USE_PLATFORM_WAYLAND_KHR || \\
  VK_USE_PLATFORM_XCB_KHR || \\
- VK_USE_PLATFORM_XLIB_KHR)
+ VK_USE_PLATFORM_XLIB_KHR || \\
+ VK_USE_PLATFORM_DISPLAY_KHR)
 
 const VkExtensionProperties 

[Mesa-dev] [PATCH 03/21] radv: Add KHR_display extension to radv

[Keith Packard]

This adds support for the KHR_display extension to the radv Vulkan
driver. The driver now attempts to open the master DRM node when the
KHR_display extension is requested so that the common winsys code can
perform the necessary operations.

Signed-off-by: Keith Packard 
---
 src/amd/vulkan/Makefile.am|   8 +++
 src/amd/vulkan/Makefile.sources   |   3 +
 src/amd/vulkan/meson.build|   7 ++
 src/amd/vulkan/radv_device.c  |  25 ++-
 src/amd/vulkan/radv_extensions.py |   7 +-
 src/amd/vulkan/radv_private.h |   2 +
 src/amd/vulkan/radv_wsi_display.c | 143 ++
 7 files changed, 191 insertions(+), 4 deletions(-)
 create mode 100644 src/amd/vulkan/radv_wsi_display.c

diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index 61025968942..061b8144b88 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -76,6 +76,14 @@ VULKAN_LIB_DEPS = \
$(DLOPEN_LIBS) \
-lm
 
+if HAVE_PLATFORM_DISPLAY
+AM_CPPFLAGS += \
+   -DVK_USE_PLATFORM_DISPLAY_KHR
+
+VULKAN_SOURCES += $(VULKAN_WSI_DISPLAY_FILES)
+
+endif
+
 if HAVE_PLATFORM_X11
 AM_CPPFLAGS += \
$(XCB_DRI3_CFLAGS) \
diff --git a/src/amd/vulkan/Makefile.sources b/src/amd/vulkan/Makefile.sources
index a510d88d965..618a6cdaed0 100644
--- a/src/amd/vulkan/Makefile.sources
+++ b/src/amd/vulkan/Makefile.sources
@@ -78,6 +78,9 @@ VULKAN_WSI_WAYLAND_FILES := \
 VULKAN_WSI_X11_FILES := \
radv_wsi_x11.c
 
+VULKAN_WSI_DISPLAY_FILES := \
+   radv_wsi_display.c
+
 VULKAN_GENERATED_FILES := \
radv_entrypoints.c \
radv_entrypoints.h \
diff --git a/src/amd/vulkan/meson.build b/src/amd/vulkan/meson.build
index 0a7b7c0bf3c..b7bb1075e7d 100644
--- a/src/amd/vulkan/meson.build
+++ b/src/amd/vulkan/meson.build
@@ -112,6 +112,13 @@ if with_platform_wayland
   libradv_files += files('radv_wsi_wayland.c')
 endif
 
+if with_platform_display
+  radv_flags += [
+'-DVK_USE_PLATFORM_DISPLAY_KHR',
+  ]
+  libradv_files += files('radv_wsi_display.c')
+endif
+
 libvulkan_radeon = shared_library(
   'vulkan_radeon',
   [libradv_files, radv_entrypoints, radv_extensions_c, vk_format_table_c],
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 09bb382eeb8..8ae7391c891 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -191,9 +191,26 @@ radv_physical_device_init(struct radv_physical_device 
*device,
const char *path = drm_device->nodes[DRM_NODE_RENDER];
VkResult result;
drmVersionPtr version;
-   int fd;
+   int fd = -1;
+
+   if (instance->khr_display_requested) {
+   fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | 
O_CLOEXEC);
+   if (fd >= 0) {
+   uint32_t accel_working = 0;
+   struct drm_amdgpu_info request = {
+   .return_pointer = (uintptr_t)_working,
+   .return_size = sizeof(accel_working),
+   .query = AMDGPU_INFO_ACCEL_WORKING
+   };
 
-   fd = open(path, O_RDWR | O_CLOEXEC);
+   if (drmCommandWrite(fd, DRM_AMDGPU_INFO, , 
sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
+   close(fd);
+   fd = -1;
+   }
+   }
+   }
+   if (fd < 0)
+   fd = open(path, O_RDWR | O_CLOEXEC);
if (fd < 0)
return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
 
@@ -387,6 +404,7 @@ VkResult radv_CreateInstance(
 {
struct radv_instance *instance;
VkResult result;
+   bool khr_display_requested = false;
 
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
 
@@ -411,6 +429,8 @@ VkResult radv_CreateInstance(
const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
if (!radv_instance_extension_supported(ext_name))
return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
+   if (strcmp(ext_name, VK_KHR_DISPLAY_EXTENSION_NAME) == 0)
+   khr_display_requested = true;
}
 
instance = vk_zalloc2(_alloc, pAllocator, sizeof(*instance), 8,
@@ -427,6 +447,7 @@ VkResult radv_CreateInstance(
 
instance->apiVersion = client_version;
instance->physicalDeviceCount = -1;
+   instance->khr_display_requested = khr_display_requested;
 
result = 
vk_debug_report_instance_init(>debug_report_callbacks);
if (result != VK_SUCCESS) {
diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index d761895d3a0..8a079595d40 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -81,6 +81,7 @@ EXTENSIONS = [
 Extension('VK_KHR_wayland_surface',   6, 
'VK_USE_PLATFORM_WAYLAND_KHR'),
 

[Mesa-dev] [PATCH 08/21] anv: Add EXT_acquire_xlib_display to anv driver

[Keith Packard]

This extension adds the ability to borrow an X RandR output for
temporary use directly by a Vulkan application to the anv driver.

Signed-off-by: Keith Packard 
---
 src/intel/Makefile.vulkan.am   |  7 +++
 src/intel/vulkan/anv_extensions.py |  1 +
 src/intel/vulkan/anv_extensions_gen.py | 10 +-
 src/intel/vulkan/anv_wsi_display.c | 30 ++
 src/intel/vulkan/meson.build   |  7 +++
 5 files changed, 50 insertions(+), 5 deletions(-)

diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
index 7c428a799d7..0f0d3815097 100644
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -194,6 +194,13 @@ VULKAN_CPPFLAGS += \
 VULKAN_SOURCES += $(VULKAN_WSI_DISPLAY_FILES)
 endif
 
+if HAVE_XLIB_LEASE
+VULKAN_CPPFLAGS += \
+   -DVK_USE_PLATFORM_XLIB_XRANDR_EXT \
+   $(XCB_RANDR_CFLAGS)
+VULKAN_LIB_DEPS += $(XCB_RANDR_LIBS)
+endif
+
 noinst_LTLIBRARIES += vulkan/libvulkan_common.la
 vulkan_libvulkan_common_la_SOURCES = $(VULKAN_SOURCES)
 vulkan_libvulkan_common_la_CFLAGS = $(VULKAN_CFLAGS)
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 75b6bf0b41f..47993f45d41 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -85,6 +85,7 @@ EXTENSIONS = [
 Extension('VK_KHR_xlib_surface',  6, 
'VK_USE_PLATFORM_XLIB_KHR'),
 Extension('VK_KHR_display',  23, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_direct_mode_display',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
+Extension('VK_EXT_acquire_xlib_display',  1, 
'VK_USE_PLATFORM_XLIB_XRANDR_EXT'),
 Extension('VK_KHX_multiview', 1, True),
 Extension('VK_EXT_debug_report',  8, True),
 Extension('VK_EXT_external_memory_dma_buf',   1, True),
diff --git a/src/intel/vulkan/anv_extensions_gen.py 
b/src/intel/vulkan/anv_extensions_gen.py
index 84d07f9767a..025907aff72 100644
--- a/src/intel/vulkan/anv_extensions_gen.py
+++ b/src/intel/vulkan/anv_extensions_gen.py
@@ -113,12 +113,12 @@ _TEMPLATE_C = Template(COPYRIGHT + """
 #include "vk_util.h"
 
 /* Convert the VK_USE_PLATFORM_* defines to booleans */
-%for platform in ['ANDROID', 'WAYLAND', 'XCB', 'XLIB', 'DISPLAY']:
-#ifdef VK_USE_PLATFORM_${platform}_KHR
-#   undef VK_USE_PLATFORM_${platform}_KHR
-#   define VK_USE_PLATFORM_${platform}_KHR true
+%for platform in ['ANDROID_KHR', 'WAYLAND_KHR', 'XCB_KHR', 'XLIB_KHR', 
'DISPLAY_KHR', 'XLIB_XRANDR_EXT']:
+#ifdef VK_USE_PLATFORM_${platform}
+#   undef VK_USE_PLATFORM_${platform}
+#   define VK_USE_PLATFORM_${platform} true
 #else
-#   define VK_USE_PLATFORM_${platform}_KHR false
+#   define VK_USE_PLATFORM_${platform} false
 #endif
 %endfor
 
diff --git a/src/intel/vulkan/anv_wsi_display.c 
b/src/intel/vulkan/anv_wsi_display.c
index e6f67f7dec9..e87aed49f7d 100644
--- a/src/intel/vulkan/anv_wsi_display.c
+++ b/src/intel/vulkan/anv_wsi_display.c
@@ -138,3 +138,33 @@ anv_ReleaseDisplayEXT(VkPhysicalDevice physical_device,
   >wsi_device,
   display);
 }
+
+#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT
+VkResult
+anv_AcquireXlibDisplayEXT(VkPhysicalDevice physical_device,
+   Display  *dpy,
+   VkDisplayKHR display)
+{
+   ANV_FROM_HANDLE(anv_physical_device, pdevice, physical_device);
+
+   return wsi_acquire_xlib_display(physical_device,
+   >wsi_device,
+   dpy,
+   display);
+}
+
+VkResult
+anv_GetRandROutputDisplayEXT(VkPhysicalDevice  physical_device,
+  Display   *dpy,
+  RROutput  output,
+  VkDisplayKHR  *display)
+{
+   ANV_FROM_HANDLE(anv_physical_device, pdevice, physical_device);
+
+   return wsi_get_randr_output_display(physical_device,
+   >wsi_device,
+   dpy,
+   output,
+   display);
+}
+#endif /* VK_USE_PLATFORM_XLIB_XRANDR_EXT */
diff --git a/src/intel/vulkan/meson.build b/src/intel/vulkan/meson.build
index 2e2ab8f7ecd..d3ab5ac8a64 100644
--- a/src/intel/vulkan/meson.build
+++ b/src/intel/vulkan/meson.build
@@ -178,6 +178,13 @@ if with_platform_display
   libanv_files += files('anv_wsi_display.c')
 endif
 
+if with_xlib_lease
+  anv_deps += dep_xcb_xrandr
+  anv_flags += [
+'-DVK_USE_PLATFORM_XLIB_XRANDR_EXT',
+  ]
+endif
+
 libanv_common = static_library(
   'anv_common',
   [libanv_files, anv_entrypoints, anv_extensions_c, anv_extensions_h],
-- 
2.15.1

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Re: [Mesa-dev] [PATCH 09/14] anv/cmd_buffer: Add a concept of pending load aspects

[Nanley Chery]

On Mon, Feb 05, 2018 at 02:34:58PM -0800, Jason Ekstrand wrote:
> These are the same as pending clear aspects only for the "load"
> operation.
> ---
>  src/intel/vulkan/anv_private.h |  1 +
>  src/intel/vulkan/genX_cmd_buffer.c | 22 --
>  2 files changed, 17 insertions(+), 6 deletions(-)
> 

This patch is
Reviewed-by: Nanley Chery 

> diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
> index 906c6f3..d424498 100644
> --- a/src/intel/vulkan/anv_private.h
> +++ b/src/intel/vulkan/anv_private.h
> @@ -1678,6 +1678,7 @@ struct anv_attachment_state {
>  
> VkImageLayoutcurrent_layout;
> VkImageAspectFlags   pending_clear_aspects;
> +   VkImageAspectFlags   pending_load_aspects;
> bool fast_clear;
> VkClearValue clear_value;
> bool clear_color_is_zero_one;
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
> b/src/intel/vulkan/genX_cmd_buffer.c
> index 608f5ee..2590ea3 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -1123,26 +1123,36 @@ genX(cmd_buffer_setup_attachments)(struct 
> anv_cmd_buffer *cmd_buffer,
>   struct anv_render_pass_attachment *att = >attachments[i];
>   VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
>   VkImageAspectFlags clear_aspects = 0;
> + VkImageAspectFlags load_aspects = 0;
>  
>   if (att_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
>  /* color attachment */
>  if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
> clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
> +} else if (att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
> +   load_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
>  }
>   } else {
>  /* depthstencil attachment */
> -if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
> -att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
> -   clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
> +if (att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
> +   if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
> +  clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
> +   } else if (att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
> +  load_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
> +   }
>  }
> -if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
> -att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
> -   clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
> +if (att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
> +   if (att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
> +  clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
> +   } else if (att->stencil_load_op == 
> VK_ATTACHMENT_LOAD_OP_LOAD) {
> +  load_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
> +   }
>  }
>   }
>  
>   state->attachments[i].current_layout = att->initial_layout;
>   state->attachments[i].pending_clear_aspects = clear_aspects;
> + state->attachments[i].pending_load_aspects = load_aspects;
>   if (clear_aspects)
>  state->attachments[i].clear_value = begin->pClearValues[i];
>  
> -- 
> 2.5.0.400.gff86faf
> 
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Re: [Mesa-dev] [PATCH 14/16] i965/icl: Disable HiZ surface sampling

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:14 AM PST Anuj Phogat wrote:
> On gen11+ AUX_HIZ is not a supported value for surfaces being
> sampled by the 3D sampler.
> 
> Signed-off-by: Anuj Phogat 
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index f27d559149..9c6f166677 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -1912,9 +1912,10 @@ intel_miptree_sample_with_hiz(struct brw_context *brw,
> const struct gen_device_info *devinfo = >screen->devinfo;
>  
> /* It's unclear how well supported sampling from the hiz buffer is on 
> GEN8,
> -* so keep things conservative for now and never enable it unless we're 
> SKL+.
> +* so keep things conservative for now and never enable it unless we're 
> GEN9+.
> +* Also, disable the sampling from the hiz buffer for GEN11+.
>  */
> -   if (devinfo->gen < 9) {
> +   if (devinfo->gen < 9 || devinfo->gen > 10) {
>return false;
> }

Sad to see this go :(

I think we should add a devinfo->has_aux_hiz boolean, set it on Gen9-10,
leave it false on Gen8 with this "it's unclear how well supported..."
comment, then change this code to use the flag.

That will disable it for Gen11 but gives us a bit more flexibility.


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Re: [Mesa-dev] [PATCH 10/14] anv/pass: Store usage in each subpass attachment

[Nanley Chery]

On Mon, Feb 05, 2018 at 02:34:59PM -0800, Jason Ekstrand wrote:
> This requires us to ditch the VkAttachmentReference struct in favor of
> an anv-specific struct.  However, we can now easily identify from just
> the subpass attachment what kind of an attachment it is.  This will make
> iteration over anv_subpass::attachments a little easier in some case.
> ---
>  src/intel/vulkan/anv_pass.c| 35 +++
>  src/intel/vulkan/anv_private.h | 16 +++-
>  src/intel/vulkan/genX_cmd_buffer.c |  2 +-
>  3 files changed, 39 insertions(+), 14 deletions(-)
> 

This patch is
Reviewed-by: Nanley Chery 

> diff --git a/src/intel/vulkan/anv_pass.c b/src/intel/vulkan/anv_pass.c
> index a77e52b..5b8b138 100644
> --- a/src/intel/vulkan/anv_pass.c
> +++ b/src/intel/vulkan/anv_pass.c
> @@ -65,7 +65,7 @@ VkResult anv_CreateRenderPass(
> anv_multialloc_add(, , pCreateInfo->attachmentCount);
> anv_multialloc_add(, _flushes, pCreateInfo->subpassCount + 1);
>  
> -   VkAttachmentReference *subpass_attachments;
> +   struct anv_subpass_attachment *subpass_attachments;
> uint32_t subpass_attachment_count = 0;
> for (uint32_t i = 0; i < pCreateInfo->subpassCount; i++) {
>subpass_attachment_count +=
> @@ -117,7 +117,11 @@ VkResult anv_CreateRenderPass(
>  
>   for (uint32_t j = 0; j < desc->inputAttachmentCount; j++) {
>  uint32_t a = desc->pInputAttachments[j].attachment;
> -subpass->input_attachments[j] = desc->pInputAttachments[j];
> +subpass->input_attachments[j] = (struct anv_subpass_attachment) {
> +   .usage =   VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT,
> +   .attachment =  desc->pInputAttachments[j].attachment,
> +   .layout =  desc->pInputAttachments[j].layout,
> +};
>  if (a != VK_ATTACHMENT_UNUSED) {
> has_input = true;
> pass->attachments[a].usage |= 
> VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT;
> @@ -138,7 +142,11 @@ VkResult anv_CreateRenderPass(
>  
>   for (uint32_t j = 0; j < desc->colorAttachmentCount; j++) {
>  uint32_t a = desc->pColorAttachments[j].attachment;
> -subpass->color_attachments[j] = desc->pColorAttachments[j];
> +subpass->color_attachments[j] = (struct anv_subpass_attachment) {
> +   .usage =   VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT,
> +   .attachment =  desc->pColorAttachments[j].attachment,
> +   .layout =  desc->pColorAttachments[j].layout,
> +};
>  if (a != VK_ATTACHMENT_UNUSED) {
> has_color = true;
> pass->attachments[a].usage |= 
> VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
> @@ -157,7 +165,11 @@ VkResult anv_CreateRenderPass(
>  
>   for (uint32_t j = 0; j < desc->colorAttachmentCount; j++) {
>  uint32_t a = desc->pResolveAttachments[j].attachment;
> -subpass->resolve_attachments[j] = desc->pResolveAttachments[j];
> +subpass->resolve_attachments[j] = (struct 
> anv_subpass_attachment) {
> +   .usage =   VK_IMAGE_USAGE_TRANSFER_DST_BIT,
> +   .attachment =  desc->pResolveAttachments[j].attachment,
> +   .layout =  desc->pResolveAttachments[j].layout,
> +};
>  if (a != VK_ATTACHMENT_UNUSED) {
> subpass->has_resolve = true;
> uint32_t color_att = desc->pColorAttachments[j].attachment;
> @@ -174,8 +186,12 @@ VkResult anv_CreateRenderPass(
>  
>if (desc->pDepthStencilAttachment) {
>   uint32_t a = desc->pDepthStencilAttachment->attachment;
> - *subpass_attachments++ = subpass->depth_stencil_attachment =
> -*desc->pDepthStencilAttachment;
> + subpass->depth_stencil_attachment = (struct anv_subpass_attachment) 
> {
> +.usage =   VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT,
> +.attachment =  desc->pDepthStencilAttachment->attachment,
> +.layout =  desc->pDepthStencilAttachment->layout,
> + };
> + *subpass_attachments++ = subpass->depth_stencil_attachment;
>   if (a != VK_ATTACHMENT_UNUSED) {
>  has_depth = true;
>  pass->attachments[a].usage |=
> @@ -186,8 +202,11 @@ VkResult anv_CreateRenderPass(
>*desc->pDepthStencilAttachment);
>   }
>} else {
> - subpass->depth_stencil_attachment.attachment = VK_ATTACHMENT_UNUSED;
> - subpass->depth_stencil_attachment.layout = 
> VK_IMAGE_LAYOUT_UNDEFINED;
> + subpass->depth_stencil_attachment = (struct anv_subpass_attachment) 
> {
> +.usage =   VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT,
> +.attachment =  VK_ATTACHMENT_UNUSED,
> +.layout =   VK_IMAGE_LAYOUT_UNDEFINED,
> + };
>}
> }
>  
> 

Re: [Mesa-dev] [PATCH 10/14] anv/pass: Store usage in each subpass attachment

[Nanley Chery]

On Tue, Feb 13, 2018 at 03:23:42PM -0800, Jason Ekstrand wrote:
> On Tue, Feb 13, 2018 at 3:18 PM, Nanley Chery  wrote:
> 
> > On Mon, Feb 05, 2018 at 02:34:59PM -0800, Jason Ekstrand wrote:
> > > This requires us to ditch the VkAttachmentReference struct in favor of
> > > an anv-specific struct.  However, we can now easily identify from just
> > > the subpass attachment what kind of an attachment it is.  This will make
> > > iteration over anv_subpass::attachments a little easier in some case.
> > > ---
> > >  src/intel/vulkan/anv_pass.c| 35 +++---
> > -
> > >  src/intel/vulkan/anv_private.h | 16 +++-
> > >  src/intel/vulkan/genX_cmd_buffer.c |  2 +-
> > >  3 files changed, 39 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/src/intel/vulkan/anv_pass.c b/src/intel/vulkan/anv_pass.c
> > > index a77e52b..5b8b138 100644
> > > --- a/src/intel/vulkan/anv_pass.c
> > > +++ b/src/intel/vulkan/anv_pass.c
> > > @@ -65,7 +65,7 @@ VkResult anv_CreateRenderPass(
> > > anv_multialloc_add(, , pCreateInfo->attachmentCount);
> > > anv_multialloc_add(, _flushes, pCreateInfo->subpassCount
> > + 1);
> > >
> > > -   VkAttachmentReference *subpass_attachments;
> > > +   struct anv_subpass_attachment *subpass_attachments;
> > > uint32_t subpass_attachment_count = 0;
> > > for (uint32_t i = 0; i < pCreateInfo->subpassCount; i++) {
> > >subpass_attachment_count +=
> > > @@ -117,7 +117,11 @@ VkResult anv_CreateRenderPass(
> > >
> > >   for (uint32_t j = 0; j < desc->inputAttachmentCount; j++) {
> > >  uint32_t a = desc->pInputAttachments[j].attachment;
> > > -subpass->input_attachments[j] = desc->pInputAttachments[j];
> > > +subpass->input_attachments[j] = (struct
> > anv_subpass_attachment) {
> > > +   .usage =   VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT,
> > > +   .attachment =  desc->pInputAttachments[j].attachment,
> > > +   .layout =  desc->pInputAttachments[j].layout,
> > > +};
> > >  if (a != VK_ATTACHMENT_UNUSED) {
> > > has_input = true;
> > > pass->attachments[a].usage |=
> > VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT;
> > > @@ -138,7 +142,11 @@ VkResult anv_CreateRenderPass(
> > >
> > >   for (uint32_t j = 0; j < desc->colorAttachmentCount; j++) {
> > >  uint32_t a = desc->pColorAttachments[j].attachment;
> > > -subpass->color_attachments[j] = desc->pColorAttachments[j];
> > > +subpass->color_attachments[j] = (struct
> > anv_subpass_attachment) {
> > > +   .usage =   VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT,
> > > +   .attachment =  desc->pColorAttachments[j].attachment,
> > > +   .layout =  desc->pColorAttachments[j].layout,
> > > +};
> >
> > I kind of liked reusing the VkAttachmentReference struct instead of
> > having to roll our own.
> 
> 
> I used to think that way.  However, as we extend stuff, it tends to stop
> being practical.  There are a number of cases where we started off with
> Vulkan structures and then ended up no longer using them.  This is
> especially prone to happen with extensions.
> 
> 
> > What do you think about creating helper
> > functions, like the following instead:
> >
> > static bool is_color_attachment(struct anv_subpass* subpass,
> > VkAttachmentReference* att_ref)
> > {
> >return att_ref >= subpass->color_attachments &&
> >   att_ref < subpass->color_attachments + subpass->color_count;
> > }
> >
> 
> I did exactly that in earlier versions of this series.  However, when I
> found myself trying to write an is_depth_attachment function it got messy
> and I decided it was easier to just stash the usage.  It's actually rather
> convenient.
> 

Ah, okay. Yeah, for depth we'd probably have to go so far as to inspect
the image view. 

-Nanley

> --Jason
> 
> 
> > -Nanley
> >
> >
> > >  if (a != VK_ATTACHMENT_UNUSED) {
> > > has_color = true;
> > > pass->attachments[a].usage |=
> > VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
> > > @@ -157,7 +165,11 @@ VkResult anv_CreateRenderPass(
> > >
> > >   for (uint32_t j = 0; j < desc->colorAttachmentCount; j++) {
> > >  uint32_t a = desc->pResolveAttachments[j].attachment;
> > > -subpass->resolve_attachments[j] =
> > desc->pResolveAttachments[j];
> > > +subpass->resolve_attachments[j] = (struct
> > anv_subpass_attachment) {
> > > +   .usage =   VK_IMAGE_USAGE_TRANSFER_DST_BIT,
> > > +   .attachment =  desc->pResolveAttachments[j].attachment,
> > > +   .layout =  desc->pResolveAttachments[j].layout,
> > > +};
> > >  if (a != VK_ATTACHMENT_UNUSED) {
> > > subpass->has_resolve = true;
> > > uint32_t color_att = 

Re: [Mesa-dev] [PATCH 16/16] i965/icl: Add render target flush after uploading binding table

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:16 AM PST Anuj Phogat wrote:
> From PIPE_CONTROL command description in gfxspecs:
> 
> "Whenever a Binding Table Index (BTI) used by a Render Taget Message
>  points to a different RENDER_SURFACE_STATE, SW must issue a Render
>  Target Cache Flush by enabling this bit. When render target flush
>  is set due to new association of BTI, PS Scoreboard Stall bit must
>  be set in this packet."
> 
> Fixes a fulsim error and a GPU hang described in below JIRA.
> 
> JIRA: MD5-322
> Signed-off-by: Anuj Phogat 
> ---
>  src/mesa/drivers/dri/i965/brw_binding_tables.c | 14 ++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c 
> b/src/mesa/drivers/dri/i965/brw_binding_tables.c
> index 73f5e56010..170daebc24 100644
> --- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
> +++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
> @@ -93,6 +93,20 @@ brw_upload_binding_table(struct brw_context *brw,
>OUT_BATCH(stage_state->bind_bo_offset);
>ADVANCE_BATCH();
> }
> +
> +   /* From PIPE_CONTROL command description in gfxspecs:
> +
> +  "Whenever a Binding Table Index (BTI) used by a Render Taget Message
> +   points to a different RENDER_SURFACE_STATE, SW must issue a Render
> +   Target Cache Flush by enabling this bit. When render target flush
> +   is set due to new association of BTI, PS Scoreboard Stall bit must
> +   be set in this packet."
> +   */
> +   if (devinfo->gen >= 11) {
> +  brw_emit_pipe_control_flush(brw,
> +  PIPE_CONTROL_RENDER_TARGET_FLUSH |
> +  PIPE_CONTROL_STALL_AT_SCOREBOARD);
> +   }
>  }
>  
>  /**
> 

This is overkill.  It'll do a RT flush when we change the binding
tables in any stage, for any reason.  Only the pixel shader's binding
tables have render target surfaces.  And, we might change other surfaces
(textures, UBOs, etc) without changing the render targets.

I would move this to update_renderbuffer_surfaces() in
brw_wm_surface_state.c.


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Re: [Mesa-dev] [PATCH 15/16] i965/icl: Enable float blend optimization and Wa3DStateMode

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:15 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat 
> ---
>  src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
> b/src/mesa/drivers/dri/i965/brw_state_upload.c
> index 2c8c0f4b27..86c12e4d35 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -62,7 +62,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
>  
> brw_upload_invariant_state(brw);
>  
> -   if (devinfo->gen == 10) {
> +   if (devinfo->gen == 10 || devinfo->gen == 11) {
>brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS,
>
> REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
>GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
> 

Yep, looks like the default is still off for some reason.

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 12/16] i965/icl: Update switch statements

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:12 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat 
> ---
>  src/mesa/drivers/dri/i965/brw_formatquery.c | 1 +
>  src/mesa/drivers/dri/i965/intel_screen.c| 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_formatquery.c 
> b/src/mesa/drivers/dri/i965/brw_formatquery.c
> index 4f3b9e467b..0599184802 100644
> --- a/src/mesa/drivers/dri/i965/brw_formatquery.c
> +++ b/src/mesa/drivers/dri/i965/brw_formatquery.c
> @@ -38,6 +38,7 @@ brw_query_samples_for_format(struct gl_context *ctx, GLenum 
> target,
> (void) internalFormat;
>  
> switch (devinfo->gen) {
> +   case 11:

This looks right.

> case 10:
> case 9:
>samples[0] = 16;
> diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
> b/src/mesa/drivers/dri/i965/intel_screen.c
> index a4e34e9f2c..f78328c146 100644
> --- a/src/mesa/drivers/dri/i965/intel_screen.c
> +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> @@ -2225,6 +2225,7 @@ set_max_gl_versions(struct intel_screen *screen)
> const bool has_astc = screen->devinfo.gen >= 9;
>  
> switch (screen->devinfo.gen) {
> +   case 11:
> case 10:
> case 9:
> case 8:
> 

There's some stuff missing, but this is the level of support we want to
advertise when everything's said and done, so I'm OK with this for now.

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 13/16] i965/icl: Add assertions to check dispatch mode is SIMD8

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:13 AM PST Anuj Phogat wrote:
> SIMD4x2 dispatch mode has been removed in GEN11. We're not using
> it anyways in Mesa. Adding few asserts to make it explicit.
> 
> Signed-off-by: Anuj Phogat 
> ---
>  src/intel/blorp/blorp_genX_exec.h | 4 
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 5 +
>  2 files changed, 9 insertions(+)
> 
> diff --git a/src/intel/blorp/blorp_genX_exec.h 
> b/src/intel/blorp/blorp_genX_exec.h
> index 85cd74f915..aa2baf6c6f 100644
> --- a/src/intel/blorp/blorp_genX_exec.h
> +++ b/src/intel/blorp/blorp_genX_exec.h
> @@ -572,6 +572,10 @@ blorp_emit_vs_config(struct blorp_batch *batch,
>   const struct blorp_params *params)
>  {
> struct brw_vs_prog_data *vs_prog_data = params->vs_prog_data;
> +#if GEN_GEN >= 11
> +   assert(!vs_prog_data ||
> +  vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
> +#endif

   assert(!vs_prog_data || GEN_GEN < 11 ||
  vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);

(no need for #if..#endif)

> blorp_emit(batch, GENX(3DSTATE_VS), vs) {
>if (vs_prog_data) {
> diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
> b/src/mesa/drivers/dri/i965/genX_state_upload.c
> index fa7dded8df..8f28052505 100644
> --- a/src/mesa/drivers/dri/i965/genX_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
> @@ -2044,6 +2044,8 @@ genX(upload_vs_state)(struct brw_context *brw)
>  
> assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ||
>vue_prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT);
> +   assert(devinfo->gen < 11 ||
> +  vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
>  
>  #if GEN_GEN == 6
> /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
> @@ -3961,6 +3963,9 @@ genX(upload_ds_state)(struct brw_context *brw)
> if (!tes_prog_data) {
>brw_batch_emit(brw, GENX(3DSTATE_DS), ds);
> } else {
> +  assert(devinfo->gen < 11 ||
> + vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
> +

   assert(GEN_GEN < 11 || ...)

(no need for run-time devinfo access)

With those changed,
Reviewed-by: Kenneth Graunke 

>brw_batch_emit(brw, GENX(3DSTATE_DS), ds) {
>   INIT_THREAD_DISPATCH_FIELDS(ds, Patch);
>  
> 



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Re: [Mesa-dev] [PATCH 09/16] i965/icl: Update the comment for maximum number of threads per PSD

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:09 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat 
> ---
>  src/intel/blorp/blorp_genX_exec.h | 9 +
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 9 +
>  2 files changed, 10 insertions(+), 8 deletions(-)

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 10/14] anv/pass: Store usage in each subpass attachment

[Jason Ekstrand]

On Tue, Feb 13, 2018 at 3:18 PM, Nanley Chery  wrote:

> On Mon, Feb 05, 2018 at 02:34:59PM -0800, Jason Ekstrand wrote:
> > This requires us to ditch the VkAttachmentReference struct in favor of
> > an anv-specific struct.  However, we can now easily identify from just
> > the subpass attachment what kind of an attachment it is.  This will make
> > iteration over anv_subpass::attachments a little easier in some case.
> > ---
> >  src/intel/vulkan/anv_pass.c| 35 +++---
> -
> >  src/intel/vulkan/anv_private.h | 16 +++-
> >  src/intel/vulkan/genX_cmd_buffer.c |  2 +-
> >  3 files changed, 39 insertions(+), 14 deletions(-)
> >
> > diff --git a/src/intel/vulkan/anv_pass.c b/src/intel/vulkan/anv_pass.c
> > index a77e52b..5b8b138 100644
> > --- a/src/intel/vulkan/anv_pass.c
> > +++ b/src/intel/vulkan/anv_pass.c
> > @@ -65,7 +65,7 @@ VkResult anv_CreateRenderPass(
> > anv_multialloc_add(, , pCreateInfo->attachmentCount);
> > anv_multialloc_add(, _flushes, pCreateInfo->subpassCount
> + 1);
> >
> > -   VkAttachmentReference *subpass_attachments;
> > +   struct anv_subpass_attachment *subpass_attachments;
> > uint32_t subpass_attachment_count = 0;
> > for (uint32_t i = 0; i < pCreateInfo->subpassCount; i++) {
> >subpass_attachment_count +=
> > @@ -117,7 +117,11 @@ VkResult anv_CreateRenderPass(
> >
> >   for (uint32_t j = 0; j < desc->inputAttachmentCount; j++) {
> >  uint32_t a = desc->pInputAttachments[j].attachment;
> > -subpass->input_attachments[j] = desc->pInputAttachments[j];
> > +subpass->input_attachments[j] = (struct
> anv_subpass_attachment) {
> > +   .usage =   VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT,
> > +   .attachment =  desc->pInputAttachments[j].attachment,
> > +   .layout =  desc->pInputAttachments[j].layout,
> > +};
> >  if (a != VK_ATTACHMENT_UNUSED) {
> > has_input = true;
> > pass->attachments[a].usage |=
> VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT;
> > @@ -138,7 +142,11 @@ VkResult anv_CreateRenderPass(
> >
> >   for (uint32_t j = 0; j < desc->colorAttachmentCount; j++) {
> >  uint32_t a = desc->pColorAttachments[j].attachment;
> > -subpass->color_attachments[j] = desc->pColorAttachments[j];
> > +subpass->color_attachments[j] = (struct
> anv_subpass_attachment) {
> > +   .usage =   VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT,
> > +   .attachment =  desc->pColorAttachments[j].attachment,
> > +   .layout =  desc->pColorAttachments[j].layout,
> > +};
>
> I kind of liked reusing the VkAttachmentReference struct instead of
> having to roll our own.


I used to think that way.  However, as we extend stuff, it tends to stop
being practical.  There are a number of cases where we started off with
Vulkan structures and then ended up no longer using them.  This is
especially prone to happen with extensions.


> What do you think about creating helper
> functions, like the following instead:
>
> static bool is_color_attachment(struct anv_subpass* subpass,
> VkAttachmentReference* att_ref)
> {
>return att_ref >= subpass->color_attachments &&
>   att_ref < subpass->color_attachments + subpass->color_count;
> }
>

I did exactly that in earlier versions of this series.  However, when I
found myself trying to write an is_depth_attachment function it got messy
and I decided it was easier to just stash the usage.  It's actually rather
convenient.

--Jason


> -Nanley
>
>
> >  if (a != VK_ATTACHMENT_UNUSED) {
> > has_color = true;
> > pass->attachments[a].usage |=
> VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
> > @@ -157,7 +165,11 @@ VkResult anv_CreateRenderPass(
> >
> >   for (uint32_t j = 0; j < desc->colorAttachmentCount; j++) {
> >  uint32_t a = desc->pResolveAttachments[j].attachment;
> > -subpass->resolve_attachments[j] =
> desc->pResolveAttachments[j];
> > +subpass->resolve_attachments[j] = (struct
> anv_subpass_attachment) {
> > +   .usage =   VK_IMAGE_USAGE_TRANSFER_DST_BIT,
> > +   .attachment =  desc->pResolveAttachments[j].attachment,
> > +   .layout =  desc->pResolveAttachments[j].layout,
> > +};
> >  if (a != VK_ATTACHMENT_UNUSED) {
> > subpass->has_resolve = true;
> > uint32_t color_att = desc->pColorAttachments[j].att
> achment;
> > @@ -174,8 +186,12 @@ VkResult anv_CreateRenderPass(
> >
> >if (desc->pDepthStencilAttachment) {
> >   uint32_t a = desc->pDepthStencilAttachment->attachment;
> > - *subpass_attachments++ = subpass->depth_stencil_attachment =
> > -*desc->pDepthStencilAttachment;
> > + 

Re: [Mesa-dev] [PATCH] ac: Use the renumbered const address space for LLVM 7.

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset 

On 02/13/2018 11:41 PM, Bas Nieuwenhuizen wrote:

The LLVM AMDGPU backend decided to renumber the constant address
space 
---
  src/amd/common/ac_llvm_build.h | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index e78e9589cf..a4d80cd8b0 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -35,7 +35,8 @@ extern "C" {
  #endif
  
  enum {

-   AC_CONST_ADDR_SPACE = 2, /* CONST is the only address space that 
selects SMEM loads */
+   /* CONST is the only address space that selects SMEM loads */
+   AC_CONST_ADDR_SPACE = HAVE_LLVM >= 0x700 ? 4 : 2,
AC_LOCAL_ADDR_SPACE = 3,
  };
  


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Re: [Mesa-dev] [PATCH 10/14] anv/pass: Store usage in each subpass attachment

[Nanley Chery]

On Mon, Feb 05, 2018 at 02:34:59PM -0800, Jason Ekstrand wrote:
> This requires us to ditch the VkAttachmentReference struct in favor of
> an anv-specific struct.  However, we can now easily identify from just
> the subpass attachment what kind of an attachment it is.  This will make
> iteration over anv_subpass::attachments a little easier in some case.
> ---
>  src/intel/vulkan/anv_pass.c| 35 +++
>  src/intel/vulkan/anv_private.h | 16 +++-
>  src/intel/vulkan/genX_cmd_buffer.c |  2 +-
>  3 files changed, 39 insertions(+), 14 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_pass.c b/src/intel/vulkan/anv_pass.c
> index a77e52b..5b8b138 100644
> --- a/src/intel/vulkan/anv_pass.c
> +++ b/src/intel/vulkan/anv_pass.c
> @@ -65,7 +65,7 @@ VkResult anv_CreateRenderPass(
> anv_multialloc_add(, , pCreateInfo->attachmentCount);
> anv_multialloc_add(, _flushes, pCreateInfo->subpassCount + 1);
>  
> -   VkAttachmentReference *subpass_attachments;
> +   struct anv_subpass_attachment *subpass_attachments;
> uint32_t subpass_attachment_count = 0;
> for (uint32_t i = 0; i < pCreateInfo->subpassCount; i++) {
>subpass_attachment_count +=
> @@ -117,7 +117,11 @@ VkResult anv_CreateRenderPass(
>  
>   for (uint32_t j = 0; j < desc->inputAttachmentCount; j++) {
>  uint32_t a = desc->pInputAttachments[j].attachment;
> -subpass->input_attachments[j] = desc->pInputAttachments[j];
> +subpass->input_attachments[j] = (struct anv_subpass_attachment) {
> +   .usage =   VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT,
> +   .attachment =  desc->pInputAttachments[j].attachment,
> +   .layout =  desc->pInputAttachments[j].layout,
> +};
>  if (a != VK_ATTACHMENT_UNUSED) {
> has_input = true;
> pass->attachments[a].usage |= 
> VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT;
> @@ -138,7 +142,11 @@ VkResult anv_CreateRenderPass(
>  
>   for (uint32_t j = 0; j < desc->colorAttachmentCount; j++) {
>  uint32_t a = desc->pColorAttachments[j].attachment;
> -subpass->color_attachments[j] = desc->pColorAttachments[j];
> +subpass->color_attachments[j] = (struct anv_subpass_attachment) {
> +   .usage =   VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT,
> +   .attachment =  desc->pColorAttachments[j].attachment,
> +   .layout =  desc->pColorAttachments[j].layout,
> +};

I kind of liked reusing the VkAttachmentReference struct instead of
having to roll our own. What do you think about creating helper
functions, like the following instead:

static bool is_color_attachment(struct anv_subpass* subpass,
VkAttachmentReference* att_ref)
{
   return att_ref >= subpass->color_attachments &&
  att_ref < subpass->color_attachments + subpass->color_count;
}

-Nanley


>  if (a != VK_ATTACHMENT_UNUSED) {
> has_color = true;
> pass->attachments[a].usage |= 
> VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
> @@ -157,7 +165,11 @@ VkResult anv_CreateRenderPass(
>  
>   for (uint32_t j = 0; j < desc->colorAttachmentCount; j++) {
>  uint32_t a = desc->pResolveAttachments[j].attachment;
> -subpass->resolve_attachments[j] = desc->pResolveAttachments[j];
> +subpass->resolve_attachments[j] = (struct 
> anv_subpass_attachment) {
> +   .usage =   VK_IMAGE_USAGE_TRANSFER_DST_BIT,
> +   .attachment =  desc->pResolveAttachments[j].attachment,
> +   .layout =  desc->pResolveAttachments[j].layout,
> +};
>  if (a != VK_ATTACHMENT_UNUSED) {
> subpass->has_resolve = true;
> uint32_t color_att = desc->pColorAttachments[j].attachment;
> @@ -174,8 +186,12 @@ VkResult anv_CreateRenderPass(
>  
>if (desc->pDepthStencilAttachment) {
>   uint32_t a = desc->pDepthStencilAttachment->attachment;
> - *subpass_attachments++ = subpass->depth_stencil_attachment =
> -*desc->pDepthStencilAttachment;
> + subpass->depth_stencil_attachment = (struct anv_subpass_attachment) 
> {
> +.usage =   VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT,
> +.attachment =  desc->pDepthStencilAttachment->attachment,
> +.layout =  desc->pDepthStencilAttachment->layout,
> + };
> + *subpass_attachments++ = subpass->depth_stencil_attachment;
>   if (a != VK_ATTACHMENT_UNUSED) {
>  has_depth = true;
>  pass->attachments[a].usage |=
> @@ -186,8 +202,11 @@ VkResult anv_CreateRenderPass(
>*desc->pDepthStencilAttachment);
>   }
>} else {
> - subpass->depth_stencil_attachment.attachment = VK_ATTACHMENT_UNUSED;
> - 

Re: [Mesa-dev] [PATCH 06/16] intel/icl: Do StateCacheInvalidation for indirect clear color

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:06 AM PST Anuj Phogat wrote:
> StateCacheInvalidation is required on all gen7+ platforms. We
> don't need to update this check for every new gen h/w unless
> this requirement is changed. So, dropping the check for latest
> gen h/w.
> 
> Signed-off-by: Anuj Phogat 
> ---
>  src/intel/blorp/blorp_genX_exec.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/intel/blorp/blorp_genX_exec.h 
> b/src/intel/blorp/blorp_genX_exec.h
> index 1968460be0..7420b9d91a 100644
> --- a/src/intel/blorp/blorp_genX_exec.h
> +++ b/src/intel/blorp/blorp_genX_exec.h
> @@ -1389,7 +1389,7 @@ blorp_emit_surface_states(struct blorp_batch *batch,
>}
> }
>  
> -#if GEN_GEN >= 7 && GEN_GEN <= 10
> +#if GEN_GEN >= 7
> if (has_indirect_clear_color) {
>/* Updating a surface state object may require that the state cache be
> * invalidated. From the SKL PRM, Shared Functions -> State -> State
> 

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 04/16] intel/isl/icl: Add the maximum surface size limit

[Kenneth Graunke]

On Tuesday, February 13, 2018 11:15:04 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat 
> ---
>  src/intel/isl/isl.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> index 59f512fc05..c9873d96df 100644
> --- a/src/intel/isl/isl.c
> +++ b/src/intel/isl/isl.c
> @@ -1483,7 +1483,7 @@ isl_surf_init_s(const struct isl_device *dev,
> */
>if (size > (uint64_t) 1 << 31)
>   return false;
> -   } else {
> +   } else if (ISL_DEV_GEN(dev) == 9 || ISL_DEV_GEN(dev) == 10) {

I'd just do:

   } else if (ISL_DEV_GEN(dev) < 11) {

Reviewed-by: Kenneth Graunke 

>/* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
> *"In addition to restrictions on maximum height, width, and depth,
> * surfaces are also restricted to a maximum size of 2^38 bytes.
> @@ -1492,6 +1492,10 @@ isl_surf_init_s(const struct isl_device *dev,
> */
>if (size > (uint64_t) 1 << 38)
>   return false;
> +   } else {
> +  /* gen11+ platforms raised this limit to 2^44 bytes. */
> +  if (size > (uint64_t) 1 << 44)
> + return false;
> }
>  
> *surf = (struct isl_surf) {
> 



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Re: [Mesa-dev] [PATCH 2/3] anv/gen10: Remove warning message.

[Kenneth Graunke]

On Tuesday, February 13, 2018 1:51:54 PM PST Rafael Antognolli wrote:
> Gen10 seems pretty stable so far, remove "alpha support" message.
> 
> Signed-off-by: Rafael Antognolli 
> Cc: Jason Ekstrand 
> Cc: "18.0" mesa-sta...@lists.freedesktop.org
> ---
>  src/intel/vulkan/anv_device.c | 8 +++-
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index 86c1bdc1d51..7390fc3600b 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -312,11 +312,9 @@ anv_physical_device_init(struct anv_physical_device 
> *device,
>intel_logw("Ivy Bridge Vulkan support is incomplete");
> } else if (device->info.gen == 7 && device->info.is_baytrail) {
>intel_logw("Bay Trail Vulkan support is incomplete");
> -   } else if (device->info.gen >= 8 && device->info.gen <= 9) {
> -  /* Broadwell, Cherryview, Skylake, Broxton, Kabylake, Coffelake is as
> -   * fully supported as anything */
> -   } else if (device->info.gen == 10) {
> -  intel_logw("Cannonlake Vulkan support is alpha");
> +   } else if (device->info.gen >= 8 && device->info.gen <= 10) {
> +  /* Broadwell, Cherryview, Skylake, Broxton, Kabylake, Coffelake,
> +   * Cannonlake is as fully supported as anything */

Getting a pretty huge list of codenames here, and Coffee was misspelled.
I'd just change it to /* Gen8-10 fully supported */ or some such.

Series is:
Reviewed-by: Kenneth Graunke 

> } else {
>result = vk_errorf(device->instance, device,
>   VK_ERROR_INCOMPATIBLE_DRIVER,
> 



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Re: [Mesa-dev] [PATCH 08/14] anv/cmd_buffer: Iterate all subpass attachments when clearing

[Jason Ekstrand]

On Tue, Feb 13, 2018 at 11:29 AM, Nanley Chery 
wrote:

> On Mon, Feb 05, 2018 at 02:34:57PM -0800, Jason Ekstrand wrote:
> > This unifies things a bit because we now handle depth and stencil at the
> > same time.  It also ensures that clears happen for input attachments.
>
> As we discussed in another patch, clears are always guaranteed to happen
> for input attachments on LOAD_OP_CLEAR, so we can get rid of that last
> sentence.


Done.


> With that change, this patch is
> Reviewed-by: Nanley Chery 
>
> > ---
> >  src/intel/vulkan/genX_cmd_buffer.c | 77 --
> 
> >  1 file changed, 32 insertions(+), 45 deletions(-)
> >
> > diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer.c
> > index ab79fbf..608f5ee 100644
> > --- a/src/intel/vulkan/genX_cmd_buffer.c
> > +++ b/src/intel/vulkan/genX_cmd_buffer.c
> > @@ -3524,66 +3524,51 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer
> *cmd_buffer,
> >
> > VkRect2D render_area = cmd_buffer->state.render_area;
> > struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
> > -   for (uint32_t i = 0; i < subpass->color_count; ++i) {
> > -  const uint32_t a = subpass->color_attachments[i].attachment;
> > +
> > +   for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
> > +  const uint32_t a = subpass->attachments[i].attachment;
> >if (a == VK_ATTACHMENT_UNUSED)
> >   continue;
> >
> >assert(a < cmd_state->pass->attachment_count);
> >struct anv_attachment_state *att_state =
> _state->attachments[a];
> >
> > -  if (!att_state->pending_clear_aspects)
> > - continue;
> > -
> > -  assert(att_state->pending_clear_aspects ==
> VK_IMAGE_ASPECT_COLOR_BIT);
> > -
> >struct anv_image_view *iview = fb->attachments[a];
> >const struct anv_image *image = iview->image;
> >
> > -  /* Multi-planar images are not supported as attachments */
> > -  assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
> > -  assert(image->n_planes == 1);
> > -
> > -  uint32_t base_layer = iview->planes[0].isl.base_array_layer;
> > -  uint32_t layer_count = fb->layers;
> > +  if (att_state->pending_clear_aspects &
> VK_IMAGE_ASPECT_COLOR_BIT) {
> > + assert(att_state->pending_clear_aspects ==
> VK_IMAGE_ASPECT_COLOR_BIT);
> >
> > -  if (att_state->fast_clear) {
> > - /* We only support fast-clears on the first layer */
> > - assert(iview->planes[0].isl.base_level == 0);
> > - assert(iview->planes[0].isl.base_array_layer == 0);
> > -
> > - anv_image_ccs_op(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
> > -  0, 0, 1, ISL_AUX_OP_FAST_CLEAR, false);
> > - base_layer++;
> > - layer_count--;
> > -  }
> > -
> > -  if (layer_count > 0) {
> > + /* Multi-planar images are not supported as attachments */
> > + assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
> >   assert(image->n_planes == 1);
> > - anv_image_clear_color(cmd_buffer, image,
> VK_IMAGE_ASPECT_COLOR_BIT,
> > -   att_state->aux_usage,
> > -   iview->planes[0].isl.format,
> > -   iview->planes[0].isl.swizzle,
> > -   iview->planes[0].isl.base_level,
> > -   base_layer, layer_count, render_area,
> > -   vk_to_isl_color(att_state->
> clear_value.color));
> > -  }
> > -
> > -  att_state->pending_clear_aspects = 0;
> > -   }
> >
> > -   if (subpass->depth_stencil_attachment.attachment !=
> VK_ATTACHMENT_UNUSED) {
> > -  const uint32_t a = subpass->depth_stencil_attachment.attachment;
> > + uint32_t base_layer = iview->planes[0].isl.base_array_layer;
> > + uint32_t layer_count = fb->layers;
> >
> > -  assert(a < cmd_state->pass->attachment_count);
> > -  struct anv_attachment_state *att_state =
> _state->attachments[a];
> > -  struct anv_image_view *iview = fb->attachments[a];
> > -  const struct anv_image *image = iview->image;
> > + if (att_state->fast_clear) {
> > +/* We only support fast-clears on the first layer */
> > +assert(iview->planes[0].isl.base_level == 0);
> > +assert(iview->planes[0].isl.base_array_layer == 0);
> >
> > -  assert(image->aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
> > -   VK_IMAGE_ASPECT_STENCIL_BIT));
> > +anv_image_ccs_op(cmd_buffer, image,
> VK_IMAGE_ASPECT_COLOR_BIT,
> > + 0, 0, 1, ISL_AUX_OP_FAST_CLEAR, false);
> > +base_layer++;
> > +layer_count--;
> > + }
> >
> > -  if (att_state->pending_clear_aspects) {
> > + if (layer_count > 0) {
> > +assert(image->n_planes == 1);
> > +

Re: [Mesa-dev] [PATCH] swr: bump minimum supported LLVM version to 4.0

[Kyriazis, George]

> On Feb 13, 2018, at 4:54 PM, Dylan Baker  wrote:
> 
> Quoting Andres Gomez (2018-02-13 14:42:57)
> [snip]
>> 
>> -if with_amd_vk or with_gallium_radeonsi
>> +if with_amd_vk or with_gallium_radeonsi or with_gallium_swr
>>   _llvm_version = '>= 4.0.0'
>> -elif with_gallium_opencl or with_gallium_swr or with_gallium_r600
>> +elif with_gallium_opencl or with_gallium_r600
> 
> It's really up to the SWR team what they want to do here, but Meson doesn't
> generate the headers as part of building a dist tarball, it generates them at
> build time whether in git or in a tarball. And doesn't use the ones generated 
> by
> autotools, so it *should* be possible to leave this as 3.9.0 if they like.
> 
It makes sense to be consistent across the board.  Once we switch to 4.0.0, it 
could be confusing to have some aspects of the build still be doable with 
pre-4.0.0 llvm.

> As long as either Tim or George gives an ack or review,
> Reviewed-by: Dylan Baker 



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[Mesa-dev] [PATCH] i965: Add gl_state_index casts for PATCH_VERTICES_IN

[Jason Ekstrand]

This fixes the build in clang
---
 src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp 
b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
index 10a4ff4..69da83a 100644
--- a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
+++ b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
@@ -254,7 +254,8 @@ brw_nir_lower_patch_vertices_in_to_uniform(nir_shader *nir)
   gl_state_index16 tokens[STATE_LENGTH] = {
  STATE_INTERNAL,
  nir->info.stage == MESA_SHADER_TESS_CTRL ?
-STATE_TCS_PATCH_VERTICES_IN : STATE_TES_PATCH_VERTICES_IN,
+(gl_state_index16)STATE_TCS_PATCH_VERTICES_IN :
+(gl_state_index16)STATE_TES_PATCH_VERTICES_IN,
   };
   var->num_state_slots = 1;
   var->state_slots =
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH] swr: bump minimum supported LLVM version to 4.0

[Kyriazis, George]

I am not an expert on all the changes needed for travis and packaging, but the 
swr changes look good.

Reviewed-by: George Kyriazis 
>

On Feb 13, 2018, at 4:42 PM, Andres Gomez 
> wrote:

Since radv and radeonsi removed support for LLVM 3.9 the distcheck
target got broken because SWR distribution needed 3.9.x.

After checking with George Kyriazis, SWR is OK with moving to LLVM 4.0
and above, which will solve this problem.

Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
Cc: George Kyriazis 
>
Cc: Tim Rowley >
Cc: Emil Velikov >
Cc: Dylan Baker >
Cc: Eric Engestrom >
Signed-off-by: Andres Gomez >
---
.travis.yml | 15 ++-
configure.ac|  6 +++---
meson.build |  4 ++--
src/gallium/drivers/swr/Makefile.am |  2 +-
src/gallium/drivers/swr/SConscript  |  4 ++--
5 files changed, 14 insertions(+), 17 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 3651d00169f..0ec08e5bff7 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -90,12 +90,10 @@ matrix:
- BUILD=make
- MAKEFLAGS="-j4"
- MAKE_CHECK_COMMAND="true"
-- LLVM_VERSION=3.9
+- LLVM_VERSION=4.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
- OVERRIDE_CC="gcc-4.8"
- OVERRIDE_CXX="g++-4.8"
-# New binutils linker is required for llvm-3.9
-- OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine 
--disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio 
--disable-gallium-osmesa"
@@ -105,13 +103,12 @@ matrix:
  addons:
apt:
  sources:
-- llvm-toolchain-trusty-3.9
+- llvm-toolchain-trusty-4.0
  packages:
-- binutils-2.26
# LLVM packaging is broken and misses these dependencies
- libedit-dev
# From sources above
-- llvm-3.9-dev
+- llvm-4.0-dev
# Common
- xz-utils
- x11proto-xf86vidmode-dev
@@ -400,7 +397,7 @@ matrix:
- BUILD=scons
- SCONSFLAGS="-j4"
- SCONS_TARGET="swr=1"
-- LLVM_VERSION=3.9
+- LLVM_VERSION=4.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
# Keep it symmetrical to the make build. There's no actual SWR, yet.
- SCONS_CHECK_COMMAND="true"
@@ -409,13 +406,13 @@ matrix:
  addons:
apt:
  sources:
-- llvm-toolchain-trusty-3.9
+- llvm-toolchain-trusty-4.0
  packages:
- scons
# LLVM packaging is broken and misses these dependencies
- libedit-dev
# From sources above
-- llvm-3.9-dev
+- llvm-4.0-dev
# Common
- xz-utils
- x11proto-xf86vidmode-dev
diff --git a/configure.ac b/configure.ac
index 8ed606c7694..7fff725954d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -105,7 +105,7 @@ LLVM_REQUIRED_OPENCL=3.9.0
LLVM_REQUIRED_R600=3.9.0
LLVM_REQUIRED_RADEONSI=4.0.0
LLVM_REQUIRED_RADV=4.0.0
-LLVM_REQUIRED_SWR=3.9.0
+LLVM_REQUIRED_SWR=4.0.0

dnl Check for progs
AC_PROG_CPP
@@ -2695,8 +2695,8 @@ if test -n "$with_gallium_drivers"; then
fi

# XXX: Keep in sync with LLVM_REQUIRED_SWR
-AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x3.9.0 -a \
-  "x$LLVM_VERSION" != x3.9.1)
+AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x4.0.0 -a \
+  "x$LLVM_VERSION" != x4.0.1)

if test "x$enable_llvm" = "xyes" -a "$with_gallium_drivers"; then
llvm_require_version $LLVM_REQUIRED_GALLIUM "gallium"
diff --git a/meson.build b/meson.build
index b39e2f8ab96..96e44459465 100644
--- a/meson.build
+++ b/meson.build
@@ -1011,9 +1011,9 @@ if with_gallium_opencl
  # TODO: optional modules
endif

-if with_amd_vk or with_gallium_radeonsi
+if with_amd_vk or with_gallium_radeonsi or with_gallium_swr
  _llvm_version = '>= 4.0.0'
-elif with_gallium_opencl or with_gallium_swr or with_gallium_r600
+elif with_gallium_opencl or with_gallium_r600
  _llvm_version = '>= 3.9.0'
else
  _llvm_version = '>= 3.3.0'
diff --git a/src/gallium/drivers/swr/Makefile.am 
b/src/gallium/drivers/swr/Makefile.am
index 2bc129429c6..3ee79f7be25 100644
--- a/src/gallium/drivers/swr/Makefile.am
+++ b/src/gallium/drivers/swr/Makefile.am
@@ -352,7 +352,7 @@ include 

Re: [Mesa-dev] [PATCH] swr: bump minimum supported LLVM version to 4.0

[Dylan Baker]

Quoting Andres Gomez (2018-02-13 14:42:57)
[snip]
>  
> -if with_amd_vk or with_gallium_radeonsi
> +if with_amd_vk or with_gallium_radeonsi or with_gallium_swr
>_llvm_version = '>= 4.0.0'
> -elif with_gallium_opencl or with_gallium_swr or with_gallium_r600
> +elif with_gallium_opencl or with_gallium_r600

It's really up to the SWR team what they want to do here, but Meson doesn't
generate the headers as part of building a dist tarball, it generates them at
build time whether in git or in a tarball. And doesn't use the ones generated by
autotools, so it *should* be possible to leave this as 3.9.0 if they like. 

As long as either Tim or George gives an ack or review,
Reviewed-by: Dylan Baker 


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Re: [Mesa-dev] [PATCH] travis: radeonsi and radv need LLVM 4.0

[Andres Gomez]

On Tue, 2018-02-06 at 19:23 +, Kyriazis, George wrote:
> SWR is OK with moving to LLVM 4.0 and above.
> 
> Just to clarify: This goes to master, which means mesa 18.0 is not
> affected, just 18.1 and later.  Correct?

That is my understanding.

3bf1e036e8a, which is the one triggering this change, is not in the
18.0 branch and, AFAIU, it shouldn't get in.

> Thanks,

Thanks to you ☺

> 
> George
> 
> > On Feb 6, 2018, at 11:07 AM, Kyriazis, George  > l.com> wrote:
> > 
> > As far as SWR is concerned, we’ll have to ask our customers.  Will
> > respond shortly.
> > 
> > Thanks,
> > 
> > George
> > 
> > > On Feb 6, 2018, at 9:42 AM, Andres Gomez 
> > > wrote:
> > > 
> > > Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
> > > Cc: Marek Olšák 
> > > Cc: Emil Velikov 
> > > Cc: Jan Vesely 
> > > Signed-off-by: Andres Gomez 
> > > ---
> > > 
> > > Additionally, AMD's support removal for LLVM 3.9 has also
> > > affected the
> > > distcheck target.
> > > 
> > > Unfortunately, SWR distribution needs 3.9.x, therefore, we cannot
> > > simply use LLVM 4.0 to generate the distribution tarball.
> > > 
> > > Either SWR upgrades its minimal dependency to LLVM 4.0 or we find
> > > a
> > > way of instructing distcheck so it would use LLVM 3.9 for the
> > > tarball
> > > generation and LLVM 4.0 for the check stage of the distcheck ...
> > > 
> > > .travis.yml | 46 --
> > > 1 file changed, 36 insertions(+), 10 deletions(-)
> > > 
> > > diff --git a/.travis.yml b/.travis.yml
> > > index 0156eefb7ad..3651d00169f 100644
> > > --- a/.travis.yml
> > > +++ b/.travis.yml
> > > @@ -37,12 +37,12 @@ matrix:
> > >  addons:
> > >apt:
> > >  sources:
> > > -- llvm-toolchain-trusty-3.9
> > > +- llvm-toolchain-trusty-4.0
> > >  packages:
> > ># LLVM packaging is broken and misses these
> > > dependencies
> > >- libedit-dev
> > ># From sources above
> > > -- llvm-3.9-dev
> > > +- llvm-4.0-dev
> > ># Common
> > >- xz-utils
> > >- libexpat1-dev
> > > @@ -119,6 +119,35 @@ matrix:
> > >- libx11-xcb-dev
> > >- libelf-dev
> > >- libunwind8-dev
> > > +- env:
> > > +- LABEL="make Gallium Drivers RadeonSI"
> > > +- BUILD=make
> > > +- MAKEFLAGS="-j4"
> > > +- MAKE_CHECK_COMMAND="true"
> > > +- LLVM_VERSION=4.0
> > > +- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
> > > +- DRI_LOADERS="--disable-glx --disable-gbm --disable-
> > > egl"
> > > +- DRI_DRIVERS=""
> > > +- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa 
> > > --disable-nine --disable-xvmc --disable-vdpau --disable-va --
> > > disable-omx-bellagio --disable-gallium-osmesa"
> > > +- GALLIUM_DRIVERS="radeonsi"
> > > +- VULKAN_DRIVERS=""
> > > +- LIBUNWIND_FLAGS="--enable-libunwind"
> > > +  addons:
> > > +apt:
> > > +  sources:
> > > +- llvm-toolchain-trusty-4.0
> > > +  packages:
> > > +# LLVM packaging is broken and misses these
> > > dependencies
> > > +- libedit-dev
> > > +# From sources above
> > > +- llvm-4.0-dev
> > > +# Common
> > > +- xz-utils
> > > +- x11proto-xf86vidmode-dev
> > > +- libexpat1-dev
> > > +- libx11-xcb-dev
> > > +- libelf-dev
> > > +- libunwind8-dev
> > >- env:
> > >- LABEL="make Gallium Drivers Other"
> > >- BUILD=make
> > > @@ -131,7 +160,7 @@ matrix:
> > >- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
> > >- DRI_DRIVERS=""
> > >- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa
> > > --disable-nine --disable-xvmc --disable-vdpau --disable-va --
> > > disable-omx-bellagio --disable-gallium-osmesa"
> > > --
> > > GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,radeonsi,freedreno,
> > > svga,swrast,vc4,virgl,etnaviv,imx"
> > > +-
> > > GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,freedreno,svga,swra
> > > st,vc4,virgl,etnaviv,imx"
> > >- VULKAN_DRIVERS=""
> > >- LIBUNWIND_FLAGS="--enable-libunwind"
> > >  addons:
> > > @@ -166,7 +195,7 @@ matrix:
> > >- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
> > >- DRI_DRIVERS=""
> > >- GALLIUM_ST="--disable-dri --enable-opencl --enable-
> > > opencl-icd --enable-llvm --disable-xa --disable-nine --disable-
> > > xvmc --disable-vdpau --disable-va --disable-omx-bellagio --
> > > disable-gallium-osmesa"
> > > -- GALLIUM_DRIVERS="r600,radeonsi"
> > > +- GALLIUM_DRIVERS="r600"
> > >- VULKAN_DRIVERS=""
> > >- 

Re: [Mesa-dev] [PATCH] i965: Add ICL to test_eu_validate.cpp

[Anuj Phogat]

Sent this patch to ML by mistake :(. Reviewers can ignore this one for now.
Matt can send it out later with rest of his compiler changes.

On Tue, Feb 13, 2018 at 2:41 PM, Anuj Phogat  wrote:
> From: Matt Turner 
>
> ---
>  src/intel/compiler/test_eu_validate.cpp | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/intel/compiler/test_eu_validate.cpp 
> b/src/intel/compiler/test_eu_validate.cpp
> index f6c2b35625..d987311ef8 100644
> --- a/src/intel/compiler/test_eu_validate.cpp
> +++ b/src/intel/compiler/test_eu_validate.cpp
> @@ -56,6 +56,7 @@ static const struct gen_info {
> { "glk", 9, IS_GLK },
> { "cfl", 9, IS_CFL },
> { "cnl", 10 },
> +   { "icl", 11 },
>  };
>
>  class validation_test: public ::testing::TestWithParam {
> --
> 2.13.6
>
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[Mesa-dev] [PATCH 13/31] swr/rast: Cull prims when all verts have negative clip distances

[George Kyriazis]

Performance optimization, and fixes some clipping issues.
---
 src/gallium/drivers/swr/rasterizer/core/clip.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/swr/rasterizer/core/clip.h 
b/src/gallium/drivers/swr/rasterizer/core/clip.h
index 1d336b6..5193672 100644
--- a/src/gallium/drivers/swr/rasterizer/core/clip.h
+++ b/src/gallium/drivers/swr/rasterizer/core/clip.h
@@ -417,6 +417,7 @@ public:
 uint32_t slot = index >> 2;
 uint32_t component = index & 0x3;
 
+typename SIMD_T::Float vCullMaskElem = SIMD_T::set1_ps(-1.0f);
 for (uint32_t e = 0; e < NumVertsPerPrim; ++e)
 {
 typename SIMD_T::Float vClipComp;
@@ -430,8 +431,11 @@ public:
 }
 
 typename SIMD_T::Float vClip = SIMD_T::template 
cmp_ps(vClipComp, vClipComp);
+typename SIMD_T::Float vCull = SIMD_T::template 
cmp_ps(SIMD_T::setzero_ps(), vClipComp);
+vCullMaskElem = SIMD_T::and_ps(vCullMaskElem, vCull);
 vClipCullMask = SIMD_T::or_ps(vClipCullMask, vClip);
 }
+vClipCullMask = SIMD_T::or_ps(vClipCullMask, vCullMaskElem);
 }
 
 return SIMD_T::movemask_ps(vClipCullMask);
-- 
2.7.4

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[Mesa-dev] [PATCH 26/31] swr/rast: Convert C Sampler intrinsics

[George Kyriazis]

Convert portions of the C sampler to the rasty SIMD lib.
---
 src/gallium/drivers/swr/rasterizer/common/intrin.h   |  3 +++
 .../drivers/swr/rasterizer/common/simdlib_128_avx.inl| 16 
 2 files changed, 19 insertions(+)

diff --git a/src/gallium/drivers/swr/rasterizer/common/intrin.h 
b/src/gallium/drivers/swr/rasterizer/common/intrin.h
index 33d37e3..59d66bc 100644
--- a/src/gallium/drivers/swr/rasterizer/common/intrin.h
+++ b/src/gallium/drivers/swr/rasterizer/common/intrin.h
@@ -26,7 +26,10 @@
 
 #include "os.h"
 
+#if !defined(SIMD_ARCH)
 #define SIMD_ARCH KNOB_ARCH
+#endif 
+
 #include "simdlib_types.hpp"
 
 typedef SIMDImpl::SIMD128Impl::Float  simd4scalar;
diff --git a/src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx.inl 
b/src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx.inl
index 7232791..56f60a8 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx.inl
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx.inl
@@ -174,6 +174,7 @@ SIMD_IWRAPPER_2_(xor_si, _mm_xor_si128);// return a 
^ b   (int)
 // Shift operations
 //---
 SIMD_IWRAPPER_1I(slli_epi32);   // return a << ImmT
+SIMD_IWRAPPER_1I(slli_epi64);   // return a << ImmT
 
 static SIMDINLINE Integer SIMDCALL sllv_epi32(Integer vA, Integer vB) // 
return a << b  (uint32)
 {
@@ -205,6 +206,11 @@ SIMD_IWRAPPER_1I(srai_epi32);   // return a >> 
ImmT   (int32)
 SIMD_IWRAPPER_1I(srli_epi32);   // return a >> ImmT   (uint32)
 SIMD_IWRAPPER_1I_(srli_si, _mm_srli_si128); // return a >> (ImmT*8) (uint)
 
+static SIMDINLINE Integer SIMDCALL srli_epi64(Integer a, uint32_t n)
+{
+return _mm_srli_epi64(a, n);
+}
+
 template  // same as srli_si, but with 
Float cast to int
 static SIMDINLINE Float SIMDCALL srlisi_ps(Float a)
 {
@@ -272,6 +278,16 @@ static SIMDINLINE Float SIMDCALL cvtepi32_ps(Integer a) // 
return (float)a(i
 return _mm_cvtepi32_ps(a);
 }
 
+static SIMDINLINE int32_t SIMDCALL cvtsi128_si32(Integer a) // return a.v[0]
+{
+return _mm_cvtsi128_si32(a);
+}
+
+static SIMDINLINE Integer SIMDCALL cvtsi32_si128(int32_t n) // return a[0] = 
n, a[1]...a[3] = 0
+{
+return _mm_cvtsi32_si128(n);
+}
+
 SIMD_IWRAPPER_1(cvtepu8_epi16); // return (int16)a(uint8 --> int16)
 SIMD_IWRAPPER_1(cvtepu8_epi32); // return (int32)a(uint8 --> int32)
 SIMD_IWRAPPER_1(cvtepu16_epi32);// return (int32)a(uint16 --> int32)
-- 
2.7.4

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[Mesa-dev] [PATCH 31/31] swr/rast: blend_epi32() should return Integer, not Float

[George Kyriazis]

fix gcc8 compiler error for KNL.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105029
---
 src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl 
b/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl
index 8de62f2..f3a58f9 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl
@@ -366,7 +366,7 @@ static SIMDINLINE Float blend_ps(Float a, Float b) // 
return ImmT ? b : a  (floa
 }
 
 template 
-static SIMDINLINE Float blend_epi32(Integer a, Integer b) // return ImmT ? b : 
a  (int32)
+static SIMDINLINE Integer blend_epi32(Integer a, Integer b) // return ImmT ? b 
: a  (int32)
 {
 return _mm512_mask_blend_epi32(__mmask16(ImmT), a, b);
 }
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 07/14] anv/cmd_buffer: Decide whether or not to HiZ clear up-front

[Jason Ekstrand]

On Tue, Feb 13, 2018 at 11:02 AM, Nanley Chery 
wrote:

> On Mon, Feb 05, 2018 at 02:34:56PM -0800, Jason Ekstrand wrote:
> > This moves the decision out of begin_subpass and into BeginRenderPass
> > like the decision for color clears.  We use a similar name for the
> > function for depth/stencil as for color even though no aux usage is
> > really getting computed.
> > ---
> >  src/intel/vulkan/genX_cmd_buffer.c | 84 +++---
> 
> >  1 file changed, 50 insertions(+), 34 deletions(-)
> >
> > diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer.c
> > index 21fdc6b..ab79fbf 100644
> > --- a/src/intel/vulkan/genX_cmd_buffer.c
> > +++ b/src/intel/vulkan/genX_cmd_buffer.c
> > @@ -350,6 +350,52 @@ color_attachment_compute_aux_usage(struct
> anv_device * device,
> > }
> >  }
> >
> > +static void
> > +depth_stencil_attachment_compute_aux_usage(struct anv_device *device,
> > +   struct anv_cmd_state
> *cmd_state,
> > +   uint32_t att, VkRect2D
> render_area)
> > +{
> > +   struct anv_attachment_state *att_state =
> _state->attachments[att];
> > +   struct anv_image_view *iview = cmd_state->framebuffer->
> attachments[att];
> > +
> > +   /* These will be initialized after the first subpass transition. */
> > +   att_state->aux_usage = ISL_AUX_USAGE_NONE;
> > +   att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
> > +
> > +   if (att_state->aux_usage != ISL_AUX_USAGE_HIZ) {
>
> We set this to NONE 3 lines above. I think you meant to have your
> variable be: iview->image->planes[plane].aux_usage ?
>

Yup.  You're right.  Fixed locally.

This means I accidentally disabled HiZ clears entirely. :(  This is going
to need another jenkins run.


> This is a nice cleanup. With the above fixed, this patch is
> Reviewed-by: Nanley Chery 
>
>
> > +  att_state->fast_clear = false;
> > +  return;
> > +   } else if (!(att_state->pending_clear_aspects &
> VK_IMAGE_ASPECT_DEPTH_BIT)) {
> > +  /* If we're just clearing stencil, we can always HiZ clear */
> > +  att_state->fast_clear = true;
> > +  return;
> > +   }
> > +
> > +   if (!blorp_can_hiz_clear_depth(GEN_GEN,
> > +  iview->planes[0].isl.format,
> > +  iview->image->samples,
> > +  render_area.offset.x,
> > +  render_area.offset.y,
> > +  render_area.offset.x +
> > +  render_area.extent.width,
> > +  render_area.offset.y +
> > +  render_area.extent.height)) {
> > +  att_state->fast_clear = false;
> > +   } else if (att_state->clear_value.depthStencil.depth !=
> ANV_HZ_FC_VAL) {
> > +  att_state->fast_clear = false;
> > +   } else if (GEN_GEN == 8 &&
> > +  anv_can_sample_with_hiz(>info, iview->image)) {
> > +  /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
> > +   * fast-cleared portion of a HiZ buffer. Testing has revealed
> that Gen8
> > +   * only supports returning 0.0f. Gens prior to gen8 do not
> support this
> > +   * feature at all.
> > +   */
> > +  att_state->fast_clear = false;
> > +   } else {
> > +  att_state->fast_clear = true;
> > +   }
> > +}
> > +
> >  static bool
> >  need_input_attachment_state(const struct anv_render_pass_attachment
> *att)
> >  {
> > @@ -1125,12 +1171,9 @@ genX(cmd_buffer_setup_attachments)(struct
> anv_cmd_buffer *cmd_buffer,
> >  add_image_view_relocs(cmd_buffer, iview, 0,
> >state->attachments[i].color);
> >   } else {
> > -/* This field will be initialized after the first subpass
> > - * transition.
> > - */
> > -state->attachments[i].aux_usage = ISL_AUX_USAGE_NONE;
> > -
> > -state->attachments[i].input_aux_usage = ISL_AUX_USAGE_NONE;
> > +depth_stencil_attachment_compute_aux_usage(cmd_buffer->
> device,
> > +   state, i,
> > +
>  begin->renderArea);
> >   }
> >
> >   if (need_input_attachment_state(>attachments[i])) {
> > @@ -3541,34 +3584,7 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer
> *cmd_buffer,
> > VK_IMAGE_ASPECT_STENCIL_BIT));
> >
> >if (att_state->pending_clear_aspects) {
> > - bool clear_with_hiz = att_state->aux_usage ==
> ISL_AUX_USAGE_HIZ;
> > - if (clear_with_hiz &&
> > - (att_state->pending_clear_aspects &
> VK_IMAGE_ASPECT_DEPTH_BIT)) {
> > -if (!blorp_can_hiz_clear_depth(GEN_GEN,
> > -   iview->planes[0].isl.format,
> > -   

[Mesa-dev] [PATCH] swr: bump minimum supported LLVM version to 4.0

[Andres Gomez]

Since radv and radeonsi removed support for LLVM 3.9 the distcheck
target got broken because SWR distribution needed 3.9.x.

After checking with George Kyriazis, SWR is OK with moving to LLVM 4.0
and above, which will solve this problem.

Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
Cc: George Kyriazis 
Cc: Tim Rowley 
Cc: Emil Velikov 
Cc: Dylan Baker 
Cc: Eric Engestrom 
Signed-off-by: Andres Gomez 
---
 .travis.yml | 15 ++-
 configure.ac|  6 +++---
 meson.build |  4 ++--
 src/gallium/drivers/swr/Makefile.am |  2 +-
 src/gallium/drivers/swr/SConscript  |  4 ++--
 5 files changed, 14 insertions(+), 17 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 3651d00169f..0ec08e5bff7 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -90,12 +90,10 @@ matrix:
 - BUILD=make
 - MAKEFLAGS="-j4"
 - MAKE_CHECK_COMMAND="true"
-- LLVM_VERSION=3.9
+- LLVM_VERSION=4.0
 - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
 - OVERRIDE_CC="gcc-4.8"
 - OVERRIDE_CXX="g++-4.8"
-# New binutils linker is required for llvm-3.9
-- OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
 - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
 - DRI_DRIVERS=""
 - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa 
--disable-nine --disable-xvmc --disable-vdpau --disable-va 
--disable-omx-bellagio --disable-gallium-osmesa"
@@ -105,13 +103,12 @@ matrix:
   addons:
 apt:
   sources:
-- llvm-toolchain-trusty-3.9
+- llvm-toolchain-trusty-4.0
   packages:
-- binutils-2.26
 # LLVM packaging is broken and misses these dependencies
 - libedit-dev
 # From sources above
-- llvm-3.9-dev
+- llvm-4.0-dev
 # Common
 - xz-utils
 - x11proto-xf86vidmode-dev
@@ -400,7 +397,7 @@ matrix:
 - BUILD=scons
 - SCONSFLAGS="-j4"
 - SCONS_TARGET="swr=1"
-- LLVM_VERSION=3.9
+- LLVM_VERSION=4.0
 - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
 # Keep it symmetrical to the make build. There's no actual SWR, yet.
 - SCONS_CHECK_COMMAND="true"
@@ -409,13 +406,13 @@ matrix:
   addons:
 apt:
   sources:
-- llvm-toolchain-trusty-3.9
+- llvm-toolchain-trusty-4.0
   packages:
 - scons
 # LLVM packaging is broken and misses these dependencies
 - libedit-dev
 # From sources above
-- llvm-3.9-dev
+- llvm-4.0-dev
 # Common
 - xz-utils
 - x11proto-xf86vidmode-dev
diff --git a/configure.ac b/configure.ac
index 8ed606c7694..7fff725954d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -105,7 +105,7 @@ LLVM_REQUIRED_OPENCL=3.9.0
 LLVM_REQUIRED_R600=3.9.0
 LLVM_REQUIRED_RADEONSI=4.0.0
 LLVM_REQUIRED_RADV=4.0.0
-LLVM_REQUIRED_SWR=3.9.0
+LLVM_REQUIRED_SWR=4.0.0
 
 dnl Check for progs
 AC_PROG_CPP
@@ -2695,8 +2695,8 @@ if test -n "$with_gallium_drivers"; then
 fi
 
 # XXX: Keep in sync with LLVM_REQUIRED_SWR
-AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x3.9.0 -a \
-  "x$LLVM_VERSION" != x3.9.1)
+AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x4.0.0 -a \
+  "x$LLVM_VERSION" != x4.0.1)
 
 if test "x$enable_llvm" = "xyes" -a "$with_gallium_drivers"; then
 llvm_require_version $LLVM_REQUIRED_GALLIUM "gallium"
diff --git a/meson.build b/meson.build
index b39e2f8ab96..96e44459465 100644
--- a/meson.build
+++ b/meson.build
@@ -1011,9 +1011,9 @@ if with_gallium_opencl
   # TODO: optional modules
 endif
 
-if with_amd_vk or with_gallium_radeonsi
+if with_amd_vk or with_gallium_radeonsi or with_gallium_swr
   _llvm_version = '>= 4.0.0'
-elif with_gallium_opencl or with_gallium_swr or with_gallium_r600
+elif with_gallium_opencl or with_gallium_r600
   _llvm_version = '>= 3.9.0'
 else
   _llvm_version = '>= 3.3.0'
diff --git a/src/gallium/drivers/swr/Makefile.am 
b/src/gallium/drivers/swr/Makefile.am
index 2bc129429c6..3ee79f7be25 100644
--- a/src/gallium/drivers/swr/Makefile.am
+++ b/src/gallium/drivers/swr/Makefile.am
@@ -352,7 +352,7 @@ include $(top_srcdir)/install-gallium-links.mk
 dist-hook:
 if SWR_INVALID_LLVM_VERSION
@echo "***"
-   @echo "LLVM 3.9.0 or LLVM 3.9.1 required to create the tarball"
+   @echo "LLVM 4.0.0 or LLVM 4.0.1 required to create the tarball"
@echo "***"
@test
 endif
diff --git 

[Mesa-dev] [PATCH 19/31] swr/rast: Make GATHER4PS virtual

[George Kyriazis]

---
 src/gallium/drivers/swr/rasterizer/jitter/builder_mem.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.h 
b/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.h
index 14dc22d..f31cb4a 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.h
+++ b/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.h
@@ -47,7 +47,7 @@ void Gather4(const SWR_FORMAT format, Value* pSrcBase, Value* 
byteOffsets,
 virtual Value *GATHERPS(Value *src, Value *pBase, Value *indices, Value *mask, 
uint8_t scale = 1);
 Value *GATHERPS_16(Value *src, Value *pBase, Value *indices, Value *mask, 
uint8_t scale = 1);
 
-void GATHER4PS(const SWR_FORMAT_INFO , Value* pSrcBase, Value* 
byteOffsets,
+virtual void GATHER4PS(const SWR_FORMAT_INFO , Value* pSrcBase, Value* 
byteOffsets,
 Value* mask, Value* vGatherComponents[], bool bPackedOutput);
 
 virtual Value *GATHERDD(Value* src, Value* pBase, Value* indices, Value* mask, 
uint8_t scale = 1);
-- 
2.7.4

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[Mesa-dev] [PATCH 28/31] swr/rast: Add semantics for translating address

[George Kyriazis]

Added support for another full translation path in fetch jitter.
---
 src/gallium/drivers/swr/rasterizer/jitter/builder_mem.h | 1 +
 src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp | 4 
 2 files changed, 5 insertions(+)

diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.h 
b/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.h
index 4e78098..4f49634 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.h
+++ b/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.h
@@ -75,3 +75,4 @@ Value* pScatterStackSrc{ nullptr };
 Value* pScatterStackOffsets{ nullptr };
 
 
+virtual Value* TRANSLATE_ADDRESS(Value* address) { return address; }
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp 
b/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
index aa2d4c3..880aaf8 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
@@ -1830,12 +1830,16 @@ Value* FetchJit::GetSimdValid16bitIndices(Value* 
pIndices, Value* pLastIndex)
 Value* pZeroIndex = ALLOCA(mInt16Ty);
 STORE(C((uint16_t)0), pZeroIndex);
 
+pLastIndex = TRANSLATE_ADDRESS(pLastIndex);
+
 // Load a SIMD of index pointers
 for(int64_t lane = 0; lane < mVWidth; lane++)
 {
 // Calculate the address of the requested index
 Value *pIndex = GEP(pIndices, C(lane));
 
+pIndex = TRANSLATE_ADDRESS(pIndex);
+
 // check if the address is less than the max index, 
 Value* mask = ICMP_ULT(pIndex, pLastIndex);
 
-- 
2.7.4

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[Mesa-dev] [PATCH 24/31] swr/rast: Make SIMDLib templated types easier to use

[George Kyriazis]

"typename SIMD_T::TypeName" --> "TypeName"
---
 .../drivers/swr/rasterizer/common/simdlib.hpp  |   9 +
 src/gallium/drivers/swr/rasterizer/core/binner.cpp | 338 ++---
 src/gallium/drivers/swr/rasterizer/core/binner.h   |  18 +-
 src/gallium/drivers/swr/rasterizer/core/clip.h | 218 ++---
 .../drivers/swr/rasterizer/core/frontend.cpp   |  22 +-
 5 files changed, 307 insertions(+), 298 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp 
b/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
index 500cf8a..4114645 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
@@ -571,3 +571,12 @@ struct SIMDBase : Traits::IsaImpl
 using SIMD128 = SIMDBase;
 using SIMD256 = SIMDBase;
 using SIMD512 = SIMDBase;
+
+template  using CompareType= typename SIMD_T::CompareType;
+template  using ScaleFactor= typename SIMD_T::ScaleFactor;
+template  using RoundMode  = typename SIMD_T::RoundMode;
+template  using Float  = typename SIMD_T::Float;
+template  using Double = typename SIMD_T::Double;
+template  using Integer= typename SIMD_T::Integer;
+template  using Vec4   = typename SIMD_T::Vec4;
+template  using Mask   = typename SIMD_T::Mask;
diff --git a/src/gallium/drivers/swr/rasterizer/core/binner.cpp 
b/src/gallium/drivers/swr/rasterizer/core/binner.cpp
index 8447bc4..3b093ce 100644
--- a/src/gallium/drivers/swr/rasterizer/core/binner.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/binner.cpp
@@ -41,23 +41,23 @@ void BinPostSetupLinesImpl(
 DRAW_CONTEXT *pDC,
 PA_STATE ,
 uint32_t workerId,
-typename SIMD_T::Vec4 prim[],
-typename SIMD_T::Float recipW[],
+Vec4 prim[],
+Float recipW[],
 uint32_t primMask,
-typename SIMD_T::Integer const ,
-typename SIMD_T::Integer const ,
-typename SIMD_T::Integer const );
+Integer const ,
+Integer const ,
+Integer const );
 
 template 
 void BinPostSetupPointsImpl(
 DRAW_CONTEXT *pDC,
 PA_STATE ,
 uint32_t workerId,
-typename SIMD_T::Vec4 prim[],
+Vec4 prim[],
 uint32_t primMask,
-typename SIMD_T::Integer const ,
-typename SIMD_T::Integer const ,
-typename SIMD_T::Integer const );
+Integer const ,
+Integer const ,
+Integer const );
 
 //
 /// @brief Processes attributes for the backend based on linkage mask and
@@ -327,34 +327,34 @@ struct EarlyRastHelper
 template 
 uint32_t SIMDCALL EarlyRasterizer(
 SIMDBBOX_T _bbox,
-typename SIMD_T::Integer ()[3],
-typename SIMD_T::Integer ()[3],
-typename SIMD_T::Integer ()[3],
-typename SIMD_T::Integer ()[3],
+Integer ()[3],
+Integer ()[3],
+Integer ()[3],
+Integer ()[3],
 uint32_t cwTrisMask,
 uint32_t triMask,
 uint32_t oneTileMask)
 {
 // step to pixel center of top-left pixel of the triangle bbox
-typename SIMD_T::Integer vTopLeftX = SIMD_T::template 
slli_epi32(er_bbox.xmin);
+Integer vTopLeftX = SIMD_T::template 
slli_epi32(er_bbox.xmin);
 vTopLeftX = SIMD_T::add_epi32(vTopLeftX, 
SIMD_T::set1_epi32(FIXED_POINT_SCALE / 2));
 
-typename SIMD_T::Integer vTopLeftY = SIMD_T::template 
slli_epi32(er_bbox.ymin);
+Integer vTopLeftY = SIMD_T::template 
slli_epi32(er_bbox.ymin);
 vTopLeftY = SIMD_T::add_epi32(vTopLeftY, 
SIMD_T::set1_epi32(FIXED_POINT_SCALE / 2));
 
 // negate A and B for CW tris
-typename SIMD_T::Integer vNegA0 = SIMD_T::mullo_epi32(vAi[0], 
SIMD_T::set1_epi32(-1));
-typename SIMD_T::Integer vNegA1 = SIMD_T::mullo_epi32(vAi[1], 
SIMD_T::set1_epi32(-1));
-typename SIMD_T::Integer vNegA2 = SIMD_T::mullo_epi32(vAi[2], 
SIMD_T::set1_epi32(-1));
-typename SIMD_T::Integer vNegB0 = SIMD_T::mullo_epi32(vBi[0], 
SIMD_T::set1_epi32(-1));
-typename SIMD_T::Integer vNegB1 = SIMD_T::mullo_epi32(vBi[1], 
SIMD_T::set1_epi32(-1));
-typename SIMD_T::Integer vNegB2 = SIMD_T::mullo_epi32(vBi[2], 
SIMD_T::set1_epi32(-1));
+Integer vNegA0 = SIMD_T::mullo_epi32(vAi[0], 
SIMD_T::set1_epi32(-1));
+Integer vNegA1 = SIMD_T::mullo_epi32(vAi[1], 
SIMD_T::set1_epi32(-1));
+Integer vNegA2 = SIMD_T::mullo_epi32(vAi[2], 
SIMD_T::set1_epi32(-1));
+Integer vNegB0 = SIMD_T::mullo_epi32(vBi[0], 
SIMD_T::set1_epi32(-1));
+Integer vNegB1 = SIMD_T::mullo_epi32(vBi[1], 
SIMD_T::set1_epi32(-1));
+Integer vNegB2 = SIMD_T::mullo_epi32(vBi[2], 
SIMD_T::set1_epi32(-1));
 
 RDTSC_EVENT(FEEarlyRastEnter, _mm_popcnt_u32(oneTileMask & triMask), 0);
 
-typename SIMD_T::Integer vShiftCntrl = EarlyRastHelper 
::InitShiftCntrl();
-typename SIMD_T::Integer vCwTris = SIMD_T::set1_epi32(cwTrisMask);
-typename SIMD_T::Integer vMask = SIMD_T::sllv_epi32(vCwTris, vShiftCntrl);
+Integer vShiftCntrl = EarlyRastHelper ::InitShiftCntrl();
+   

[Mesa-dev] [PATCH 15/31] swr/rast: Fix avx version of GATHERPS

[George Kyriazis]

GEP was given the wrong type, and asserting.
---
 src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp 
b/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp
index 98d4354..0c9e279 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp
@@ -160,12 +160,13 @@ namespace SwrJit
 vGather = VUNDEF_F();
 Value *vScaleVec = VIMMED1((uint32_t)scale);
 Value *vOffsets = MUL(vIndices, vScaleVec);
+   Value *pBasePtr = BITCAST(pBase, PointerType::get(mInt8Ty, 0));
 for (uint32_t i = 0; i < mVWidth; ++i)
 {
 // single component byte index
 Value *offset = VEXTRACT(vOffsets, C(i));
 // byte pointer to component
-Value *loadAddress = GEP(pBase, offset);
+Value *loadAddress = GEP(pBasePtr, offset);
 loadAddress = BITCAST(loadAddress, PointerType::get(mFP32Ty, 
0));
 // pointer to the value to load if we're masking off a 
component
 Value *maskLoadAddress = GEP(vSrcPtr, { C(0), C(i) });
-- 
2.7.4

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[Mesa-dev] [PATCH 29/31] swr/rast: Consolidate archrast Draw events

[George Kyriazis]

Consolidate archrst draw events into single draw event with an attribute
that represents the type of draw

- Add handlers for new private proto versions of DrawInstancedEvent,
  DrawIndexedInstancedEvent, DrawInstancedSplitEvent, and
  DrawIndexedInstancedSplitEvent
- Convert the draw events to generic DrawInfoEvents
- parse_proto_event_fields() replaces 'AR_DRAW_TYPE' as a field type with
  'uint32_t'. This draw type is actually an enum, but can be represented
  as an unsigned integer.
- is_draw_or_dispatch() recognizes DrawInfoEvent as a draw event
---
 .../drivers/swr/rasterizer/archrast/archrast.cpp   | 28 
 .../drivers/swr/rasterizer/archrast/events.proto   | 32 ++-
 .../swr/rasterizer/archrast/events_private.proto   | 37 ++
 src/gallium/drivers/swr/rasterizer/core/api.cpp|  8 ++---
 4 files changed, 79 insertions(+), 26 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/archrast/archrast.cpp 
b/src/gallium/drivers/swr/rasterizer/archrast/archrast.cpp
index 49e7764..d7a3b29 100644
--- a/src/gallium/drivers/swr/rasterizer/archrast/archrast.cpp
+++ b/src/gallium/drivers/swr/rasterizer/archrast/archrast.cpp
@@ -173,6 +173,34 @@ namespace ArchRast
 mClipper.trivialAcceptCount += _mm_popcnt_u32(event.data.validMask 
& ~event.data.clipMask);
 }
 
+virtual void Handle(const DrawInstancedEvent& event)
+{
+DrawInfoEvent e(event.data.drawId, event.data.type, 
event.data.topology, event.data.numVertices, 0, 0, event.data.startVertex, 
event.data.numInstances, event.data.startInstance);
+
+EventHandlerFile::Handle(e);
+}
+
+virtual void Handle(const DrawIndexedInstancedEvent& event)
+{
+DrawInfoEvent e(event.data.drawId, event.data.type, 
event.data.topology, 0, event.data.numIndices, event.data.indexOffset, 
event.data.baseVertex, event.data.numInstances, event.data.startInstance);
+
+EventHandlerFile::Handle(e);
+}
+
+virtual void Handle(const DrawInstancedSplitEvent& event)
+{
+DrawInfoEvent e(event.data.drawId, event.data.type, 0, 0, 0, 0, 0, 
0, 0);
+
+EventHandlerFile::Handle(e);
+}
+
+virtual void Handle(const DrawIndexedInstancedSplitEvent& event)
+{
+DrawInfoEvent e(event.data.drawId, event.data.type, 0, 0, 0, 0, 0, 
0, 0);
+
+EventHandlerFile::Handle(e);
+}
+
 // Flush cached events for this draw
 virtual void FlushDraw(uint32_t drawId)
 {
diff --git a/src/gallium/drivers/swr/rasterizer/archrast/events.proto 
b/src/gallium/drivers/swr/rasterizer/archrast/events.proto
index c96e7a1..638dfd0 100644
--- a/src/gallium/drivers/swr/rasterizer/archrast/events.proto
+++ b/src/gallium/drivers/swr/rasterizer/archrast/events.proto
@@ -21,28 +21,28 @@
 #
 # Provides definitions for events.
 
-event ThreadStartApiEvent
+enum AR_DRAW_TYPE
 {
+Instanced = 0,
+IndexedInstanced = 1,
+InstancedSplit = 2,
+IndexedInstancedSplit = 3
 };
 
-event ThreadStartWorkerEvent
+event ThreadStartApiEvent
 {
 };
 
-event DrawInstancedEvent
+event ThreadStartWorkerEvent
 {
-uint32_t drawId;
-uint32_t topology;
-uint32_t numVertices;
-int32_t  startVertex;
-uint32_t numInstances;
-uint32_t startInstance;
 };
 
-event DrawIndexedInstancedEvent
+event DrawInfoEvent
 {
 uint32_t drawId;
+AR_DRAW_TYPE type;
 uint32_t topology;
+uint32_t numVertices;
 uint32_t numIndices;
 int32_t  indexOffset;
 int32_t  baseVertex;
@@ -64,18 +64,6 @@ event FrameEndEvent
 uint32_t nextDrawId;
 };
 
-///@brief API Stat: Split draw event for DrawInstanced. In certain cases, 
Rasty can split draws up into smaller draws.
-event DrawInstancedSplitEvent
-{
-uint32_t drawId;
-};
-
-///@brief API Stat: Split draw event for DrawIndexedInstanced.
-event DrawIndexedInstancedSplitEvent
-{
-uint32_t drawId;
-};
-
 ///@brief API Stat: Synchonization event.
 event SwrSyncEvent
 {
diff --git a/src/gallium/drivers/swr/rasterizer/archrast/events_private.proto 
b/src/gallium/drivers/swr/rasterizer/archrast/events_private.proto
index f6dde33..71b723d 100644
--- a/src/gallium/drivers/swr/rasterizer/archrast/events_private.proto
+++ b/src/gallium/drivers/swr/rasterizer/archrast/events_private.proto
@@ -113,3 +113,40 @@ event ClipInfoEvent
 uint32_t validMask;
 uint32_t clipMask;
 };
+
+event DrawInstancedEvent
+{
+uint32_t drawId;
+AR_DRAW_TYPE type;
+uint32_t topology;
+uint32_t numVertices;
+int32_t  startVertex;
+uint32_t numInstances;
+uint32_t startInstance;
+};
+
+event DrawIndexedInstancedEvent
+{
+uint32_t drawId;
+AR_DRAW_TYPE type;
+uint32_t topology;
+uint32_t numIndices;
+int32_t  indexOffset;
+int32_t  baseVertex;
+uint32_t numInstances;
+uint32_t startInstance;
+};
+
+///@brief API Stat: Split draw event for 

[Mesa-dev] [PATCH 30/31] swr/rast: Normalize path for debug metadata

[George Kyriazis]

in template gen_llvm.hpp
---
 src/gallium/drivers/swr/rasterizer/codegen/templates/gen_llvm.hpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_llvm.hpp 
b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_llvm.hpp
index 9db6c61..d61194d 100644
--- a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_llvm.hpp
+++ b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_llvm.hpp
@@ -57,7 +57,7 @@ namespace SwrJit
 
 // Compute debug metadata
 llvm::DIBuilder builder(*pJitMgr->mpCurrentModule);
-llvm::DIFile* pFile = builder.createFile("${input_file}", 
"${input_dir}");
+llvm::DIFile* pFile = builder.createFile("${input_file}", 
"${os.path.normpath(input_dir).replace('\\', '/')}");
 
 std::vector> dbgMembers;
 %for member in type['members']:
@@ -79,6 +79,7 @@ namespace SwrJit
 } // ns SwrJit
 
 <%! # Global function definitions
+import os
 def calc_max_len(fields):
 max_type_len = 0
 max_name_len = 0
-- 
2.7.4

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[Mesa-dev] [PATCH 23/31] swr/rast: Use right type for offset to next component

[George Kyriazis]

---
 src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp 
b/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp
index 491fb98..617cf33 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp
@@ -401,7 +401,7 @@ namespace SwrJit
 if (info.numComps > 2)
 {
 // offset base to the next components(zw) in the vertex to 
gather
-pSrcBase = OFFSET_TO_NEXT_COMPONENT(pSrcBase, C((char)4));
+pSrcBase = OFFSET_TO_NEXT_COMPONENT(pSrcBase, C((intptr_t)4));
 
 vGatherResult[1] = GATHERPS(vGatherMaskedVal, pSrcBase, 
byteOffsets, vMask);
 // e.g. result of second 8x32bit integer gather for 16bit 
components
@@ -434,7 +434,7 @@ namespace SwrJit
 vGatherComponents[swizzleIndex] = 
GATHERPS(vGatherComponents[swizzleIndex], pSrcBase, byteOffsets, vMask);
 
 // offset base to the next component to gather
-pSrcBase = OFFSET_TO_NEXT_COMPONENT(pSrcBase, C((char)4));
+pSrcBase = OFFSET_TO_NEXT_COMPONENT(pSrcBase, C((intptr_t)4));
 }
 }
 break;
@@ -479,7 +479,7 @@ namespace SwrJit
 if (info.numComps > 2)
 {
 // offset base to the next components(zw) in the vertex to 
gather
-pSrcBase = OFFSET_TO_NEXT_COMPONENT(pSrcBase, C((char)4));
+pSrcBase = OFFSET_TO_NEXT_COMPONENT(pSrcBase, C((intptr_t)4));
 
 vGatherResult[1] = GATHERDD(vGatherMaskedVal, pSrcBase, 
byteOffsets, vMask);
 // e.g. result of second 8x32bit integer gather for 16bit 
components
@@ -513,7 +513,7 @@ namespace SwrJit
 vGatherComponents[swizzleIndex] = 
GATHERDD(vGatherComponents[swizzleIndex], pSrcBase, byteOffsets, vMask);
 
 // offset base to the next component to gather
-pSrcBase = OFFSET_TO_NEXT_COMPONENT(pSrcBase, C((char)4));
+pSrcBase = OFFSET_TO_NEXT_COMPONENT(pSrcBase, C((intptr_t)4));
 }
 }
 break;
-- 
2.7.4

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[Mesa-dev] [PATCH 12/31] swr/rast: whitespace cleanup

[George Kyriazis]

---
 .../drivers/swr/rasterizer/jitter/JitManager.h | 38 +++---
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h 
b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
index ddd6864..3660249 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
+++ b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
@@ -136,38 +136,38 @@ struct JitManager
 JitCachemCache;
 
 // Need to be rebuilt after a JIT and before building new IR
-llvm::Module* mpCurrentModule;
-bool mIsModuleFinalized;
-uint32_t mJitNumber;
+llvm::Module*   mpCurrentModule;
+boolmIsModuleFinalized;
+uint32_tmJitNumber;
 
-uint32_t mVWidth;
+uint32_tmVWidth;
 
 
 // Built in types.
-llvm::Type*mInt8Ty;
-llvm::Type*mInt32Ty;
-llvm::Type*mInt64Ty;
-llvm::Type*mFP32Ty;
+llvm::Type* mInt8Ty;
+llvm::Type* mInt32Ty;
+llvm::Type* mInt64Ty;
+llvm::Type* mFP32Ty;
 
-llvm::Type* mSimtFP32Ty;
-llvm::Type* mSimtInt32Ty;
+llvm::Type* mSimtFP32Ty;
+llvm::Type* mSimtInt32Ty;
 
-llvm::Type* mSimdVectorInt32Ty;
-llvm::Type* mSimdVectorTy;
+llvm::Type* mSimdVectorInt32Ty;
+llvm::Type* mSimdVectorTy;
 
 #if USE_SIMD16_SHADERS
-llvm::Type* mSimd16FP32Ty;
-llvm::Type* mSimd16Int32Ty;
+llvm::Type* mSimd16FP32Ty;
+llvm::Type* mSimd16Int32Ty;
 
-llvm::Type* mSimd16VectorFP32Ty;
-llvm::Type* mSimd16VectorInt32Ty;
+llvm::Type* mSimd16VectorFP32Ty;
+llvm::Type* mSimd16VectorInt32Ty;
 
 #endif
 // fetch shader types
-llvm::FunctionType*mFetchShaderTy;
+llvm::FunctionType* mFetchShaderTy;
 
-JitInstructionSet mArch;
-std::string mCore;
+JitInstructionSet   mArch;
+std::string mCore;
 
 // Debugging support
 std::unordered_map mDebugStructMap;
-- 
2.7.4

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[Mesa-dev] [PATCH 17/31] swr/rast: Misc cleanup

[George Kyriazis]

Together with correct detection of clipDistance NaNs when no cullDistance is set
---
 src/gallium/drivers/swr/rasterizer/core/clip.h|  2 +-
 src/gallium/drivers/swr/rasterizer/core/context.h | 26 
 src/gallium/drivers/swr/rasterizer/core/state.h   | 81 +--
 3 files changed, 60 insertions(+), 49 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/clip.h 
b/src/gallium/drivers/swr/rasterizer/core/clip.h
index 5193672..ddee3b1 100644
--- a/src/gallium/drivers/swr/rasterizer/core/clip.h
+++ b/src/gallium/drivers/swr/rasterizer/core/clip.h
@@ -703,7 +703,7 @@ public:
 primMask &= ~ComputeNaNMask(prim);
 
 // user cull distance cull 
-if (state.backendState.cullDistanceMask)
+if (state.backendState.cullDistanceMask | 
state.backendState.clipDistanceMask)
 {
 primMask &= ~ComputeUserClipCullMask(pa, prim);
 }
diff --git a/src/gallium/drivers/swr/rasterizer/core/context.h 
b/src/gallium/drivers/swr/rasterizer/core/context.h
index a284c42..489aa78 100644
--- a/src/gallium/drivers/swr/rasterizer/core/context.h
+++ b/src/gallium/drivers/swr/rasterizer/core/context.h
@@ -227,8 +227,9 @@ OSALIGNLINE(struct) API_STATE
 // Vertex Buffers
 SWR_VERTEX_BUFFER_STATE vertexBuffers[KNOB_NUM_STREAMS];
 
-// Index Buffer
-SWR_INDEX_BUFFER_STATE  indexBuffer;
+// GS - Geometry Shader State
+SWR_GS_STATEgsState;
+PFN_GS_FUNC pfnGsFunc;
 
 // FS - Fetch Shader State
 PFN_FETCH_FUNC  pfnFetchFunc;
@@ -236,9 +237,8 @@ OSALIGNLINE(struct) API_STATE
 // VS - Vertex Shader State
 PFN_VERTEX_FUNC pfnVertexFunc;
 
-// GS - Geometry Shader State
-PFN_GS_FUNC pfnGsFunc;
-SWR_GS_STATEgsState;
+// Index Buffer
+SWR_INDEX_BUFFER_STATE  indexBuffer;
 
 // CS - Compute Shader
 PFN_CS_FUNC pfnCsFunc;
@@ -265,8 +265,6 @@ OSALIGNLINE(struct) API_STATE
 // Number of attributes used by the frontend (vs, so, gs)
 uint32_tfeNumAttributes;
 
-PRIMITIVE_TOPOLOGY  topology;
-boolforceFront;
 
 // RS - Rasterizer State
 SWR_RASTSTATE   rastState;
@@ -282,8 +280,12 @@ OSALIGNLINE(struct) API_STATE
 SWR_RECTscissorsInFixedPoint[KNOB_NUM_VIEWPORTS_SCISSORS];
 boolscissorsTileAligned;
 
+boolforceFront;
+PRIMITIVE_TOPOLOGY  topology;
+
+
 // Backend state
-SWR_BACKEND_STATE   backendState;
+OSALIGNLINE(SWR_BACKEND_STATE) backendState;
 
 SWR_DEPTH_BOUNDS_STATE  depthBoundsState;
 
@@ -400,8 +402,6 @@ struct DRAW_CONTEXT
 DispatchQueue*  pDispatch;  // Queue for thread groups. (isCompute)
 };
 DRAW_STATE* pState; // Read-only state. Core should not 
update this outside of API thread.
-DRAW_DYNAMIC_STATE dynState;
-
 CachingArena*   pArena;
 
 uint32_tdrawId;
@@ -412,11 +412,13 @@ struct DRAW_CONTEXT
 
 FE_WORK FeWork;
 
+SYNC_DESC   retireCallback; // Call this func when this DC is retired.
+
+DRAW_DYNAMIC_STATE dynState;
+
 volatile OSALIGNLINE(bool)   doneFE; // Is FE work done for 
this draw?
 volatile OSALIGNLINE(uint32_t)   FeLock;
 volatile OSALIGNLINE(uint32_t)   threadsDone;
-
-SYNC_DESC   retireCallback; // Call this func when this DC is retired.
 };
 
 static_assert((sizeof(DRAW_CONTEXT) & 63) == 0, "Invalid size for 
DRAW_CONTEXT");
diff --git a/src/gallium/drivers/swr/rasterizer/core/state.h 
b/src/gallium/drivers/swr/rasterizer/core/state.h
index d959c64..6b108d9 100644
--- a/src/gallium/drivers/swr/rasterizer/core/state.h
+++ b/src/gallium/drivers/swr/rasterizer/core/state.h
@@ -228,8 +228,8 @@ struct SWR_VS_CONTEXT
 #if USE_SIMD16_FRONTEND
 uint32_t AlternateOffset;   // IN: amount to offset for interleaving 
even/odd simd8 in simd16vertex output
 #if USE_SIMD16_VS
-simd16scalari mask16;  // IN: Active mask for shader (16-wide)
-simd16scalari VertexID16;  // IN: Vertex ID (16-wide)
+simd16scalari mask16;   // IN: Active mask for shader (16-wide)
+simd16scalari VertexID16;   // IN: Vertex ID (16-wide)
 #endif
 #endif
 };
@@ -553,11 +553,10 @@ struct SWR_SURFACE_STATE
 // in the fetch shader jit
 struct SWR_VERTEX_BUFFER_STATE
 {
+gfxptr_t xpData;
 uint32_t index;
 uint32_t pitch;
-gfxptr_t xpData;
 uint32_t size;
-uint32_t numaNode;
 uint32_t minVertex; // min vertex (for bounds checking)
 uint32_t maxVertex; // size / pitch.  precalculated value used 
by fetch shader for OOB checks
 uint32_t partialInboundsSize;   // size % pitch.  precalculated value used 
by fetch shader for partially OOB vertices
@@ -565,9 +564,9 @@ struct SWR_VERTEX_BUFFER_STATE
 
 struct SWR_INDEX_BUFFER_STATE
 {
+const void *pIndices;
 // Format type for 

[Mesa-dev] [PATCH 27/31] swr/rast: Fix SRL call with a non-immediate

[George Kyriazis]

Don't count on the compiler automagically converting an srli call to
srl if the shift count isn't an immediate.
---
 src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx.inl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx.inl 
b/src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx.inl
index 56f60a8..b1511c6 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx.inl
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx.inl
@@ -206,9 +206,9 @@ SIMD_IWRAPPER_1I(srai_epi32);   // return a >> 
ImmT   (int32)
 SIMD_IWRAPPER_1I(srli_epi32);   // return a >> ImmT   (uint32)
 SIMD_IWRAPPER_1I_(srli_si, _mm_srli_si128); // return a >> (ImmT*8) (uint)
 
-static SIMDINLINE Integer SIMDCALL srli_epi64(Integer a, uint32_t n)
+static SIMDINLINE Integer SIMDCALL srl_epi64(Integer a, Integer n)
 {
-return _mm_srli_epi64(a, n);
+return _mm_srl_epi64(a, n);
 }
 
 template  // same as srli_si, but with 
Float cast to int
-- 
2.7.4

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[Mesa-dev] [PATCH 11/31] swr/rast: Fix invalid number of attributes

[George Kyriazis]

Fix invalid number of attributes passed into tesselation PA.
Needs to take into account any offsets from the shader.
nnocuous issue, but removes an assert firing in debug.
---
 src/gallium/drivers/swr/rasterizer/core/frontend.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp 
b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
index c44dd2c..33533af 100644
--- a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
@@ -1334,7 +1334,7 @@ static void TessellationStages(
 dsContext.vectorStride,
 #endif
 SWR_VTX_NUM_SLOTS,
-tsState.numDsOutputAttribs,
+tsState.numDsOutputAttribs + tsState.dsOutVtxAttribOffset,
 tsData.ppIndices,
 tsData.NumPrimitives,
 tsState.postDSTopology,
-- 
2.7.4

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[Mesa-dev] [PATCH 25/31] swr/rast: Update/add comments

[George Kyriazis]

---
 src/gallium/drivers/swr/rasterizer/core/api.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp 
b/src/gallium/drivers/swr/rasterizer/core/api.cpp
index f45da96..99d3cd5 100644
--- a/src/gallium/drivers/swr/rasterizer/core/api.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/api.cpp
@@ -921,7 +921,7 @@ void SetupPipeline(DRAW_CONTEXT *pDC)
 };
 
 
-// disable clipper if viewport transform is disabled
+// Disable clipper if viewport transform is disabled
 if (pState->state.frontendState.vpTransformDisable)
 {
 pState->pfnProcessPrims = pfnBinner;
@@ -930,6 +930,7 @@ void SetupPipeline(DRAW_CONTEXT *pDC)
 #endif
 }
 
+// Disable rasterizer and backend if no pixel, no depth/stencil, and no 
attributes
 if ((pState->state.psState.pfnPixelShader == nullptr) &&
 (pState->state.depthStencilState.depthTestEnable == FALSE) &&
 (pState->state.depthStencilState.depthWriteEnable == FALSE) &&
-- 
2.7.4

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