Re: [PEDA] Protel's Good/Bad points (WAS:Using 3D)
It's possible. PC hardware can exhibit problems. In all those MB of RAM, if a few bits flake out, it can crash a program. New PCs are on the absolute bleeding edge, which means some blood (and sweat and tears) is bound to be spilt somewhere. If Protel is the largest app (with your design file loaded) you run on that PC, it could be using an area of RAM that is not fit for use. Instead of running the latest 2 GHz P++, maybe you should try it on an older, slower PC. The most advanced PC I have right now is a W2K/SP2 dual-PIII 1.0 GHz with 512MB PC133 and a Matrox G450 video card. Rock stable - but then I haven't done any Protel jobs as huge as the one you are doing. Protel 99SE has plenty of bugs and quirks. But no program, no matter how good, can overcome a marginal, overclocked, metastable, negative-timing-margin PC. Please note that the older, slower PC that a lot of people have sitting around was a bleeding edge machine when it was new. For this recommendation to work, it seems that one would have to try the software on a slow system built out of more modern fast components. I seem to recall recommendations against overclocking 286 systems because it could lead to flaky results. The contents of this E-mail may contain information that is legally privileged and/or confidential to the named recipient. This information is not to be used by any other person and/or organisation. The views expressed in this document do not necessarily reflect those of the company. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] xls files
Hello Wayne Save a copy of your ddb file to a safe place first, perhaps under a different name, before importing other files. We have had some trouble when non-Protel files were imported into the database. I don't remember the details but I think we were getting some sort of crashing. We were in a rush to get the job done so we did not investigate further. If I recall correctly, we recovered by using one of the backup files. Phil Wayne Yep thats one solution but I would really like to know if I can open the xls file with excel when its still within the database just like you do with a word doc. Cheers Wayne Trow The contents of this E-mail may contain information that is legally privileged and/or confidential to the named recipient. This information is not to be used by any other person and/or organisation. The views expressed in this document do not necessarily reflect those of the company. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Logo's for FCC, UL and CE ?
This issue with CE marking has caused many of us lots of headaches. Wading through the standards documents, it becomes clear that they are the work committees where all the members want to have their say, whether or not it is of value or not. How about changing the location of the tattoo to one's cheek. Then one can make a statement at each inspection ... Sorry! It's Friday here in New Zealand... -Original Message- From: David Cuthbert [mailto:[EMAIL PROTECTED]] Sent: Friday, 10 August 2001 08:15 To: Protel EDA Forum Subject: Re: [PEDA] Logo's for FCC, UL and CE ? Brad Velander [EMAIL PROTECTED] wrote: Similarly, one can apply the same logic to resistors, capacitors and other components. Unless there is a specific directive which covers those types of components, they are covered under the products most suitable directives and are the responsibility of the integrator who used the components in their product. Hmm... this begs the question: What about CE markings on the integrator him/herself? Presumably, if an engineer has a CE tattoo on his arm/shoulder/etc., this would mean the products he designs are CE-compliant, right? With tongue firmly in cheek... --- Dave Cuthbert [EMAIL PROTECTED] The contents of this E-mail may contain information that is legally privileged and/or confidential to the named recipient. This information is not to be used by any other person and/or organisation. The views expressed in this document do not necessarily reflect those of the company. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] a lib. for everyone
The suggestions for locating the library on a web site has a lot of merit, especially in view of the concerns summarised here by Andrew. Software that is used for on-line catalogue shopping could possibly be adapted, or used as a model, to allow users to browse through the various permutations possible for any particular footprint. This would probably produce the results that the users would want sooner, less expensively and more reliably than trying to have the same facility incorporated within Protel. It would then be possible to show all of the specifications and parameters related to the footprint, such as paste screen thickness, reflow vs solder wave vs hand soldering, margin from actual part to the part outline etc. Some guidelines should be set regarding the information to be included in the spec. sheet for each footprint. It would then be left up to the user to decide how applicable a particular footprint would be in his situation. This approach would allow Protel's programmers to stick with improving the basic product. The web site could be supported by one or more sponsors, donations or subscriptions. There are probably enough participants in this forum who have the skills to develop such a web site. People are already putting time into developing Protel servers and sharing them with other forum members. Just a thought or two. Phil So -Original Message- From: Andrew J Jenkins [mailto:[EMAIL PROTECTED]] Sent: Thursday, 26 July 2001 05:56 To: Protel EDA Forum Subject: Re: [PEDA] a lib. for everyone On 01:10 PM 7/24/2001 -0700, Brad Velander wrote: Andrew, please don't throw me into the simple nay-sayers Nope. I didn't. Just doubting Thomas, to whom I originally replied. I have my doubts about whether it could be accomplished amongst a group as diverse as ours, but it can be done. My concerns would be more for the diverse opinions and desired features within the library and coming to some consensus on a standard approach. Features are the stumbling block. As has been mentioned, one person's preferred footprint may not be another's. (my efforts, for instance, have been primarily limited to hand-soldered PCBs, resulting in a need for much larger pads than might be expected with other soldering processes) This leads me to the conclusion that either multiple working footprints for a given base footprint will have to be individually generated, or another process which allows for capturing the variations within a single, generalized part, like folding an agreed-upon group of mfg methods requirements into each footprint, by use of the available layers, or by use of some other trick(s). Unless some trickery is practiced, I'm concerned that the library size might grow beyond the expected 10K count value that has been offered. Many of us have that tendency to ramble, as long as it is a flow of thoughts that others can discuss and build on what is the problem with it? None that I can think of. I was just practicing my apologetics ;) aj P.S. In answer to your question/comment a few days ago, I've been here all along, never left, just on Hiatus for the last couple months, and so fell into the nether-state of Lurker...Too much work on the decrepit 100+ yr old house to accomplish, and too little time to accomplish it in...(right now, it's just too danged hot here in Cleveburg to work outside in the sun all day long, (ex: 88F 70%RH @ 5pm yesterday) so I have un poco tiempo with which to play before dragging my butt back out into the lobster pot every so often. The contents of this E-mail may contain information that is legally privileged and/or confidential to the named recipient. This information is not to be used by any other person and/or organisation. The views expressed in this document do not necessarily reflect those of the company. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] New on-line PCB quoting service for Protel 99 SE
Buried within Abd ul-Rahman's message Except for the perception that Protel is wasting resources on this. Protel, however, for better or for worse, has a history of providing us with things that we don't want and we must admit that sometimes, at least, they have been right and we had our heads in the sand. I would bet that most are all working for organisations that are (getting more) lean and mean due to competitive pressures. This implies that we should be using suppliers of goods and services that are also lean and mean. Remember, the money that they spend must ultimately come from their customers, past, present and future. Philip So Electronics Design Engineer PDL Electronics Ltd 81 Austin Street Napier New Zealand Phone :++64 6 843 5855 ext. 7152 Fax:++64 6 843 0603 E-mail :[EMAIL PROTECTED] Visit our website: http://www.pdl.co.nz The contents of this E-mail may contain information that is legally privileged and/or confidential to the named recipient. This information is not to be used by any other person and/or organisation. The views expressed in this document do not necessarily reflect those of the company. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] [PROTEL EDA USERS]: Help with a daughter board
Expanding on Andrew's fourth suggestion. Enter your board outline and do you component placement then get one or two sets of prototype boards made with no etching. There will be copper all over one or both sides of the boards. Maybe use one of those quick turn around places. While they are making the prototypes, you can place the tracks. You will then be able to populate the boards with components and check that no components interfere with each other. You will also be able to check that the completed assembly will fit in the enclosure and that wiring looms can be routed nicely. The RF designer can also check that the circuitry on the lower board will not interfere with the circuitry on the upper board. We do 3-D models in AutoCAD here but we have found that working out issues like the routing wires is still best done using a physical sample of the board assemblies. -Original Message- From: Andrew Jenkins [mailto:[EMAIL PROTECTED]] Sent: Tuesday, 6 February 2001 17:37 To: Multiple recipients of list proteledausers Subject: Re: [PROTEL EDA USERS]: Help with a daughter board On 10:46 PM 2/5/2001 -0500, Glennster wrote: What is the best way to ensure that the 2 boards mate exactly. When assembled, the top board goes down on top of the relays with the contacts sticking through the PCB and is soldered on the top along with the header. Honestly? IMO, the VERY best way to ensure that the boards mate correctly is to 1. use your own custom footprints, NOT THE MFG FOOTPRINTS, which will be made by using a vernier to measure all of the critical dimensions. This includes both mating connectors (headers and the like) as well as any penetrating components (those components which penetrate the RF board by routed holes in the RF board) 2. When designing the board, cut and paste a copy of the RF board directly ontop of a copy of the relay board to verify accurate location of mating components. 3. print the board layouts to mylar at 2:1 or at a magnification as large as the largest board, and overlay one print on the other to verify that everything is accurately registered. That's how I get it right the first time. Optional... 4. If this is more than a one-off, and especially if you're going to produce large quantities, prototype the circuits in question and hand fab an assembly to verify that the real world will play out. regards, aj The contents of this E-mail may contain information that is legally privileged and/or confidential to the named recipient. This information is not to be used by any other person and/or organisation. The views expressed in this document do not necessarily reflect those of the company. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the reply command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
Re: [PEDA] Protel news. Was: BGA Design
-Original Message- From: Terry Harris [mailto:[EMAIL PROTECTED]] Sent: Tuesday, 8 May 2001 04:12 To: Protel EDA Forum Subject: Re: [PEDA] Protel news. Was: BGA Design On Mon, 07 May 2001 10:48:49 +1000, Don wrote: Combined in what way? Personally I write HDL (verilog), draw schematics, layout PCBs, and write embedded software - I doubt many Protel customers do all that as individuals although many will as companies. What use is a VHDL or C compiler to a guy like... Brad Velander, Lead PCB Designer, If you have a look at the current toolchain for the AT94 it will be immediately clear ( look for co-verification ) as to why it would be advantageous for Atmel to be able to source low cost modules to make the CPUsea of gates ubiquitous. That still doesn't answer the question what does Brad want a C compiler for. Currently their tools are sourced from the big guys such as Mentor have licensing cost issues which prevent the devices from common usage. I will agree providing low cost tools needed to do the job would help Atmel and it's customers. If the speculation about the direction that Protel is taking is correct, then they would be aiming to serve two masters - the traditional PCB focused user and the user who wants it all. This sort of move would likely make the software package truly fat-ware with lots of extra features and complications that most of the users don't need and will resent having to navigate around to get to the core features that they do need. Even if they decide to create two product lines, each to serve one master, it is likely that there will still be extra overhead built into the simpler product. This is analagous to what has happened to MS Word and Excel over the years. How many people truly need to use all of the features in the current versions? I have yet to see where the extra overhead introduced by the new features made the software run faster. Many of the added features are of the me too type where they don't work all that well, or don't do enough, forcing you to go buy the software that is focused on the type of work you are intending to do. At GE, they had a New Product Introduction procedure that forced you to look at the real needs of the potential customer base. One of the criteria used in drawing up the product specifications was that the product should meet the needs of 80% of it's potential customer base. Often, trying to meet the needs of the remaining 20% of your potential customer base forces too much extra cost onto the 80%. The products developed using this philosopy did quite well on the marketplace. Phil So The contents of this E-mail may contain information that is legally privileged and/or confidential to the named recipient. This information is not to be used by any other person and/or organisation. The views expressed in this document do not necessarily reflect those of the company. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Netlist error?
project only the GND net. All the GND power ports are only connecting to each other on the one sheet, while all the others are creating a seperate GND net for the rest of the project. I have seen something like what I think you have described. There were two nets in the netlist with identical net names. Each contained a subset of the nodes that were to be connected to the net in the schematic. There was no overlap between the two nets. All nodes that were to be connected appeared in one of the two nets. I fixed some other unrelated(?) ERC and this situation disappeared. That is, the two nets became one that contained all the proper nodes. I did not investigate further since the deadline for several PCB's was imminent. Regards, Phil So The contents of this E-mail may contain information that is legally privileged and/or confidential to the named recipient. This information is not to be used by any other person and/or organisation. The views expressed in this document do not necessarily reflect those of the company. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
