Re: Will z/OS be obsolete in 5 years?

On Tue, 8 Aug 2023 at 00:06, Jon Perryman wrote: > > On Thu, 20 Jul 2023 at 09:01, Rob van der Heij > wrote: > > It would be interesting to see your evidence of IBM Z not performing > well with Linux. > > Linux on z performs better than Linux on most other hardware.

Re: Will z/OS be obsolete in 5 years?

On Thu, 20 Jul 2023 at 02:15, Jon Perryman wrote: > > Why do that. It would result in a huge loss of hardware revenue. > > IFLs for running UNIX are much cheaper than the CPUs needed to run z/OS. > > IFL's are discounted because Linux runs poorly on z16. Every CPU in a z16 > is the same so IBM

Re: Vector Instructions

On Wed, 29 Sept 2021 at 06:06, Dan Greiner wrote: > I have put together a series of PowerPoint files illustrating the > operation of the vector-facility instructions ... a sort of graphic-novel > version of Chapters 21-25 of the PoO. Since the Assembler List doesn't > accept file uploads, you

Re: 9121 TCM Teardown

On Tue, 6 Oct 2020 at 19:58, Ray Mansell wrote: > What fun! However, I feel this should have been posted to the > DisAssembler list :-) If you have the stamina for more destructive review of devices we value: https://youtu.be/CBjoWMA5d84

Re: Structured Programming Macro Package

On Sun, 13 Sep 2020 at 13:18, FancyDancer wrote: > The main claim to fame that this package has is that is is able to > override the normal precedence of AND conjuctions and have OR conjunctions > be evaluated at a higher priority, by adding an extra pair of parentheses > around two or more

Re: Deep cuts

On Fri, 4 Sep 2020 at 19:46, Seymour J Metz wrote: > VM uses a token of 8X'FF' at the end of the (R1) parameter list. I don't > recall what the convention is for the (R0) extended parameter list > introduced by VM/SP. The extended parameter list uses begin- and end pointers, 31 bit as CMS does

Re: Clearing a register

Speed hardly matters unless you have to do it very often. I had something like that when shifting 32 bit into 64 and was lucky enough to have half a spare register and could do LR (which I suspect might be something the CPU has some tricks for)

Re: Code visitation

On Wed, 5 Aug 2020 at 09:49, Keven wrote: Are there any of y’all out there who, like me, sometimes have a > wistful yearning to see some code they wrote some number of years ago at a > company they no longer work for..for no reason other than simply > wanting to look at it? Maybe

Re: *-*

On Thu, 30 Apr 2020 at 14:40, Seymour J Metz wrote: > Empirically, it *is* necessary to explain that equating R0 though R15 to > register numbers other than the ones implicit in the names is a cardinal > sin. > I ran into some code where the programmer decided to know better and had defined

Re: BASR to AMODE 64

On Sat, 23 Nov 2019 at 01:11, Bernd Oppolzer wrote: > As others have pointed out, the different OSes have different strategies; > z/OS does never allocate virtual addresses from 0x8000 to 0x. > I sometimes wish the Principles of Operation would along those lines avoid to allocate

Re: Questionable Instructions in Obtaining EAX documentation

On Mon, 11 Nov 2019 at 14:56, Charles Mills wrote: > Works better than it used to! It's good to ~2 billion now, right? Was only > good to ~16 million when they coded it. > > I'm not confused on how LA works in AMODE 31, am I? I never use it for > integer arithmetic anymore so I could be off base

Re: Questionable Instructions in Obtaining EAX documentation

On Sat, 9 Nov 2019 at 20:51, Kerry Liles wrote: > Old habits die hard... I still just useLA 1,256although now I > might just code it asLA 1,256(,0) > I'm more worried about old code and old programmers doing LA 1,1(,1) doing arithmetic. Rob

Re: BIC documentation - unclear?

On Thu, 20 Jun 2019 at 16:53, John McKown wrote: > Especially CFC & UPT. IIRC, those were put in explicitly for DFSORT. And, > used improperly CFC causes ozone depletion {grin}. But the latest one that > caused me to laugh was "Perform Random Number Operation" (PRNO -- porno). > BRAS is also

Re: Fwd: Assembler III at Latham, NY 12110, USA

On Wed, 10 Apr 2019 at 13:20, Don Higgins wrote: > I am interested in the Assembler III position even though I do not own > steel toed shoes. I consider "signal on novalue" in REXX as my steel toed shoes, but I decline offshore roles. Sir Rob the Plumber

Re: I Want An OPTABLE Built-In Function

On Wed, 3 Apr 2019 at 16:35, Farley, Peter x23353 < peter.far...@broadridge.com> wrote: > As opposed to the Scots instruction set, MC'opcode? > > That was a good chuckle, thanks for making my morning brighter! > Why didn't I think of that? All these things like EQU, ORG, DS, and PRINT... that's

Re: I Want An OPTABLE Built-In Function

On Wed, 3 Apr 2019 at 09:58, Jonathan Scott wrote: To check whether a machine operation code is supported in the > current OPTABLE, use the operation code attribute, O'opcode. > I refer to the "new" instructions as the Welsh instruction set, and this checks whether it's Irish :-) Rob

Re: Fwd: Assembler III at Latham, NY 12110, USA

On Tue, 19 Mar 2019 at 20:01, Seymour J Metz wrote: > No worse than Monster. > > "When the only tool in your toolbox is a pipe, everything looks like a > filter." > I don't really mind a job offer as Piping Engineer, but I don't like off-shore work :-) It bothers me more if they match VMware

Re: Multi CPU interlock question

On Wed, 9 Jan 2019 at 12:17, Martin Truebner wrote: > Joe, > > Robs is answer is already saying everything but let me give you > some more details. > > the load (or store) will always do it on a fullwordBUT to do it > proper would require doing it with a CS. > As long as the operand is

Re: Multi CPU interlock question

On Wed, 9 Jan 2019 at 11:29, Joe Owens wrote: > A 4 byte address field in virtual storage has one updater and many readers > > If using load and store instuctions, will the readers always see a > complete (valid) address, or could a CPU see a partially updated field > while a store is in

Re: Macro Behavior

On Fri, 19 Oct 2018 at 19:04, Peter Relson wrote: > There is no "should" in this sort of situation. There is a "could". There > is a "wouldn't it be nice if". > > Could it be done? Sure. Would having done so have helped this case? Sure. > Would doing so be a better use of limited resources than

Re: EX

Ouch, obviously not as Jonathan points out... :facepalm: On Mon, 6 Aug 2018 at 17:23, Rob van der Heij wrote: > On Mon, 6 Aug 2018 at 16:35, Ed Jaffe wrote: > >> We use 'Jxx *+2' which disturbs no registers and is guaranteed to fail >> with an 0C1. >> >> I'm ver

Re: EX

On Mon, 6 Aug 2018 at 16:35, Ed Jaffe wrote: > We use 'Jxx *+2' which disturbs no registers and is guaranteed to fail > with an 0C1. > > I'm very fond of having an extra code for the type of assert, so I can already blush before I see the listing ;-) I suppose I could have the macro generate

Re: EQU * considered harmful

> BL *+4+4+4 > L R15,ERRNO_30303 > B General_error_routine > MVCX,Y > (Again, just typing some example code, not actual code.) > > Of course, I also use GOTO in COBOL, so maybe I am just a non-standard > person. > > To

Re: EQU * considered harmful

I’m afraid those sequences only make sense when you wrote them, not much later. I inherited similar attempts to code the length of data. Just don’t. On Fri, 3 Aug 2018 at 18:03, Tony Thigpen wrote: > I was taught that to make it easy to read, do the following: >BL *+4+2 > LR

Re: EQU * considered harmful

On Fri, 3 Aug 2018 at 03:32, Phil Smith III wrote: > Hobart Spitz wrote: > > >can't endorse either DS 0H or EQU *; use structured macros instead. > > Why "can't endorse"? I'm not getting your point. > I'm with Hobart there. I have *never* had the problem that I was coding a branch to a data

Re: EQU * considered harmful

I very often use it to define location and length of a composite set of variables. Your END idea would not help me. And don’t we do plain constants like hash table size? Don’t think length is always known early enough. And bits in a flag byte? Rob On Wed, 1 Aug 2018 at 18:34, Steve Smith wrote:

Re: An idea I got when researching a bug - warnings when a specific register is changed

On 25 June 2018 at 21:49, Phil Smith III wrote: > > Seriously, l like it and would use it. I'd prefer it not be tied to USING > because there are other reasons to not use a register (I think; can't come > up with any offhand, but I feel like there are?). Maybe: > > I suppose there are plenty of

Re: Count Words?

On 17 June 2018 at 03:57, Farley, Peter x23353 wrote: > Didn't think of that, but you are probably right - pipeline stalls are > quite expensive and tough to benchmark. > But pipeline stalls at least are consistent and show in a profile, even though it may not show the exact spot. I find

Re: Pascal

On 2 February 2018 at 14:28, Martin Ward wrote: > > Incidentally, perl strings can be over 4GB in length: in fact, > any size which will will fit in memory (including swap space). > Just don't let the ASN.1 folks come closer, or you end up with variable length length

Re: Fair comparison C vs HLASM

On 2 February 2018 at 03:11, Paul Raulerson wrote: > > Timing is usually done with signal and/or semaphores - or better yet with > message > queues. :) > With 'relative timing' I mean the flow of records in two parallel paths, for example selecting a subset of the records

Re: Fair comparison C vs HLASM

On 1 February 2018 at 20:10, Paul Gilmartin < 0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote: > On 2018-02-01, at 10:28:47, Kirk Wolf wrote: > > > and you can also get a completion statusarray ("PIPESTATUS[i]") > > from a multi-stage pipe. > > > Valuable indeed. I often wish for it.

Re: Fair comparison C vs HLASM

On 1 February 2018 at 16:40, Paul Gilmartin < 0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote: > > with a multi-stream pipeline topology ... > > That restriction is a myth. C programs can deal with multi-stream > pipe topologies. In shell that requires named pipes. > Because CMS

Re: Fair comparison C vs HLASM

On 29 January 2018 at 20:16, Paul Gilmartin < 0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote: > On 2018-01-29, at 11:55:56, Seymour J Metz wrote: > > > While the DOS I/O was very device dependent, there was the DTFDI with > limited device independence. > > > Insofar as "device

Re: Fair comparison C vs HLASM

On 25 January 2018 at 10:18, Dave Wade wrote: > I don't know if Fortran H does loop unrolling, but some compilers that are > targeted at Vector Processors do. > FORTRAN can be a pig of a language though, especially with a poor > compiler. Even worse, on two dimensional

Re: Fair comparison C vs HLASM

On 24 January 2018 at 18:33, Charles Mills wrote: > > The reality is that cycle times are not getting any faster. A z14 does not > execute z10 machine instructions significantly (any?) faster than a z10. > The second sentence does not follow from the first one. While a single

Re: Fair comparison C vs HLASM

On 22 January 2018 at 07:47, Jon Perryman wrote: > I find it amazing how C programmers believe in the superiority despite > overwhelming evidence to the contrary. Surprisingly, the psychological term > for this is "motivated reasoning" and I never believed it until now.

Re: Address of a =LITERAL

On 14 December 2017 at 08:17, Windt, W.K.F. van der (Fred) < 0782fe4a8c02-dmarc-requ...@listserv.uga.edu> wrote: > > It surprises me that no one has pointed out that having complex tables > > assembled/compiled into a program is generally a Bad Idea. Almost always > > such tables have to be

Re: Any real need for sequence numbers in 73-80 any more?

On 12 December 2017 at 17:45, Paul Gilmartin < 0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote: > Perhaps not a great challenge. Long ago, I wrote a bimodal (XEDIT and > ISPF Edit) macro. It relied on a few interface subroutines: > Get a line, Put a line, UP, DOWN, SAVE, ... No

Re: Any real need for sequence numbers in 73-80 any more?

On 12 December 2017 at 16:53, Paul Gilmartin < 0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote: > > sequence numbers. I normally assemble within XEDIT using the listing to > > steer the editor to the first line causing the error. > > > Can you share? Can it be adapted for ISPF Edit? > >

Re: Any real need for sequence numbers in 73-80 any more?

On 11 December 2017 at 20:36, Dave Wade wrote: > As I generally only play with old versions of VM I don't have ISPF. In old > versions of VM and line numbers on the assembler source are integral to the > way the system is built. > So the build process keeps each change as

Re: Load module

You should really study the class material rather than asking others on the list. On Sat, 11 Nov 2017 at 20:20, Sudershan Ravi wrote: > How can I say that the module is dynamic or Static? where can I find the > info? >

Re: Rehabilitated TROT Routine (Was: Detection of Compile-Time Self-Modifying Code)

On 12 October 2017 at 08:03, Pieter Wiid wrote: > Correction: > > DOWHILE,TROT,R14,R2,B'0001',1 > ENDDO > > Constructs where evaluation of the condition has a side effect (or completely relies on the side effect) are often more a convenience to the writer than to the

Re: interesting, to me, new z14 instruction: BIC

And I thought the BIC instruction was for when you press hard, that you could write several cache lines at once :-)

Re: KMx vs PCC crypto instructions

On 10 August 2017 at 22:33, Farley, Peter x23353 < peter.far...@broadridge.com> wrote: > OT: I would disagree that ICSF is the "overall better choice". IMHO, if > you do not need unique Crypto Express co-processor functions or completely > and totally secure keys then ICSF is just wasted

Re: Question about CPUs

The term you are groping for here is "memory interlock". This was coined > by IBM in regard to the TS instruction in that it imposes a lock on its > target byte to prevent any other processor in the SMP configuration from > manipulating that byte until its operation is complete. > I believe the

Re: Structured programminng macros

On 15 May 2017 at 10:09, Pieter Wiid wrote: > Think about my example where you could have cards with or without an "*" > in col 1. > > First card - "*", so the "IF" branch is not taken, followed by > unconditional branch. > > next 5 cards the branch is taken, then another "*"

Re: Structured programminng macros

On 15 May 2017 at 08:41, Pieter Wiid wrote: > With the IF structure, given the normal ratio of comment to "real" data, > you will have a very high percentage of pipeline flush due to incorrect > branch prediction. > Why would prediction of a branch in a loop be notoriously

Re: 50 year old assembler code still running.

On 11 March 2017 at 13:52, Tony Thigpen wrote: > I am working on some REALLY old code. Some of the code has dates back in > 1967! The oldest date found is 5/9/67. > > This code is still running daily. That's as good as 50 years later. The > only reason we are touching the code

Re: EXECUTE Instruction and location of its target instruction

It's not like we would walk all the way to the location that "more far" is expensive. It's in the same cache line or it's not. I have a macro to generate the target in-line to ensure that HLASM knows the USING that applies to the target, accepting the fact that I sometimes need to branch over it.

Re: SIIS "issue" after upgrade to z13 machine.

On 12 November 2016 at 10:10, Philippe Cloarec wrote: > > Since we do talk of CPU cycles savings here I will check for AGI cases and > their resolution and try to implement instruction grouping as much I can. > > From my humble point this is a real topic and all z13

Re: SIIS "issue" after upgrade to z13 machine.

The example that I have seen was where the customer had a linkage model for small subroutines that used a static save area and local storage after a branch at the start of the program. That's painful for small routines because a lot of the code is in the same cache line and gets hit each time you

Re: Please use meaningful subject (was: ASSEMBLER-LIST Digest - 6 Jun 2016 to 20 Jun 2016 (#2016-62))

On 22 June 2016 at 09:48, Paul Gilmartin < 0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote: > On 2016-06-22, at 00:50, Rob van der Heij wrote: > > > > An interesting idea might be to sign up for the web interface at > > listserv.uga.edu and use that to res

Re: Please use meaningful subject (was: ASSEMBLER-LIST Digest - 6 Jun 2016 to 20 Jun 2016 (#2016-62))

On 22 June 2016 at 08:07, Peter Hunkeler wrote: > I'd appreciate people responding to digest message would take a little > care of adding a meaningful subject. And include some snippets of the text > you're referring to. > > -- > Peter Hunkeler > An interesting idea might be to

Re: Structured Programming Macros

I had the pleasure of doing a lot of work with the Structured Programming macros that we have for CMS Pipelines. Unlike the SPM from HLASM Toolkit, things like IF / THEN / ELSE and some expect the condition code to be produced by normal instructions, so the argument for IF is a condition code. I

Re: Structured Programming Macros

> Thanks, having had the privilege of developing code under VM/CMS in the > past I do have knowledge of the MACLIB format and would be comfortable > writing the needed Rexx to convert the libraries should I need them. > > Working them into the official development environment for approved use is

Re: *+n branches

you see it. We have HLASM to compute offsets, why make it harder? If writing the code slows you down, you need macros. --- Rob van der Heij z/VM Development, CMS Pipelines

Re: LZRG??? Does this mean that 56-bit addressing is a thing?

On 11 March 2015 at 16:41, Paul Gilmartin 0014e0e4a59b-dmarc-requ...@listserv.uga.edu wrote: On 2015-03-11, at 08:49, John McKown wrote: And POPCNT is another one. Why do I need to know the number of 1 bits in each individual byte in a GPR? Because CDC had it first? I suspect

Re: New Principles of Operation

Google got me the link as the 2nd hit... http://www-01.ibm.com/support/docview.wss?uid=isg2b9de5f05a9d57819852571c500428f9a On 9 March 2015 at 22:32, Jose Flores jflo...@gtsoftware.com wrote: Hi Abe, Can you provide the link? I googled it but found nothing regarding the -10. Thanks! Jose

Re: An Interesting Technique

On 16 February 2015 at 13:32, mar...@pi-sysprog.de wrote: Rob, it is rather unpleasant to find code store into the save area even in the middle of the code you can see, that it either uses r13 in the store (with no local save area) or R13+4 as field in a load and then the store to

Re: An Interesting Technique

On 15 February 2015 at 22:18, Bernd Oppolzer bernd.oppol...@t-online.de wrote: I have some criticism against this technique, because it turns the save area trace in the case of an abend pretty useless, because the EP address which was at the position 16(r13) before the return code was stored

Re: gas2asm package location? [was: RE: Announcing PCRE 8.36 port to native classic z/OS]

On 11 February 2015 at 15:21, Farley, Peter x23353 peter.far...@broadridge.com wrote: Thanks for the interesting link Rob. I found another reference to gas2asm at the CMS/TSO Pipelines page at Marist here: Ah, those were probably done after I explored the territory using a big brown bag

Re: Announcing PCRE 8.36 port to native classic z/OS

And for the deer that look into the other headlights, Rich Smrcina got it mostly running on CMS using John Hartmann's gas2asm efforts ( https://rvdheij.wordpress.com/tag/gas2asm/) So I crafted a pipeline stage around it... pipe query | split | pcre '^[A-Z]*[0-9]*[A-Z]$' | cons PIPINX086I On 11

Re: One more second

But the average installation with NTP / ETR running UTC would not even have to that, would they? NTP will pick up the extra second, and ETR will find the hardware clock ahead of time and slow it down for 8 hrs to align with the new wall clock time: UTC incl leap seconds. If you'd schedule the 1

Re: Replication factor of a group item

What is 11 times no string of 33 characters ? Are you sure you need 11 empty strings rather than 10 ? nnCL33 is nn times a field of type C and length 33. When nn is 0 you don't actually allocate but only align. Which is why you see 0F or 0D. But for type C there is no alignment... On 26

Re: Redesigning the Principles of Operation Manual

On 14 November 2014 08:39, Martin Packer martin_pac...@uk.ibm.com wrote: John, do you know if something akin to DCF is still used in the production of it? Or, better still, Bookie. I think Jonathan Scott thought not. But if so the conversion to HTML and then on (via modern web techniques)

Re: Redesigning the Principles of Operation Manual

And in case we need more distraction on a Friday night... It looks like the intern left too soon... ;-) If you think reading the PDF on your phone is hard, try the shiny new IBM Knowledge Center instead. Would have thought that with content managed like that, they could have made it accessible

Re: Redesigning the Principles of Operation Manual

On 13 November 2014 04:20, Mark Boonie boo...@us.ibm.com wrote: - No more bunching: Perhaps a reasonable suggestion. Bear in mind, though, that it would increase the repetitive nature of the document. Also, the need to ensure that similar instructions were documented similarly as much as

Re: 2GiB = address 4GiB

Yes, z/VM has a bar. With our first 64-bit version, there were some restrictions that virtual machine pages for guest I/O had to be under the bar. That was rather unpleasant for Linux that does not use dedicated memory areas as I/O buffer. It got crowded under the bar. And the 32-bit Linux s390

Re: 2GiB = address 4GiB

On 5 November 2014 16:32, John McKown john.archie.mck...@gmail.com wrote: On Wed, Nov 5, 2014 at 8:57 AM, Steve Smith sasd...@gmail.com wrote: It's important to note that the reservation of x'8000' through x'' is merely to help avoid addressing issues, as well-explained

Re: 2GiB = address 4GiB

. On 5 November 2014 22:22, Rob van der Heij rvdh...@gmail.com wrote: On 5 November 2014 16:32, John McKown john.archie.mck...@gmail.com wrote: On Wed, Nov 5, 2014 at 8:57 AM, Steve Smith sasd...@gmail.com wrote: It's important to note that the reservation of x'8000' through x'

Re: ML and Architecture Level Set

List ASSEMBLER-LIST@listserv.uga.edu wrote on 08/08/2014 05:39:23 PM: From: Rob van der Heij rvdh...@gmail.com To: ASSEMBLER-LIST@listserv.uga.edu Date: 08/08/2014 05:39 PM Subject: ML and Architecture Level Set Sent by: IBM Mainframe Assembler List ASSEMBLER-LIST@listserv.uga.edu

Re: ML and Architecture Level Set

Was wrong. It is available in an ESA virtual machine. Just as it says in the book. On Aug 9, 2014 8:46 AM, Rob van der Heij rvdh...@gmail.com wrote: This is what i expected. So my surprise that an ESA virtual machine on the z12 did not do it. Guess its only in SIE and not V/SIE On Aug 9, 2014

ML and Architecture Level Set

Folks, I am looking at the Principles of Operation telling me the ML and MLR that are flagged N3 in the summary. And the legend says: N3 Instruction is new in z/Architecture and has been added to ESA/390. Any RSY or RXY instructions still use the RSE or RXE format and 12-bit displacements in

Re: nuls vs. blank as padding characters

On 4 August 2014 22:07, John Gilmore jwgli...@gmail.com wrote: I have indeed come to suspect strongly that we are likely to disagree about most things. I will arrange a small public celebration when I find that we in fact agree about something significant. My impression was that the two of

Re: Local Time conversion to/from UTC Time

On 8 July 2014 14:29, John Gilmore jwgli...@gmail.com wrote: The z/Architecture TOD clock provides values trhat are analogous to International Atomic Time, TAI, ones, which are innocent of leap-second corrections. UTC values do contain these corrections, and IBM provides facilities for

Re: Out of Order and Superscalar - small experiment

On 3 June 2014 01:56, Robin Vowels robi...@dodo.com.au wrote: XR Rn,Rn is faster than SR. But does it matter? Such an instruction should be executed only once, and once only. It shouldn't be in the loop. So why is it faster? I suppose faster means it would allow more options for it to

Re: Out of Order and Superscalar - small experiment

On 3 June 2014 09:19, Robin Vowels robi...@dodo.com.au wrote: On 2 June 2014 19:56, Robin Vowels robi...@dodo.com.au wrote: From: Tony Harminc t...@harminc.com Sent: Tuesday, June 03, 2014 3:30 AM Is LHI Rn,0 faster than SR Rn,Rn? I'd expect them to be the same, but SR is half the size,

Out of Order and Superscalar - small experiment

I've been reading about it, but mostly ignored it as not too important for what I do. But... More recently I've been working on porting Linux gcc object code to CMS, and now that I needed a nice checksum routine, I figured I might take a popular open source checksum routine

Re: Out of Order and Superscalar - small experiment

On 2 June 2014 19:30, Tony Harminc t...@harminc.com wrote: Is LHI Rn,0 faster than SR Rn,Rn? I'd expect them to be the same, but SR is half the size, and so lessens the amount of i-cache used. The effect of the footprint is a challenge to measure, but that would also vote against unrolling

Re: MVCL

It seems to me you're making it harder than it is. Think we referred to base as the code base for branch instructions and for the target of ex. If you don't try baseless code you will have the literals often on the same base as the instructions. And maybe for the target of ex and one of the

Re: MVCL

On 21 May 2014 07:34, Robin Vowels robi...@dodo.com.au wrote: From: Ed Jaffe edja...@phoenixsoftware.com Sent: Wednesday, May 21, 2014 2:52 PM On 5/20/2014 8:44 PM, Robin Vowels wrote: I use MVCL a lot even for very small moves where the length is not known at assembly time. But I

Re: MVCL

So that is to say that the target does come out of the instruction cache (maybe using the shortcut on ec12). So it's not just for the reader to see the instruction in line with the same usings On May 21, 2014 5:37 PM, zMan zedgarhoo...@gmail.com wrote: P.S. That predates concerns about cache

CPU Measurement Facility Documentation

Lock me up when I say that consistent layout of documentation does not matter... ;-) I was reading SA23-2261-02 trying to make sense of the CPU MF counters. And looking at Page 5 which has the heading The CPU-Measurement Facility Extended Counters Definition for z10,z196/z114,zEC12 and lists

Re: Automatic reply: AUTO: Umberto Silvestri is prepared for DELETION (FREEZE)

On 11 March 2014 16:20, Steve Comstock st...@trainersfriend.com wrote: Great. Now we've got automatic replies to automatic replies. I was already concerned that the DST change got the best of the respected audience here, considering there was no reaction on a dozen of those mails. But then,

Re: ...DIGEST...

On 26 February 2014 03:42, zMan zedgarhoo...@gmail.com wrote: The latter. But I'd ask the first question differently: what mail software lets subscribers reply to individual digest articles WITHOUT requiring them to manually set the Subject: line? And even that approach has its limitations

Re: OT: SI units and precision

On 7 January 2014 23:35, Steve Smith sasd...@gmail.com wrote: An inch, a cup, a pound, a foot, a pint and a grain all have a relationship to the practical world that is much more useful than units based on the circumference of the earth. And while it was once somewhat difficult to convert

Re: OT: SI units and precision

On 6 January 2014 14:42, Baron Carter baron_car...@technologist.com wrote: When using the SI metric system we must be accurate in using the correct symbols. The symbol for kilometers is km not Km. Therefore kilometers per hour is km/h not Km/h. The SI system is made up of symbols not

Re: Base-less programming

John Hartmann's FPLOM library is on http://vm.marist.edu/~pipeline/#Runtimewhich might take some tinkering to shape it into something that can be used on other platforms than CMS. I like it a lot... -Rob On 4 December 2013 22:30, Tony Harminc t...@harminc.com wrote: On 4 December 2013 15:56,

Re: Specification exception on a z10

On 20 November 2013 09:50, Bernd Oppolzer bernd.oppol...@t-online.dewrote: KM is known to the machine - if not, this should be S0C1, not S0C6. But all function codes are disabled, so function code 18 is not known to the machine, so the S0C6. Is this correct? This is not very nice: there

Re: signum

On 24 October 2013 16:25, Farley, Peter x23353 peter.far...@broadridge.comwrote: Wow. I have occasionally been accused of using obscure, unmaintainable code in the name of efficiency, but that gubbins example and Rob's default parameter assignment parse make me look positively conservative.

Re: signum

On 25 October 2013 17:59, John Gilmore jwgli...@gmail.com wrote: Rob's macro FOOBAR is easy to improve, as in I don't disagree yet, but what's the improvement? It's a lot more code (though still less than what I inherited) and I agree the mnote is more verbose. But does it serve a purpose?

Re: Linear search vs binary

On 24 October 2013 02:43, Paul Gilmartin paulgboul...@aim.com wrote: The search may be terminated early (however infrequently) on discovering an exact match. But this requires an extra comparison if ternary results are unavailable (as they are in assembler -- is that sufficiently on-topic?)

Re: signum

On 24 October 2013 02:42, Tony Harminc t...@harminc.com wrote: On 23 October 2013 19:43, Paul Gilmartin paulgboul...@aim.com wrote: I have occasionally gotten flamboyant and coded such as: X = copies( 'gubbins', A==B ) /* instead of: */ if A==B then X = 'gubbins'

Re: Why is division by zero permitted?

Ask someone for a web browser and type google.com ;-) OS assembler language; 360, and december 1967 Many moons ago, a friend (who went to math school) showed me his scars and explained that it were evil that compilers could optimize in such a way that an attempt to divide by zero would go

Re: Linear search vs binary

On 24 October 2013 12:50, Don Higgins d...@higgins.net wrote: I see discussion about optimizing the binary search, but I don't see any discussion about optimizing linear search which might make it much faster than binary depending on the search history. Putting the last key found at front of

Re: signum (was: Linear search vs binary)

Since the machine architectures that came to mind all have this 3-state result after comparison, I expected the compiler to take advantage of it when I write something like if ( j k ) m = -1; else if (j k) m = 1; else m = 0; return m; A few surprises with gcc, like pretty dumb code

Re: signum (was: Linear search vs binary)

branches using the CC. I suppose my next attempt would have been a case statement using sign() Rob On 23 October 2013 12:25, robin robi...@dodo.com.au wrote: From: Rob van der Heij rvdh...@gmail.com Sent: Wednesday, October 23, 2013 8:12 PM Since the machine architectures that came

Re: Concatanate Bits Instruction?

On 4 August 2013 13:05, robin robi...@dodo.com.au wrote: Then double shift left by k bits. Then do an OI using EX to put in those k bits. Then double left shift again, this time by 8 bits and OI using EX. Continue thus if there are more bits I've done something similar with an 8-bit

Re: 3 job openings for mainframe Assembler/C programmers, dump readers

On 26 July 2013 00:44, Bernd Oppolzer bernd.oppol...@t-online.de wrote: Of course you can teach dump reading and debugging; Steve Comstock does it, I do it, and others do it as well. At least it gets them beyond the point where they claim it got a protection exception on a LR instruction ;-)

Re: Good Performing Code (Was: Millicode Instructions)

On 17 April 2013 07:34, Ed Jaffe edja...@phoenixsoftware.com wrote: On 4/16/2013 3:55 PM, Scott Ford wrote: I want to ask a question, in this day/age and processing power is it really worth being concerned about Assembler instructions speed ? I am not unbiased. My answer is exactly what

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