Re: [casper] pfb_coeff_gen_calc shifted sinc arguments

I’m very happy to hear that. I was working with the ATA taps which looked strange and lead me down this path. We probably saw the same thing and wound up at the same result— I’m just late to the party! Cheers, Nathan From: casper@lists.berkeley.edu on behalf of

Re: [casper] pfb_coeff_gen_calc shifted sinc arguments

and was pointed out to me by the late Frankin Antonio (lest I take credit for a level of detail-orientation I don't possess) On Thu, 30 May 2024, 01:46 Andrew Martens, wrote: > Hi Nathan > > This bug (if we are talking about the same one) was fixed in a commit 2 > years ago but has not made

Re: [casper] pfb_coeff_gen_calc shifted sinc arguments

Hi Andrew, Yes, that version corrects the issue I found. Thanks for confirming. Regards, Nathan From: casper@lists.berkeley.edu on behalf of Andrew Martens Sent: Thursday, May 30, 2024 12:46 AM To: casper@lists.berkeley.edu Subject: Re: [casper]

Re: [casper] pfb_coeff_gen_calc shifted sinc arguments

Hi Nathan This bug (if we are talking about the same one) was fixed in a commit 2 years ago but has not made it into the main repo yet. It was pointed out to me by Jack Hickish. For more info see https://github.com/ska-sa/mlib_devel/commit/702d962842b53f76ec661b27b1156679ccb71929 The fixed

[casper] pfb_coeff_gen_calc shifted sinc arguments

Hi all, I was comparing the coarse channelization response and taps from a CASPER instrument to other window design routines and noticed a small discrepancy comparing to pfb_coeff_gen_calc. The argument to the sinc to generate an ideal lowpass filter is typically -wc..wc. Different routines

Re: [casper] Adding new HW support for Red Pitaya SDRLab

Hi Jack, Thanks for your prompt response. That works great! Feel free to email me privately a link (assuming you can see my email address). No preference for platforms. Best, Will On Tuesday, May 21, 2024 at 8:42:05 PM UTC Jack Hickish wrote: > Hi Will, > > Sure -- how about 10am toronto

Re: [casper] Adding new HW support for Red Pitaya SDRLab

Hi Will, Sure -- how about 10am toronto time tomorrow? Cheers Jack On Tue, 21 May 2024 at 21:21, Will Taylor wrote: > Hi, > > I'm starting a project to add the tool-chain support for the 16-bit ADC, > 50Ohm version of Red Pitaya. I will need to add support for the board > itself and the ADC

[casper] Adding new HW support for Red Pitaya SDRLab

Hi, I'm starting a project to add the tool-chain support for the 16-bit ADC, 50Ohm version of Red Pitaya. I will need to add support for the board itself and the ADC peripheral (the DAC is identical to the 14-bit STEMLab Red Pitaya). I'm unclear on the best method to add this hardware

[casper] NEWSDR 2024 Event Registration

Hi All, I wanted to let you know that registration for the New England Workshop for Software Defined Radio (NEWSDR) is open! See below for links! NEWSDR 2024 will be held at Worcester Polytechnic Institute on May 30 and 31st. This event brings together SDR enthusiasts and researchers from New

Re: [casper] General GPIO

Thanks Jack! Sorry for the delay, I have been busy with other projects for a while. In fact we sorted out the problem which was because of another totally unrelated bug, so the GPIO approach worked from the start. So, for the record, to get previously undefined GPIO pins working you should

Re: [casper] General GPIO

On Mon, 11 Mar 2024 at 08:47, Kaj Wiik wrote: > Hi all, > > Somewhat related to the previous question: how to define and use (RFSoC) > pins as GPIOs via the gpio block? > > I noticed that group 'led' is in both gpio block mask and in .yaml but > e.g. there is 'pmod' group in rfsoc4x2.yaml but it

Re: [casper] Regarding 32 channel ADC channel calibration in ROACH2

Hi dan, I hope your reply regarding the FFT core will solve my problem. I will try this method. Thank you so much. Regarding the ADC calibration, I have calibrated a single 16 ADC card and it was successful. when i try to calibrate both of them at the same time, it is giving error. Thank

Re: [casper] Regarding 32 channel ADC channel calibration in ROACH2

hi sivasankar, you are correct, the biplex fft's also have multiple inputs, but they are used in a different way: instead of multiple time samples from a single real ADC to process higher data rates than the FFT clock rate, the biplex FFT's compute two or four FFTs simultaneously. e.g. you can

Re: [casper] Regarding 32 channel ADC channel calibration in ROACH2

Hi dan, Thank you for your immediate response. In the fft_biplex_real blocks also they have at least two simultaneous input paths. So how can I split the one channel ADC output stream(200MHz) into multiple paths to give it to FFT block? Even if i find a method to do that, It will reduce the

Re: [casper] Regarding 32 channel ADC channel calibration in ROACH2

hi sivakumar, for low sample rate FFT's (where the FPGA clock = sample rate), i suggest you consider: fft_biplex_real_2x (Real-sampled Biplex FFT, with Output Demuxed by 2) fft_biplex_real_4x

[casper] Regarding 32 channel ADC channel calibration in ROACH2

Dear Caspers, Currently I am facing an issue with 32 ADC channel calibration with ROACH2 rev2 board. The script for 16-ADC channel calibration is working fine and it has calibrated successfully. I have used the same script and changed the 16 ADC design to 32 ADC channel. I have selected

Re: [casper] Question about using DRAM for ADC Data Storage on RFSoC

Hi Yunfan, Access to the DRAM is not yet supported. It is something that we want to achieve, although not much work is being done on that at the moment. If working on making DRAM work is something that interests you we welcome contributions and can help get you started on the right path.

[casper] Question about using DRAM for ADC Data Storage on RFSoC

Dear CASPER Team, I want to know if it is possible to use the DRAM (total 8GB) on RFSoC to store the ADC sampling data. I have tried to switch the 'bitfiled_snapshot' block storage medium to 'DRAM' and it shows the problem that "There is no block name xps_library/dram", when I configured the

[casper] Re: MATLAB startsg startup Warning "Unable to resolve the name py.sys.path."

The solution is to perform these commands while activated into the environment. sudo apt-get -y install expat sudo apt install build-essential libssl-dev libffi-dev python3.8-dev On Thursday, March 14, 2024 at 9:41:08 PM UTC-4 Ken Semanov wrote: > The following error occurs during MATLAB

[casper] MATLAB startsg startup Warning "Unable to resolve the name py.sys.path."

The following error occurs during MATLAB start up, after activating the cfpga_env virtual environment and performing ./startsg Starting Model Composer Warning: Executing startup failed in matlabrc. This indicates a potentially serious problem in your MATLAB setup, which should be

Re: [casper] ZCU 208 PPS Input

Thanks, John. I am certainly not advocating using -es1. You have production silicon and the only way for the tools to accurately target the device in all aspects is to setup the tool with the correct information. We need that note and ability to support the correct device, thank you for that.

Re: [casper] ZCU 208 PPS Input

Hi Mitch, The -es1 removal in the yaml file was something that was brought up by colleagues of mine who have used zcu216s recently. When I did have issues with the 100 Gbe I looked into the Vivado project and found that the part number did have the -es1 tag so that's why I was suspecting that

Re: [casper] ZCU 208 PPS Input

Hi John, On Mar 12, 2024, at 10:00 AM, John Swoboda wrote: Hi Mitch, Thanks for the reply. The 100 Gbe is working fine on my end. I also was able to get the into my design. Great to hear! In terms of using the -es1 in the design files, I would suggest that this be noted in the tutorials

Re: [casper] ZCU 208 PPS Input

Hi Mitch, Thanks for the reply. The 100 Gbe is working fine on my end. I also was able to get the into my design. In terms of using the -es1 in the design files, I would suggest that this be noted in the tutorials that this could be an issue for people if they do not have a -es1 board and

[casper] General GPIO

Hi all, Somewhat related to the previous question: how to define and use (RFSoC) pins as GPIOs via the gpio block? I noticed that group 'led' is in both gpio block mask and in .yaml but e.g. there is 'pmod' group in rfsoc4x2.yaml but it is not seen in the gpio mask parameters. Can that group be

Re: [casper] ZCU 208 PPS Input

Hi John, Now I think the trick is you have to change the block parameters for the yellow block supplying the PPS to be single ended because I ran that and it got rid of my error since in the zcu208/216 use single LVCMOS18 instead of LVDS_25. Am I on the right track here? Yes, this is correct.

Re: [casper] VDIF Packetizer

Dear all,Very interested in this discussion and in both the VDIF and VITA49 packet formats for RFSoCs. Open-sourcing the blocks would definitely be welcome!Best,WaelSent from my iPhoneOn Mar 6, 2024, at 1:02 PM, Matthew Schiller wrote:While I haven't written it yet, I plan to write one capable

Re: [casper] VDIF Packetizer

While I haven't written it yet, I plan to write one capable of 400G by August 2024. Should be trivial to operate at 100G as well. I also plan to write one for VITA49.2. Matthew Schiller On Wed, Mar 6, 2024 at 3:46 PM Kaj Wiik wrote: > Hi Mayukh and all, > > I am developing a single dish

Re: [casper] VDIF Packetizer

Hi Mayukh and all, I am developing a single dish backend with RFSoC and extending that for VDIF streaming would be very interesting. Opening the source would be very welcome! Thanks, Kaj On Wed, 6 Mar 2024 at 22:21, Mayukh Bagchi wrote: > Hello Casperites, > > Hope you all are doing well. >

[casper] VDIF Packetizer

Hello Casperites, Hope you all are doing well. I have been working on an RFSoC-based backend for our BVEX (Balloon-borne VLBI Experiment) project. As a mobile K-band VLBI station we are using the RFSoC 4x2 for our IF stage for digitizing and storing the data. I have had a lot of help from the

[casper] PhD Opportunity in GPU/DSP

Hi everyone, (Apologies if you receive this via multiple distribution channels) Swinburne University, CSIRO, and Fourier Space Pty Ltd are advertising a PhD scholarship opportunity in the area of high performance digital signal processing for radio astronomy. This full-time PhD position will

Re: [casper] ClockConstraint arguments order

Hi Ken, In this case, ‘A’ is the name given to the clock constraint. ‘B’ is the net/pin name where this constraint is applied to. Please not that, in the design there should be a pin with the name ‘B’ in the current module. Depending on the tool you are using for verification, the TCL command

[casper] ClockConstraint arguments order

Say the xdc file required this line create_clock -period 3.000 -name A -waveform {0.000 1.500} -add [get_pins B] Where would the A and B be placed in the constructor of ClockConstraint? CC = ClockConstraint( signal=??, name=?? , freq=None , period=3.000, port_en=False, virtual_en=False,

[casper] NEWSDR 2024

Hi all, I'm on the committee that plans the New England Workshop for Software Defined Radio (NEWSDR). I can't recall if anyone from the CASPER community has participated in the past, but I would like to see that change! I would highly encourage anyone here to check out this workshop! Here's

[casper] SETI Institute Posdoc Scholarships

Hi all, For anyone interested, there are two postdoc scholarships at the SETI Institute currently accepting applications. One is in astrobiology, the other in technosignatures. See https://www.seti.org/postdoctoral-fellowships-seti-institute for more info! Cheers Jack -- You received this

Re: [casper] Problem with 10 GbE communication in ROACH-2

If I had to guess I would say this is another issue with casperfpga version incompatibility. Did you try using the casperfpga from that tutorials repository which at least _should_ have been tested with whatever bitstreams are in there --

回复: [casper] Question about the RFSoC Clock Configuration

Hi Bishnu and Mitch, Thank you so much for your help! I am very sorry I did not look at that before and only focused on the tutorial which have a snapshot for RFDC config that use 245.76MHz. I have now solved the question and the ADC status is 15 with PLL working! Now I can figure out the fix

[casper][roach2] pfb blocks doesn't allow to change parameters

Dear Caspers, Currently, I am experimenting with roach2 boards and trying to compile the ‘tut_spec’ with small modifications but have an issue with Casper DSP block ‘pfb_fir_real’. I can add it from the library to the model but cannot seem to change the parameters. Once I ied to change any

Re: [casper] Problem with 10 GbE communication in ROACH-2

I'd suggest start by trying the casperfpga which is included as a git submodule in the tutorials repo -- https://github.com/casper-astro/casperfpga/tree/a88f9af0b16e6a12fe51884d29c162e76e7c21a6 I'm guessing this is substantially older than the one you are using, and may be python2.7 only. As

Re: [casper] Question about the RFSoC Clock Configuration

Hi Yufan, Sorry this did not resolve your issues. I believe I see the issue now and am sorry I did not catch this earlier. In your previous screenshots for the configuration of the RFDC the PLL reference clock input is set to 245.76 MHz when it should be set to 491.52 MHz. The LMX file you are

Re: [casper] Problem with 10 GbE communication in ROACH-2

Hi Jack, Thanks for the reply. I am using the below version of casperfpga. casperfpga 0.4.4.dev1336+py38.276ee44 Do I need to change the casperfpga version? Sivasankar.S On Wed, Feb 28, 2024 at 9:28 PM Jack Hickish wrote: > I think this might be a mismatch between the

Re: [casper] Problem with 10 GbE communication in ROACH-2

I think this might be a mismatch between the Ethernet memory map compiled into the firmware vs expected by casperfpga. What version of casperfpga are you using? Cheers Jack On Wed, 28 Feb 2024 at 15:25, Sivakumar Sivasankar wrote: > Dear Caspers, > I am a research student at FIU,

[casper] DSP Engineer opening at Thai National Radio Observatory

Hi Everyone, I would like to share this opening for DSP engineer at National Astronomical Research Institute of Thailand (NARIT). The institute has various ongoing projects to develop digital signal proecessing capabilities for use at the Thai National Radio Observatory using SKARAB, Alveo,

[casper] Re: AD9082 JESD204C oneshot_sync

Hi All, To hopefully save anyone going through the same pain, this behaviour only occurs when using the AD9082 in ADC-only (i.e. JESD TX only) mode, and it turns out that in this mode one still has to set the DAC JESD Receiver (0x4AE, for anyone from the future reading this) to JESD204C mode even

[casper] AD9082 JESD204C oneshot_sync

Hi casperites, I'm hoping someone can help me out of a JESD204C subclass 1 synchronization hell. There is a long version of this story, but the short version is: 1. I have an AD9082-FMCA-EBZ development board (hosting an AD9082 ADC+DAC chip) being used with an iWave ZU11 development board. 2.

Re: [casper] Question about the RFSoC Clock Configuration

Hi Yunfan, Could you please try the `m2021a-dev` branch of `mlib_devel` and see if it helps resolve your issues with setting up the clock configuration? This development branch has new changes and adjustments that make simpler and

Re: [casper] Fault LED is switched on when I start the Roach2

Hi Dave, I appreciate your response. Now the fault led has switched off. But I couldn't see anything on the terminal using serial connection. I am getting balckscree with a cursor only. I showed some documentations about debricking the board. Even though, I couldn't get some of the scripts

Re: [casper] Connection Problem on RFSoC 4*2 Board

Hi Yunfan, Some debugging suggestions below: > On Feb 8, 2024, at 12:50 PM, Yunfan Zhang wrote: > > Dear CASPER Team, > > I am a student who is trying to create the CASPER environment for our RFSoC > 4*2 board. > > The problem I have currently encountered that, I cannot actually connect

Re: [casper] Fault LED is switched on when I start the Roach2

Maybe somebody has a clearer recollection than I do, but I think the “fault” LED on ROACH2 boards was a bit unreliable/meaningless as an indicator of an actual fault. HTH, Dave > On Feb 9, 2024, at 00:16, Sivakumar Sivasankar wrote: > > Dear Caspers, > Now the fault led is off. But I

[casper] Fault LED is switched on when I start the Roach2

Dear Caspers, I am a research student at FIU. Currently working with Roach2 boards. I have a problem with roach2 board. when I connect it, the fault LED is also switching on. I have connected the board with an ethernet also. But it is not communicating since the RX/TX led is not

[casper] ROACH2 Recovering using Xilinx JTAG cable

Hello everyone! My name is Alikhan Talipbayev, currently I am senior year student at Nazarbayev University. I am doing my Capstone project where I use ROACH2 REV2 to build fpga readout system for mkids. Last month I tried to update ROACH2 using one tutorial I found in mail archive, at the

Re: [casper] Connecting issues with Roach2 from Corr

Dear Jack, Than you so much for the response. I referred the documents that you sent. Initially we were trying with minicom to the booting process but it didn't work. Then we used putty and did the soloboot through that. It has worked now. Our Roach2 is up and running now. Thanks again for

Re: [casper] Connecting issues with Roach2 from Corr

Howdy, I think probably the first thing to do is make sure the board really is booting, and running a katcp server on port 7147. If the board side of the connection is working, you should be able to connect to the ROACH over telnet: ``` telnet 10.42.0.226 7147 ?help ``` If this does not

[casper] Connecting issues with Roach2 from Corr

Dear Caspers, I am a research student in FIU . Currently I am working on the setup of a Roach2 board. Since I have installed MATLAB 2013b, Xilinx ISE 14.7 and compiled the tutorial 1 design. Now I have the .fpg and .bof file. Currently i am trying to blast the compiled files into the

[casper] Custom yellow block does not call add_build_dir_source()

YellowBlock classes have no access to the Jasper build directory. One possible way around this is to override method add_build_dir_source() , as is done in lines 110-111 in this file,

[casper] Fwd: Postdoc Position in "Experimental Radio Interferometry"

Apologies for any repeat postings. Forwarding in case any casperites may be interested. Regards, -- Forwarded message - From: Matthias Kadler Date: Fri, Jan 26, 2024 at 12:41 AM Subject: Fwd: Postdoc Position in "Experimental Radio Interferometry" I am currently looking for a

[casper] Status of hardware JTAG testing.

The following file appears to be the beginnings of a hardware testing flow for AXI-Lite interface, in the spirit of the JTAG-to-AXI-Master IP. It seems to be missing some key components (yellow blocks and .m mask).

[casper] 4th URSI Atlantic Radio Science Conference (URSI AT-RASC) 2024

Hi all, This is a FINAL call for papers for a session on "Real-time Processing for Radio Astronomy" for the 4th Atlantic Radio Science Meeting (URSI AT-RASC) in Gran Canaria, Spain, 19-24 May 2024. Information on the conference is at: https://www.atrasc.com/home.php We hope you will

[casper] Commissioning Scientist Positions at SKA (Aus)

Hi all, There are a number of commissioning scientist positions available for SKA Low - see link: https://recruitment.skao.int/vacancy/commissioning-scientists-545230.html Contact the SKAO for further information and feel free to pass on to others. Regards, Francois -- You received this

[casper] Call for Papers: 4th URSI Atlantic Radio Science Conference (URSI AT-RASC) 2024

Hi all, This is a call for papers for a session on "real-time processing for radio astronomy" for the 4th Atlantic Radio Science Meeting (URSI AT-RASC) in Gran Canaria, Spain, 19-24 May 2024. Information on the conference is at: https://www.atrasc.com/home.php We hope you will consider

Re: [casper] sourcecode for YAML parsing

Hi Ken, The process starts in `mlib_devel/jasper_library/casper_platform.py` where the yaml file is desearlized into an object that is then carried through the flow. The pin information in that object is then used in other places. Mitch On Jan 3, 2024, at 3:53 PM, Ken Semanov wrote: Which

[casper] sourcecode for YAML parsing

Which part of the CASPER source code parses the "pins:" section of the yaml files found in mlib_devel/jasper_library/platforms/*.yaml ? -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop

Re: [casper] Create a full PL pdi for AMD Versal SoC

Hi Wei, The issue might be that the PDI you are attempting to use with `fpga_manager` is considered a “base” PDI that is part of the BOOT PDI image loaded by the PLM during boot. Since this PDI contains the PLM/PPU information these cores cannot be reconfigured at run time (as indicated by

[casper] Create a full PL pdi for AMD Versal SoC

Hi All, Happy new year! I'm working on the 400G Ethernet test on vpk180 board, which is based on the AMD Versal SoC chip. To do the test remotely (and also to port the casper toolflow on this board later), I created a Ubuntu image for

[casper] FPGA boards - Donation.

Dear CASPER team, Seasons greetings.. I am looking for CASPER FPGA board (ROACH 1 or 2)+ 2 Ch ADC. If anyone willing to donate it. Please let us know. Will write you more about the project in detail. Thanks and regards Indrajit -- You received this message because you are subscribed to

Re: [casper] ROACH auto shuts off after 20 mins of running

Not an expert at this at all, but it could be that the ATX power supply has gone bad, or has had the connection to its sensor line (usually a bridge between pins 15 and 16) come loose . ATX has a sensor that will cause the power supply to go into standby, so you could check that connection, or try

[casper] ROACH auto shuts off after 20 mins of running

Hello, we have a ROACH that we use as a correlator. It has been working great for the last 8 years or so but randomly while running the other day it shut itself off and now will not stay powered on for longer than around 20 minutes before auto shutting off again. The ROACH works completely

[casper] Call for Papers: 4th URSI Atlantic Radio Science Conference (URSI AT-RASC) 2024

Hi all, This is a call for papers for a session on "real-time processing for radio astronomy" for the 4th Atlantic Radio Science Meeting (URSI AT-RASC) in Gran Canaria, Spain, 19-24 May 2024. Information on the conference is at: https://www.atrasc.com/home.php We hope you will consider

Re: [casper] Questions about the Casper RFDC block in Simulink

Hi Sebastian, It is not possible on RFSoC 4x2 to switch from Dual to Quad tile. The architecture is fixed and inherent to the FPGA. So this would be true of all RFSoC platforms. A very brief overview of this is in the RFSoC

[casper] CASPER Postdoctoral Fellow Opportunity at UC Berkeley

Hi Everyone, We are advertising a new CASPER postdoc position at UC Berkeley, working on the development of hardware and software instrumentation for the community. https://aprecruit.berkeley.edu/JPF04224 Please feel free to send this on to anyone who may be interested. Note that the

Re: [casper] Failed to build Casperfpga

Hey Bishnu, I back Jonathon's suggestion - although I'm fairly sure that I got away with installing python3-dev and then just gcc, not the entire build-essentials package, when I recently did a clean install. I also vaguely recall having to manually install Cython too: $python3 -m pip install

Re: [casper] Failed to build Casperfpga

Hi Bishnu, It looks like the culprit is progska - which is a c program included in the library for programming the SKARAB boards. You could manually remove the dependency (you won't need it for rfsoc work) but it may be easier to install the required os packages. You will almost certainly need

Re: [casper] Failed to build Casperfpga

Hi Bishnu, I vaguely remember stumbling into this, the problem was a broken Linux release of Matlab. I found this from my notes: Ubuntu 20 comes with gcc 7.x to 9.x versions by default; you need to either install gcc 6.x manually or create a symbolic link using the following sudo commands: sudo

Re: [casper] Help with setting up RFSoC

Hi Heystek, That's wonderful news, congrats! I found that getting the toolchain working is very hard and tedious, working with it is fun! :-) Also, it should be noted that 99% of the setup problems are from Python, Matlab, and Vivado and not from the CASPER toolflow itself. Good luck with your

Re: [casper] Help with casperfpga / RFSoC

Hi Emiliano, On boot, the CASPER RFSoC image is expecting to be connected to a network where a DHCP server is running. This can be changed, but is the default behavior. From the information you provided it appears that there is no DHCP server that is offering IP addresses. In your screenshoot

RE: [casper] state of the art single bit correlators

Yes, thank you, Dan, I realise much more than just the right number of I/O pins, Cheers, Neil From: casper@lists.berkeley.edu On Behalf Of Dan Werthimer Sent: 14 November 2023 22:01 To: casper@lists.berkeley.edu Subject: Re: [casper] state of the art single bit correlators hi neil,

Re: [casper] state of the art single bit correlators

hi neil, thanks for this research on FPGA LVDS pair resources. as you know, just because an FPGA has 1152 pairs at 1.4 Gb/sec, doesn't mean you can input and correlate1152 antennas at 700 MHz bandwidth (real sampling), or 576 antennas at 1.4 GHz bandwidth (complex sampling), as the FPGA fabric

RE: [casper] state of the art single bit correlators

Hi Dan, Quite right! Xilinx(AMD) do the VIRTEXTM-7 XC7V2000T with a maximum of 576 differential I/O pairs, the XC7VX1140T with a maximum of 528 Differential I/O pairs, and the VIRTEXTM ULTRASCALE XCVU440 with a maximum of 648 differential HP I/O pairs. Altera (Intel) do the Stratix 10

Re: [casper] Help with setting up RFSoC

Hey Mitch. Thank you for the reply. The Python version that my system is returning is 3.7.13. Should I rather use Python 3.8? I have noticed that matlab2021a does not support python3.9. Thank you - Heystek Grobler 0832721009

Re: [casper] Help with setting up RFSoC

Hi Haystek, This most likely is a python version conflict. When you activate your Python environment, what is the version of Python that `python -V` returns? For me, my casper dev env returns Python 3.8.2. The second tutorial incorporates the RFDC yellow block. When the back end tool

Re: [casper] state of the art single bit correlators

Kristian, This piqued my interest as I've been talking with a research group that wants to do exactly this for fast optical fiber detonation cameras. Do you have any direct experience with using switch optical transceivers connected to fiber lines for sensing, or has anyone already done this?

RE: [casper] state of the art single bit correlators

Certainly a great read, many thanks! From: 'Jonathan Weintroub' via casper@lists.berkeley.edu Sent: 13 November 2023 13:59 To: casper@lists.berkeley.edu Subject: Re: [casper] state of the art single bit correlators Hi Neil, Dan, That would be the thesis of the brilliant Curtis Mead,

Re: [casper] state of the art single bit correlators

I would imagine if you wanted to go to crazy bandwidths you could even use optical transceivers on switches as single bit digitisers... On Mon, 13 Nov 2023, 14:56 Dan Werthimer, wrote: > > hi neil, > > paul horowitz, at harvard, had a PhD student who characterized and used > FPGA LVDS inputs as

Re: [casper] state of the art single bit correlators

Hi Neil, Dan, That would be the thesis of the brilliant Curtis Mead, downloadable here: https://dash.harvard.edu/handle/1/11158246 Jono > On Nov 13, 2023, at 8:56 AM, Dan Werthimer wrote: > > > hi neil, > > paul horowitz, at harvard, had a PhD student who characterized and used FPGA >

Re: [casper] state of the art single bit correlators

hi neil, paul horowitz, at harvard, had a PhD student who characterized and used FPGA LVDS inputs as ADC's for a seti experiment. that thesis is available, and i think there is a publication as well - paul will know. best wishes, dan On Mon, Nov 13, 2023 at 12:48 AM salmon.na via

RE: [casper] state of the art single bit correlators

Hi Dan, Just one further question, in terms of building a single bit cross-correlator on an FPGA, exploiting differential LVDS pair for single bit digitisation, might there be a suitable reference for this that I can include in the paper and an IEEE transaction journal? Many thanks,

Re: [casper] state of the art single bit correlators

Hi Dan, that's great information - very helpful.many thanks, best wishes  NeilSent from my Galaxy Original message From: Dan Werthimer Date: 11/11/2023 21:51 (GMT+00:00) To: casper@lists.berkeley.edu Subject: Re: [casper] state of the art single bit correlators hi neil, i

Re: [casper] state of the art single bit correlators

hi neil, i don't think waiting 5 years will help: there will be faster serdes - the current chips handle ~5 Tbit/sec and that will probably double every two years, but that won't help you because you need other fpga's to convert your slow 1 gsps data rate to 100, 200, 400, or 800 Gbit/sec serial.

Re: [casper] state of the art single bit correlators

hi neil, regarding how big an FPGA you need: let's assume 512 complex signals at 1 Gbit/sec real, 1 Gbit/sec imag: you'll need ~512^2 / 2 = 2^17 complex multipliers, which can be made from 2^18 four bit look up tables, assuming a 500 MHz FPGA clock. for the accumulators, you need 2^18 adders,

RE: [casper] state of the art single bit correlators

Hi Dan, Those are attractive looking numbers. Is it possible to say how that might scale over the next 5-years, will the number of pins go up, faster than the processing speed, or the number of gate on board? Is it likely to remain I/O bound of compute bound? Many thanks, Neil

Re: [casper] state of the art single bit correlators

hi neil, for a single frequency channel correlator (continuum correlator), an XF architecture (lag correlator) is the way to go, the number of antennas in your correlator will likely be limited by the number of signals you can get into the FPGA. (the correlator will be I/O bound, not compute

RE: [casper] state of the art single bit correlators

Many thanks Dan, cheers, Neil From: salmon.na via casper@lists.berkeley.edu Sent: 11 November 2023 20:43 To: casper@lists.berkeley.edu Subject: RE: [casper] state of the art single bit correlators Thanks Dan, Yes, one antenna for one receiver, and there is only one frequency channel,

RE: [casper] state of the art single bit correlators

Thanks Dan, Yes, one antenna for one receiver, and there is only one frequency channel, and a single polarisation, so quite a simple configuration. A good idea to use differential inputs as single bit ADCs. So the FX correlator looks the better architecture. So are you saying

Re: [casper] state of the art single bit correlators

hi niel, oops, i just re-read your email and my undestanding is that you are digitizing complex IQ data at 1 Gsps for I and 1 Gsps for Q (1 GHz bandwidth). so please cut my numbers in my email from a few minutes ago (appended below) in half: you can get ~512 signals digitized (or brought in

Re: [casper] state of the art single bit correlators

hi neil, by number of receiver channels, i presume you mean number of antennas? are these single or dual polarization? how many spectral channels do you need in your correlator ? for a large number of spectral channels, you'll likely want to use an FX architecture correlator (not XF). in an FX

RE: [EXTERNAL] [casper] state of the art single bit correlators

Hi Neil, For your 1-bit correlation, are you going to implement a lag correlator? If so, then your logic could be: * ISERDES operating at 1Gbps sampling the complex-valued baseband * 4-bits at 250MHz or 8-bits at 125MHz inside the FPGA * Logic to perform 4-bits or 8-bits digital

[casper] state of the art single bit correlators

For a paper on non-radioastronomy aperture synthesis technology I need to know how many receiver channels can run into an almost top of the range FPGA optimally designed single-bit cross-correlator running a 2 Gbps. So each receiver is digitised (sine and cosine) in single bits 1 Gbps. I'm

Re: [casper] ROACH 1 root file system image

Hi Indrajit, Thanks a million! Very much appreciated. Best wishes, Colm On Sat, 28 Oct 2023 at 08:24, Indrajit Barve wrote: > Dear Dr Colm Bracken, > > I shared the image file here. > > > https://drive.google.com/file/d/13MJ5ad3qi0VIggE98t6lKSJPtqeOScb7/view?usp=drivesdk > > Thanks and

Re: [casper] Help with setting up RFSoC

Hi Heystek, I think it better if you used 20.04. Is the first machine (18.04) the one that crashes and that when you have had Matlab working that comes from your second machine (20.04)? I just did some tests and was able to reproduce your issue with generating the dtbo. In your xilinx device

Re: [casper] Help with setting up RFSoC

Heystek, Matlab crashing: You had said earlier that you were on Ubuntu 20.04? Is this still the case? Toolflow error: Can you send me the commit hash for your current head of the Xilinx device tree repo? Mitch > On Oct 31, 2023, at 1:52 PM, Heystek Grobler wrote: > > > Hey Kaj, Mitch,

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