Re: [coreboot] Thread derailment

there, I looked for improvements, which some people provided to me. I would like to thank them! I'll give you a good advice: better start working, you talk too much! ;-) Thank you, Zoran Stojsavljevic ___ On Wed, May 2, 2018 at 7:45 PM, Nico Huber <nic...@gmx.de> wrote: > O

Re: [coreboot] Thread derailment

Hello David, > We need open dialogue with vendors more than we need obnoxious > commentary from certain individuals. I see... I hit hard INTEL... Again! And INTEL is NOT (at all) happy about that, I can read between the lines. :-) It is NOT matter of open dialogue with vendors. It is matter of

Re: [coreboot] Why do we have FSP-S

> Our recommendation for some time has been a mix -- arm64 client devices > (laptops, tablets, etc.) and ppc64el servers. With those two, you can > replace x86 entirely if you don't have proprietary software in your > environment. With all due respect, this is the discussion about Coreboot going

Re: [coreboot] Why do we have FSP-S

higher class ship > with AMI UEFI and AMI BMC. Plus they contain their own magic blobs, > some akin to the ME. ARM64 is not a panacea either; OpenPOWER's > actually shipping open POWER9 systems right now with source code. Why > not go down that route? > > On 04/30/2018 09:32

Re: [coreboot] Why do we have FSP-S

The magic formula to all this, INTEL improvement, is everything contained in only one word: ARM64! This is a very politically correct Civil Approach, don't you agree?! ;-) Best Regards. Zoran Stojsavljevic ___ On Tue, May 1, 2018 at 1:46 AM, David Hendricks <dhendri...@fb.com>

Re: [coreboot] Why do we have FSP-S

Nico, Aaron, You are just, with this desperate chit-chat, fueling INTEL's big EGO. Please, continue to do so! INTEL, at the end of the day, will thank you for that! :-)) Zoran ___ On Mon, Apr 30, 2018 at 4:48 PM, Nico Huber wrote: > Hello Aaron, > > thanks for your reply. >

Re: [coreboot] Why do we have FSP-S

Nico (Huber), > So it's time for an FSP3.0 that was designed with the community, I'd say. You talk (in this email, at least) too much. :-)) I wish you a Good Luck. You'll need it (all the luck in this and others' Worlds). And much more than that! Even Captain Jean-Luc Picard (Star Trek Next

Re: [coreboot] Coreboot events 2018

>When will the conference program be known? Also interested in this item. 90% I'll attend the event, at least for one or possible two days! Zoran ___ On Mon, Apr 23, 2018 at 9:34 PM, Alexey Borovikov wrote: > Thank! > When will it be possible to find out what reports

Re: [coreboot] How to handle vbt.bin

Lot af talk, no work... All of this is already architected. I already did some ground work here (also parts assembled from Coreboot responses approximately a year ago): https://en.wikipedia.org/wiki/Coreboot/VBT The thing which needs to be done ASAP (in *RED*): 1. Make a "decompiler" that

Re: [coreboot] How to handle vbt.bin

https://en.wikipedia.org/wiki/Coreboot/VBT Zoran ___ On Sun, Apr 15, 2018 at 12:48 PM, Patrick Rudolph wrote: > On Thu, 2018-04-05 at 11:34 -0500, Matt DeVillier wrote: > > On Thu, Apr 5, 2018 at 11:29 AM, Nico Huber wrote: > > > On 05.04.2018 18:15,

Re: [coreboot] BIOS/CoreBoot/UBOOT

> Is it possible to go from BIOS/UEFI to UBOOT (on-board)? How? Actually, since you are using, after all, YOCTO Project to build your BDX-DE BSP, you can freely use U-Boot, if Bin Meng (U-Boot BSP maintainer) already integrated BDX-DE/Camelback CRB's FSP into U-Boot. If? Bin, Did you integrate

Re: [coreboot] Minnowboard

t will hang > before giving any output. > > Best regards > Michael > > > > > > Ursprüngliche Nachricht > Von: Zoran Stojsavljevic <zoran.stojsavlje...@gmail.com> > Datum: 21.03.18 13:23 (GMT+01:00) > An: Daniel Wagner <w...

Re: [coreboot] Minnowboard

> It shows under position of ME. ME for Bay Trail is called TXE. I need to intervene here. TXE is a security engine, doing in HW MD5, sha256, sha1024 signatures, and more. It is used for locking and factory programming the device, also. This has nothing to do with ME. ME is completely different

Re: [coreboot] Minnowboard

Hello Daniel, You need to properly build Coreboot, integrating BYT-I (as I recall minnow board) FSP, and the info about BYT-I FSP you can find here: https://github.com/IntelFsp/FSP Zoran ___ On Wed, Mar 21, 2018 at 12:47 PM, Daniel Wagner wrote: > Hi, > > I would like to

Re: [coreboot] FOSDEM 2018 beverage round?

Hello Peter, > Timothy already summed everything up pretty well, but I'll go to the > beer event at Delirium on Friday evening before FOSDEM and am happy > to have a chat. Be prepared - Delirium gets real busy. Please, after spending many drinking rounds at Delirium, next morning, watch out for

Re: [coreboot] x86 validation suite

Nothing simpler, my dear friend Ron. Do the following steps (on your Linux/Debian/Ubuntu/OpenSUSE/RHEL/Fedora/Centos): [1] Go to YOCTO project: https://www.yoctoproject.org [2] Go to the following site: https://www.yoctoproject.org/downloads [3] Do git clone Rocko: git clone -b rocko

Re: [coreboot] BDX-DE PCI init fail

rg/GRUB2 > > > By the way, I saw following message in the log. Should I choose >> NodeManager Mode? Do you know what's different? > > >> >>[SPS] SiliconEnabling Mode >> >> >> Thanks. >> -Hilbert >> >> -Original Message- >>

Re: [coreboot] BDX-DE PCI init fail

cy. If I use GRUB2 as payload, it just > hangs there. I am still struggling on this :( > By the way, I saw following message in the log. Should I choose NodeManager > Mode? Do you know what's different? > >>>[SPS] SiliconEnabling Mode > > > Thanks. > -Hilbert > &g

Re: [coreboot] BDX-DE PCI init fail

> Booting from Hard Disk... > Booting from :7c00 It is booting from the thirty second Kbyte of HDD (sector 62, sector 0 is MBR), where the beginning of GRUB Legacy is placed/implanted, called core.img or similar name. https://wiki.archlinux.org/index.php/GRUB_Legacy Well, you have succeed,

Re: [coreboot] BDX-DE PCI init fail

> grub> Yup, you have reached the GRUB2 shell. I have no idea what the underlying system is yuo have done this? UEFI or Legacy? If UEFI, this USB will NOT work for Coreboot + SeaBIOS. If Legacy, then I have no idea why it does not work (it should)!? If UEFI, then you might reconsider

Re: [coreboot] BDX-DE PCI init fail

> 1. There is a 8GB DDR4 memory in my system. YUP, it is clearly visible from e820. I do not know too much about setup parameters for DDRs, so it is hard for me to get the DDRX (X) from MRC logs you have attached at the beginning of this email thread. I assumed DDR3. > 2. I don't attach any

Re: [coreboot] BDX-DE PCI init fail

Hello Hilbert, I looked into the Coreboot logs (SeaBIOS ones, you have posted recently). My comments with: <<=== ___ ress ESC for boot menu. Searching bootorder for: HALT Space available for UMB: c2000-ee800, f6940-f70d0 Returned 192512 bytes of ZoneHigh

Re: [coreboot] BDX-DE PCI init fail

Hello Hilbert, After work (somewhere around 19:00 PM CET), I'll look into your logs. Please, stay tuned. I am simply sold out, and have no time for anything else... I will have some advises for you, hopefully! Zoran ___ On Mon, Jan 8, 2018 at 11:57 AM, Hilbert Tu(杜睿哲_Pegatron)

Re: [coreboot] 16 GPUs on one board

s. Mostly GTX 1070's. > > On an interesting note, one of my oldest motherboards, a Gigabyte > GA-970A-UD3 will boot with all 8 cards, but gives me the no VGA beep code. > Serial console for the win! > > Is this just a BIOS level issue? Or is there some hardware component

Re: [coreboot] 16 GPUs on one board

> I am totally off the deep end and don't know where else to turn > for help/advice. I am trying to get 16 GPU's on one motherboard. H. Yet another crypto currencies miner. ;-) > Whenever I attach more then 3~5 GPU's to a single motherboard, > it fails to post. To make matters worse, my

Re: [coreboot] BDX-DE PCI init fail

> ... I am not sure if is a side effect or just a new issue. Do you have any > recommendation about the reboot? [1] The complete boot log is beneficial as far as you have progressed... Isn't it? But you can also try SeaBIOS as payload (let go with simple ones), and see how far you'll go with it?

Re: [coreboot] BDX-DE PCI init fail

YES, U R correct. BDX-DE supoosed to be SoC, as I now recall. It was once upon a time/a long time back, about 2.5 to 3 years ago I played with this stuff. You supposed NOT to use anything beneath 0x50663 (forget 0x50661/2). I have no idea why you are using PPR 0x50663, the production part (PR) is

Re: [coreboot] BDX-DE PCI init fail

started to reboot again after jumping to boot > code as attached. I use U-Boot as payload. If grub was used, it just hanged > there. Did you have same condition before? Thanks. > > > > -Hilbert > > > > From: David Hendricks [mailto:david.hendri...@gmail.com] > Sent

Re: [coreboot] soc/intel/braswell for cherrytrail ?

Hello Peter, ATOM Cherrytrail is well known code name for CCG creations (retail target space). ATOM Braswell is an IOTG creation (embedded marketing space), and it comes with some Cherrytrail enhancements (silicon packaging, which goes from -40C to +85C - retail is from 0C to +70C). As I recall.

Re: [coreboot] BDX-DE PCI init fail

Tu(杜睿哲_Pegatron) > Sent: Tuesday, January 02, 2018 9:41 AM > To: 'Zoran Stojsavljevic' > Cc: David Hendricks; coreboot@coreboot.org > Subject: Re: [coreboot] BDX-DE PCI init fail > > Hi Zoran, > > The log was just at following link: > http://mail.coreboot.org/pip

Re: [coreboot] Coreboot with an UEFI payload to boot (Clover) an Thinkpad X230 Hackintosh

g like this (you need to figure it out what do you need at the serial end: male or female): https://www.staples.de/content/images/product/5869644_1_xnl.jpg Zoran On Tue, Jan 2, 2018 at 1:44 PM, my First name is Test And my last Name is iPation <testipat...@live.com> wrote: > > > On 01

Re: [coreboot] Coreboot with an UEFI payload to boot (Clover) an Thinkpad X230 Hackintosh

lect both. And of course Grub2 build —with-plaform=coreboot > cannot boot Clover (nor macOS). > > So for now, I’m stuck.. Maybe I’ll try Coreboot/Seabios/Duet(Tianocore) > > > Thanks Zoran. > > > > > From: Zoran Stojsavljevic <zoran.stojsavlje...@gmail.com> >

Re: [coreboot] How to properly conform with GPLv2 for Coreboot and SeaBIOS on an embedded system

iemens Industrial (2011-2016). Werner, thank you very much for all hard work and contribution you brought and will continue to bring to Coreboot, and lessons/knowledge you unselfishly gave to me/us here! Zoran Stojsavljevic ___ On Mon, Jan 1, 2018 at 2:00 AM, David Hendricks <dav

Re: [coreboot] Doubt about SPD init in Skylake

> The system must initialize some arrays before initializing > the SPD in order to execute FspMemoryInit. I do not know > what these arrays do, and how do I get these values when > porting new motherboard. It is, actually, vice versa (SPD is used for the IMC initialization). Serial Presence

Re: [coreboot] BDX-DE PCI init fail

> I still have same issue even tried to comment out > the 1f.3 device in ./src/mainboard/intel/camel- > backmountain_fsp/devicetree.cb then rebuild coreboot. You wrote that you submitted the log. Is this the full log? I doubt. I do NOT see physical memory layout as well as MTRR layout. Could

Re: [coreboot] Coreboot with an UEFI payload to boot (Clover) an Thinkpad X230 Hackintosh

wapping drives with UEFI compatible OSes. Your choice. :-) Zoran On Fri, Dec 29, 2017 at 7:58 PM, my First name is Test And my last Name is iPation <testipat...@live.com> wrote: > > > > > > From: Zoran Stojsavljevic <zoran.stojsavlje...@gmail.com> > Sent: Friday, Dec

Re: [coreboot] Coreboot with an UEFI payload to boot (Clover) an Thinkpad X230 Hackintosh

> Hi, I have a Thinkpad X230 with stock Bios,booting > macOS High Sierra, using Clover EFI boot loader. > And it's working great! Then I've went through the > process of installing Coreboot/Seabios + Ubuntu on > another disk, and it works like a charm too! However, > I would like to use

Re: [coreboot] Coreboot Purism BIOS is free? open?

isters there, undocumented, which are outlined in C-Specs, NOT all of them??? The only proper way how to solve this problem is to force INTEL to publicly release C-Specs for each and every CORE and ATOM families, which is equivalent to force NSA to release their deepest secrets to the public. Good Luck

Re: [coreboot] Coreboot Purism BIOS is free? open?

Hello Youness, With all due respect, you write too long emails, trying to defend Purism. Lot of yours argument I do not buy. Some of them I do. But, hey, this is what you/Purism have/has to offer, and this is a sort of fair deal. We all know what you are offering, in regards to x86, so let it

Re: [coreboot] anyone know what happened here?

ote: > Hi Zoran, > > please stop sending HTML emails. Your mails are often very hard to > view. Especially the quotations are completely messed up by your MUA > when you play with the font settings. > > On 22.12.2017 10:38, Zoran Stojsavljevic wrote: >> Nice. So now we have Ubuntu I

Re: [coreboot] anyone know what happened here?

> > > On Dec 21, 2017 10:51 PM, "Zoran Stojsavljevic" < > zoran.stojsavlje...@gmail.com> wrote: > > > from what I recall, *the driver was trying to be responsible and lock > SPI write access by default, but due to the* > *> off-by-one, ended up setting th

Re: [coreboot] anyone know what happened here?

> from what I recall, *the driver was trying to be responsible and lock SPI write access by default, but due to the* *> off-by-one, ended up setting the 'inverse' bit on the 2nd status register of some chips, which reversed the RO* *> and RW regions of the chip*. This naturally led to the EFI

Re: [coreboot] coreboot support for Minnowboard Turbot E3845

il.com> wrote: > Hey, > > I extracted 906 from original BIOS. > > But it still hangs on after POST 0x92 the same with 907. > > Aren't there any possibilities to get more debug information out of FSP? > > > Best Regards > > Michael > > > > > Am

Re: [coreboot] Disabling Intel ME 11 via undocumented mode

devill...@gmail.com> wrote: > On Fri, Dec 15, 2017 at 10:23 AM, Zoran Stojsavljevic < > zoran.stojsavlje...@gmail.com> wrote: > >> IME (I is typo) = ME . >> > > pretty sure the I is for Intel ;-) > > (or, at least that's how I've seen it referenced elsewhere

Re: [coreboot] Disabling Intel ME 11 via undocumented mode

IME (I is typo) = ME . Zoran On Fri, Dec 15, 2017 at 5:14 PM, Gregg Levine wrote: > Hello! > (I'm working from the office today on a library computer...) > My regular laptop might be wearing one of those dratted things. But > before we start confusing people further,

Re: [coreboot] Disabling Intel ME 11 via undocumented mode

> According to Positive Technologies, on Skylake and higher (like the > Purism machines) the kernel loads the BUP, and the HAP bit only disables > the normal userspace processes This is very good observation. Let us look again into the unknown code, compressed by Huffman (unknown tables):

Re: [coreboot] Hardware vendors offering systems with Intel ME disabled

e UEFI shell (I do NOT care about password protection, as it does NOT exist at all). Zoran On Fri, Dec 8, 2017 at 4:26 PM, awokd <aw...@elude.in> wrote: > On Fri, December 8, 2017 4:44 am, Zoran Stojsavljevic wrote: > > Let me try again to state what I stated before, with some new ins

Re: [coreboot] Disabling Intel ME 11 via undocumented mode

atory core with signed > firmware can be. > > [1] https://twitter.com/rootkovska/status/938458875522666497 > > On 12/08/2017 07:51 AM, Zoran Stojsavljevic wrote: > > Disabling Intel ME 11 via undocumented mode > > http://blog.ptsecurity.com/2017/08/disabling-intel-me.ht

[coreboot] Disabling Intel ME 11 via undocumented mode

Disabling Intel ME 11 via undocumented mode http://blog.ptsecurity.com/2017/08/disabling-intel-me.html I just managed (few hours ago) to read this article (way after replying to previous thread about Dell HAP, I read only few intro paragraphs)... It is, after all, amazing how far these two

Re: [coreboot] Hardware vendors offering systems with Intel ME disabled

Let me try again to state what I stated before, with some new insides, because Tim brought the new equation: HAP into this discussion. HAP - High Assurance Platform is long known (I know it from 2014), and its purpose, introduced by INTEL ME team was to disable ME as an application in INTEL

Re: [coreboot] usbd_req_re_enumerate

I can try to help here. But what you wrote here is not enough. What info is required here, is (significantly) more, then you wrote here. I'll try to make some ad-hoc systematic approach. :-) Phase 1: [1] What PC/CPU you are using for this purpose (as much detailed info as possible: make. year,

Re: [coreboot] Blank screen during boot and max CPU fan speed for ASUS KGPE-D16

ran On Wed, Dec 6, 2017 at 6:56 AM, taii...@gmx.com <taii...@gmx.com> wrote: > On 12/06/2017 12:35 AM, Zoran Stojsavljevic wrote: > > The full speed fan is normal. These are server boards and coreboot >>> *purposefully sets the fans to full speed until the OS boots* and can &g

Re: [coreboot] Blank screen during boot and max CPU fan speed for ASUS KGPE-D16

> The full speed fan is normal. These are server boards and coreboot > *purposefully sets the fans to full speed until the OS boots* and can take > over fan control duties via 'fancontrol' [1] or a similar application. > Note that the 'w83795' kernel module is required for this to work. Correct

Re: [coreboot] Blank screen during boot and max CPU fan speed for ASUS KGPE-D16

> - Memory: 16x 4 GB = 64 GB Corsair DDR3-1600 SDRAM (CMZ32GX3M8X1600C9) I will try shot in the dark, since I have no idea about AMD architecture. Seems that you have 8-memory channels architecture, And being you I will start reducing amount of memory to see if anything changes. Would first do 8x

Re: [coreboot] freebsd

According to this picture: https://upload.wikimedia.org/wikipedia/commons/7/77/Unix_history-simple.svg Seems that FreeBSD takes much slower development than Linux. Thus it is much more stable, it seems. Since my best take on it is that there are 10x or maybe even 100x developers on Linux. I see

Re: [coreboot] freebsd

> I contact you soon about freebsd, *because linux is not a good solution to solve my goal*. Why? What is your goal, Vincenzo? Zoran On Sun, Dec 3, 2017 at 6:28 PM, Vincenzo Di Salvo < ingegneriafore...@alice.it> wrote: > Hello guys, > > > > thanks very much for your replies. I've contacted

Re: [coreboot] Is Goryachy's JTAG hack a chance for free firmware ?

U will execute whatever you place in the flash, and it's IgorS>> up to you whether to implement signing checks or not. Thank you, Igor, for chime-in/participating! :-) Zoran ___ On Thu, Nov 30, 2017 at 6:54 PM, Enrico Weigelt, metux IT consult < i...@metux.net> wrote: > On 30.1

Re: [coreboot] Is Goryachy's JTAG hack a chance for free firmware ?

> I believe some day soon we will see a POWER laptop, even 5 years ago people would say that something like TALOS 2 couldn't be done and look where we are now! As my best understanding is, POWER is done by IBM (if I am not mistaken), and as I also know IBM got rid of their fabs long time ago.

Re: [coreboot] Is Goryachy's JTAG hack a chance for free firmware ?

> If i'm correct, the ME firmware (or parts of it) is signed, and > the CPU won't run (or switches off) if signatures don't match. I have no idea how it works for non INTEL architectures. I do know how it works for INTEL. You can fully use UEFI BIOS without any signatures. With so-called slim TXE

Re: [coreboot] Lenovo G505s AMD Hardware Virtualization

> Last resort is to flash back the OEM image but I'm hoping to avoid that. I would suggest to do this step now. As interim step, Then you can verify everything you are trying to do with Coreboot. The first and obvious step is to check for MCU using dmesg, if any exists. If yes, the next step,

Re: [coreboot] Creating PIRQ table

> Try to boot linux in legacy mode (enable CSM and set all boot options to legacy mode)... For this to happen (to boot Linux in legacy mode with CSM set in BIOS), such Linux must be installed with BIOS already using Legacy/with CSM mode set. It is impossible to set CSM mode in UEFI BIOS, and

Re: [coreboot] blobs: is there a reason for intel microcode version 20150121?

> And if you ask Intel employees about it, they just ignore you. In 99,9% of cases, asking INTEL employees about anything is just pure waste of the time and effort! IMHO! Zoran On Tue, Nov 21, 2017 at 7:33 PM, Nico Huber wrote: > Hi Martin, > > On 21.11.2017 09:31, Martin

Re: [coreboot] blobs: is there a reason for intel microcode version 20150121?

for one, who is smart, I gave even redundant info. ;-) Good Luck, Zoran Stojsavljevic PS. Please, google what MCU is (Micro Code Unit and purpose of it), I am too lazy to write about it! ___ On Tue, Nov 21, 2017 at 1:48 PM, Martin Kepplinger <mart...@posteo.de> wrote: > Am 21.11.201

Re: [coreboot] blobs: is there a reason for intel microcode version 20150121?

> I know very little about it really. It may well be potentially bad to simply use the latest version, > but in case it's really only because nobody did it, I might prepare a patch to use > downloadmirror.intel.com/27337/eng/microcode-20171117.tgz instead (someday, after > I testing it on my

Re: [coreboot] how to Compile apollolake soc

First email thread to read ([coreboot] Intel Leaf Hill Coreboot Trouble): https://mail.coreboot.org/pipermail/coreboot/2017-September/085210.html Second community thread to read (to get the idea about APL-I IFWI): https://embedded.communities.intel.com/thread/13129 Please, let us know if

Re: [coreboot] Problems changing payload on Intel Leaf Hill

> The vbt.dat (5kB) is need by GOP driver. But we haven’t done anything with that yet. Mario, Your English is much better, as I remembered it. Way! ;-) And from me the present/gift for/to the cause: https://en.wikipedia.org/wiki/Coreboot/VBT Zoran On Mon, Nov 6, 2017 at 10:32 AM,

Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

ressed you here, directly)!? And, yes, I am also involved. In this mess. Not running away from my woes! https://www.youtube.com/watch?v=R8y6DJAeolo Zoran ___ On Fri, Nov 3, 2017 at 8:20 PM, Zoran Stojsavljevic < zoran.stojsavlje...@gmail.com> wrote: > > I don't understand your no

Re: [coreboot] [VERY IMPORTANT] Announcement regarding Apollo Lake Coreboot building

> Zoran, and others, > > I wanted to build coreboot for APL CRP too. Tried to compile but failed at last command I think. First email thread to read ([coreboot] Intel Leaf Hill Coreboot Trouble): https://mail.coreboot.org/pipermail/coreboot/2017-September/085210.html Second community thread

Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

ent! Redesigned APIs, completely. ;-) It seems that I cleared it all, didn't I? Good Luck with the sporadic solutions (whatever works the best/at all in particular cases)! Zoran On Fri, Nov 3, 2017 at 2:48 PM, ron minnich <rminn...@gmail.com> wrote: > > > On Fri, Nov 3, 2017 at 5:54 AM Z

Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

Hello Wolfgang, Let me make it very productive... I know you will NOT like it (but I do NOT care, after what you did answer to me)! Your guy Stefan is here, asking for a help. Stefan got the straight answer: FSP/Coreboot (intermingled), then U_Boot as payload... You got that? What do you want

Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

. But you all should think what I really wrote here... Please, think it through??? Thank you, Zoran Stojsavljevic ___ On Fri, Nov 3, 2017 at 4:32 AM, Alexander Couzens <lyn...@fe80.eu> wrote: > Hi Stefan, > > we have two versions in the tree > a) fsp baytrail > b) non

Re: [coreboot] Problems changing payload on Intel Leaf Hill

>> ahwan writes >> Please advise, thank you. Mario (Werner), You should offer to this guy job (Siemens Motion Control) in DE (Bayern). He is tough guy, as I read/percept. I am (dead) serious. Zoran Stojsavljevic On Fri, Nov 3, 2017 at 8:37 AM, ahW@n via coreboot <coreboot@core

Re: [coreboot] New bugtracker/wiki registration process - please do not use freenode irc servers

> Those people are providing great diversity for having a non centralized TOR network. In sincere hope that TOR network will change (for the much better) state of Humanity, as it appears not to be in great shape in these modern times, after all! Zoran On Tue, Oct 31, 2017 at 3:50 PM,

Re: [coreboot] Does S3 work on Haswell boards?

but “systemctl suspend” works exactly the > same. USB wakeup doesn't work at all for me. I wake system with power > button. > > > From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] > Sent: Tuesday, October 31, 2017 10:19 AM > To: Аладышев Константин > Cc: Core

Re: [coreboot] Does S3 work on Haswell boards?

t your kernel version and results here. Hope this helps. Best Regards, Zoran Stojsavljevic ___ On Mon, Oct 30, 2017 at 4:49 PM, Аладышев Константин <aladys...@nicevt.ru> wrote: > I have problem with S3 mode on Haswell board. Everything is fine if S3 time > is very

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

- datasheet.pdf (Chapter 4.0 Power Management) I hope this can help... Somehow [*this time without attachment, since Coreboot mailer blocked me*] Zoran On Fri, Oct 27, 2017 at 7:09 PM, Zoran Stojsavljevic < zoran.stojsavlje...@gmail.com> wrote: > I'll try (boldly, unfortunately) to help here...

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

. And you, GOOGLE guys... Should think a bit beyond Reality. You should... (I am damn serious)! Zoran Stojsavljevic On Thu, Oct 19, 2017 at 4:56 PM, Аладышев Константин <aladys...@nicevt.ru> wrote: > No, unfortunately this option by itself doesn’t help. > > > > I guess my minimal h

Re: [coreboot] Possibility to tear electrically out the Bios chip

). Please, stay tuned, it'll take a time! Zoran Stojsavljevic On Fri, Oct 13, 2017 at 8:37 AM, ingegneriafore...@alice.it < ingegneriafore...@alice.it> wrote: > Hello everybody, > > please, has some of you ripped out the BIOS chip from the motherboard when > the pc is power

Re: [coreboot] greetings and laptop questions

ize the risk. > > Sorry for my part of starting this heated debate. > > And thanks again to all for the insight! > > Jim > > > > > > On Wed, Oct 11, 2017 at 5:52 PM, Zoran Stojsavljevic < > zoran.stojsavlje...@gmail.com> wrote: > >> > let's

Re: [coreboot] greetings and laptop questions

ssence. For TRUE purposes (I could NOT be blackmailed, never ever)! Sorry to be Honest Straight! Zoran Stojsavljevic On Wed, Oct 11, 2017 at 5:43 PM, ron minnich <rminn...@gmail.com> wrote: > let's pause this discussion until the new mailing list is up, and then > move it there, ok? This is n

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

described earlier commit that solves my USB problem is 3d9545c and it > was merged in kernel 3.5 > > So in this terminology: > Old kernels: <3.5 > Modern kernels: >=3.5 > > From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] > Sent: Tuesday, October 10, 2017

Re: [coreboot] greetings and laptop questions

e of sand in the desert of big IT companies' dishonesty! Zoran Stojsavljevic On Wed, Oct 11, 2017 at 12:57 AM, Nico Huber <nic...@gmx.de> wrote: > On 10.10.2017 20:02, Youness Alaoui wrote: > >> So my conclusion, Purism draws customers from other Linux supporting > >&

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

s about working with old kernels > > From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] > Sent: Tuesday, October 10, 2017 9:48 AM > To: Аладышев Константин > Cc: coreboot > Subject: Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards > > Hello Kost

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

> I'm going to try the hack to disable xhci, as suggested by Zoran and Аладышев's earlier email. You might try both variants. Do not forget, both ehci and xhci hubs are on different clocking domains, so you can set only one at the time (no workaround/circumventing tricks). I would advise to try

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

Hello Kostja, We already had this discussion a while ago, didn't we? https://mail.coreboot.org/pipermail/coreboot/2016-December/082772.html (BTW, ATOM BYT has exactly the same problem) Zoran On Mon, Oct 9, 2017 at 11:58 AM, Аладышев Константин wrote: > I try to port

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

Potihon6ky rebjatiski... Tiho! Daite mne vremja razobratsja! Thank you, Zoran On Mon, Oct 9, 2017 at 11:58 AM, Аладышев Константин wrote: > I try to port coreboot on boards with Haswell CPU and Lynxpoint LP chipset > (IBASE IB908AF-4650 board, DFI HU968) and I've

Re: [coreboot] greetings and laptop questions

> I am looking at a new laptop, and one of my options is a Dell Precision 7510 (I like the quad-core and loads of RAM available) > but I would like to not use a vendor BIOS. I see... SKL-S -> Intel® Core™ i7-6820HQ INTEL claims on these babies to have the following:

Re: [coreboot] Ability to remotely debug the grub menu in case of boot failure

> as always, your other other choice is to use linux in flash as a bootstrap, and then have the full spectrum of x-over-network solutions that you get from that. That's my new (old) approach nowadays. Hello Ron, As my best understanding, Ron, you would like to have Linux kernel with initramfs as

[coreboot] Fwd: [U-Boot] Broadwell-DE bare metal

booting U-Boot data in-between! ;-) Very interesting observation, I should say. Waiting for unwinding the ball. Zoran -- Forwarded message -- From: Zoran Stojsavljevic <zoran.stojsavlje...@gmail.com> Date: Thu, Oct 5, 2017 at 1:27 PM Subject: Re: [U-Boot] Broadwell-DE bare

Re: [coreboot] Broadwell-DE NS FSP not support

tion, “6 months for skilled person” J Maybe I > should try BIOS/UEFI first. > > > > -Hilbert > > > > *From:* Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] > *Sent:* Wednesday, October 04, 2017 7:57 PM > *To:* Hilbert Tu(杜睿哲_Pegatron) > *Cc:* coreboot@coreb

Re: [coreboot] Broadwell-DE NS FSP not support

cent thinking, Zoran ___ On Wed, Oct 4, 2017 at 2:30 PM, Piotr Król <piotr.k...@3mdeb.com> wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA512 > > > > On 10/04/2017 01:56 PM, Zoran Stojsavljevic wrote: > > Hello Hilbert, > > Hi Zoran, > > > &

Re: [coreboot] Broadwell-DE NS FSP not support

Hello Hilbert, There is none FSP for BDW-DE? Are you sure?? And how did you conclude that??? Here is the answer: https://github.com/IntelFsp/FSP Intel® Xeon® Processor D Product Family (formerly Broadwell-DE, Compliant with FSP v1.0 Specification) Broadwell-DE: git clone -b Broadwell-DE

Re: [coreboot] Intel Leaf Hill Coreboot Trouble

s seconday bootloader in this case. Either use Coreboot, either U-boot, you do not need both! IMHO. Best Regards, Zoran Stojsavljevic ___ On Thu, Sep 28, 2017 at 6:13 PM, Cameron Craig <cameron.cr...@exterity.com> wrote: > Hi Zoran, > > > > Thanks for the advice, I had a glimpse a

Re: [coreboot] Intel Leaf Hill Coreboot Trouble

Since I really want to help, and I do not have any time left for Coreboot (since I am fully/200% devoted to Fedora/RHEL/kernel.org and YOCTO), three kludge thinking from me (APL-I supposed to be my get_to_the_rich_pals_vehicle in Y2015, but mortally crashed somewhere in the process - For Good)!:

Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works

es of log, where 64bit EDKII fails). Hope this helps...?! Good luck! :-) Zoran Stojsavljevic ___ On Fri, Sep 22, 2017 at 8:46 AM, Patrick Georgi via coreboot < coreboot@coreboot.org> wrote: > 2017-09-22 3:33 GMT+02:00 Melissa Yi <hu...@celestica.com>: > >Anyone can giv

Re: [coreboot] About Paging, Realmode and what is going on

scratch with the COMPLETE embedded solution for 2 to 3 weeks. Mini com express for around 20 to 100 EUR a piece? Please, could you try to do this with INTEL ATOM or CORE in this time for this price? ;-) Zoran Stojsavljevic On Thu, Sep 7, 2017 at 2:23 AM, ron minnich <rminn...@gmail.com> wrote: > The or

Re: [coreboot] About Paging, Realmode and what is going on

> Hint: on x86 it's essentially one billion instructions before you can even think about using RAM, much less loading the payload. This is why everybody using INTEL silicon do have FSP as A MUST (instead SEC+PEI). And this is why CORE CPU creations (2C+) have > 500 million gates per silicon.

Re: [coreboot] About Paging, Realmode and what is going on

> But a bootloader built as a payload could also be built to use BIOS > interfaces. GRUB is one example of this. Let us assume the following configuration: FSP -> Coreboot -> Payload: GRUB2 -> Linux No legacy interrupts, correct? So, what is this for the architecture? CSM? UEFI look alike? I

Re: [coreboot] INT 13, real mode, block write commands and coreboot

> is there a way to disable this BIOS function? More precisely, coreboot can be set to avoid > receiving commands from GRUB and Ubuntu KERNEL? If you build the following structure (please, do understand that this is very high level of presentation, which does not reflect reality 100%) on x86

Re: [coreboot] REPLY: INT 13H

> I don't see a reason why it should be impossible to abolish Real Mode, Segmentation and basically everything beside Long-Mode > and virtual 32 Bit-mode. This is why: https://en.wikipedia.org/wiki/Itanium > The Operating-System-Manufactures would need a bit of time to change their operating

  1   2   3   4   >