[coreboot] KGPE-D16 coreboot support open call

] https://github.com/osresearch/heads/issues/719 -- Piotr Król Founder and Chief Executive Officer GPG: B2EE71E967AA9E4C https://3mdeb.com | @3mdeb_com OpenPGP_signature Description: OpenPGP digital signature ___ coreboot mailing list -- coreboot

[coreboot] Re: RFC: On testing and reporting how well coreboot does on real hardware

approach as ultimate solution for coreboot, but rather show how other OSS projects solved the same problem. Of course we may need something more sophisticated, but more sophisticated example needs more resources. Best Regards, -- Piotr Król Founder and Chief Executive Officer GPG: B2EE

[coreboot] Re: RFC: On testing and reporting how well coreboot does on real hardware

fwupd they would be able to seamlessly deliver alternative firmware to their devices including updates. Best Regards, -- Piotr Król Embedded Systems Consultant GPG: B2EE71E967AA9E4C https://3mdeb.com | @3mdeb_com OpenPGP_signature Description: OpenPGP digital signature

[coreboot] Re: [RFC] How should we manage tree-wide changes?

On 5/10/21 1:45 PM, Paul Menzel wrote: > Dear Piotr, > > > Am 10.05.21 um 10:51 schrieb Piotr Król: > >> On 5/8/21 9:24 AM, Paul Menzel wrote: > >>> Am 28.04.21 um 00:38 schrieb Piotr Król: >> >> (...) >> >>>> This is one part o

[coreboot] Re: [RFC] How should we manage tree-wide changes?

On 5/8/21 9:24 AM, Paul Menzel wrote: > Dear Piotr, Hi Paul, > > > Thank you for bringing up these issues. > > Am 28.04.21 um 00:38 schrieb Piotr Król: (...) >> This is one part of the problem, other is specifications compatibility >> where ACPI is one that

[coreboot] Re: [RFC] How should we manage tree-wide changes?

ion to push any solution. What I tried to do was to bring 3mdeb perspective related to gerrit documentation proposal and discuss how problems we see can be addressed. > > On 06.05.21 00:13, Piotr Król wrote: >> There are many reasons for rebasing or updating firmware to name few >> sec

[coreboot] Re: [RFC] How should we manage tree-wide changes?

On 5/6/21 2:43 PM, Patrick Georgi wrote: > Am Do., 6. Mai 2021 um 14:03 Uhr schrieb Piotr Król > mailto:piotr.k...@3mdeb.com>>: > > If 3mdeb maintains some boards, we already testing those and would be > glad to hook, in secure way, to patch testing sys

[coreboot] Re: [RFC] How should we manage tree-wide changes?

stable branch > maintainers to pick that up. We could probably do something similar. > But we still need someone setting up and maintaining the branch first. > I think Linux model is not bad and seem to work for many projects. My point is not sudden, another dramatic switch to new wa

[coreboot] Re: [RFC] How should we manage tree-wide changes?

d like > that but others not so much. And if I'm flipping the arguments in a > function that's only used 2 or 3 times in the whole tree, it's kind of > overkill to write an spatch. > +1 Best Regards, -- Piotr Król Embedded Systems Consultant GPG: B2EE71E967AA9E4C https://3mdeb.

[coreboot] Re: Building Coreboot with Nix

sion. Topics was so popular that we added it to official Dasharo Trolling Topics List: https://docs.dasharo.com/osf-trolling-list/build_process/ Best Regards, -- Piotr Król Embedded Systems Consultant GPG: B2EE71E967AA9E4C https://3mdeb.com | @3mdeb_com _

[coreboot] Re: [RFC] How should we manage tree-wide changes?

a larger forum to make sure that > we find rough consensus across the community before a decision is made > on how to proceed here. Best Regards, -- Piotr Król Embedded Systems Consultant GPG: B2EE71E967AA9E4C https://3mdeb.com | @3mdeb_com OpenPGP_signature Description: OpenPGP digital sig

[coreboot] Re: About support for my netbook

ably only companies that have CNDA with Intel can still obtain those, but who knows maybe it lays on some server somewhere. Best Regards, -- Piotr Król Embedded Systems Consultant GPG: B2EE71E967AA9E4C https://3mdeb.com | @3mdeb_com ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Initial mainboard commit - minimal requirements and completion criteria

l. Many thanks for your contribution. Best Regards, -- Piotr Król Embedded Systems Consultant GPG: B2EE71E967AA9E4C https://3mdeb.com | @3mdeb_com ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Initial mainboard commit - minimal requirements and completion criteria

wrong we will fix that. We believe this is a little bit bigger problem that should be addressed by coreboot leaders since it reflects the healthiness of the community and agenda of participating entities. Best Regards, -- Piotr Król Embedded Systems Consultant GPG: B2EE71E967A

[coreboot] KGPE-D16 maintainership

we would be very grateful. Please copy other people and share this post wherever is necessary to keep this platform alive. Positive feedback will help things rolling. Best Regards, - -- Piotr Król Embedded Systems Consultant GPG: B2EE71E967AA9E4C https://3mdeb.com | @3mdeb_com -BEGIN PGP

[coreboot] Re: Status on Dell OptiPlex 7010 support

back since it has problems now. [1] https://cloud.3mdeb.com/index.php/s/DJxMQ6YFeee4J3Q [2] https://review.coreboot.org/c/coreboot/+/25095 Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -BEGIN PGP SIGNATURE

[coreboot] Re: Status on Dell OptiPlex 7010 support

ource=ig_web_button_share_sheet [2] https://www.instagram.com/p/BsA7zX3FxzT/?utm_source=ig_web_button_share_sheet [3] https://www.win-raid.com/t1053f39-Optiplex-and-VPro-AMT-ME.html#msg18356 [4] https://cloud.3mdeb.com/index.php/s/XxyRfeKRxWNTJ7P Best Regards

[coreboot] Re: Status on Dell OptiPlex 7010 support

pt8jFX5Y/?utm_source=ig_web_button_share_ sheet [3] https://twitter.com/pietrushnic/status/1071384206603939843 [4] https://www.netcheif.com/Reviews/PLA5405/PDF/MX25L3206E.pdf [5] http://www.macronix.com/Lists/Datasheet/Attachments/7370/MX25L6406E,%203 V,%2064Mb,%20v1.9.pdf Best Regards, - --

[coreboot] Re: Porting Qotom Q355G4 SBC (similar to Librem 13)

2 how Intel can keep source code secret - I'm not a lawyer, but sounds very weird and I believe we can address that through some channels in Intel. Can you point me to document in Intel Research and Design Center so I can look at that? I have correct CNDA signed with Intel. Best Regards, -- Piot

[coreboot] Re: Porting Qotom Q355G4 SBC (similar to Librem 13)

On 12/28/18 3:48 AM, John Keates wrote: >> >> On 28 Dec 2018, at 00:36, Piotr Król wrote: >> >> On 8/19/18 4:06 PM, John Keates wrote: >>> Hi, Hi John, > The extra pointers are helpful indeed. I have started searches for > ULV and mobile series

[coreboot] Re: Status on Dell OptiPlex 7010 support

nitely rise priority of that work. Best Regards, -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

_BINARIES="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/cpu_ microcode_blob.bin" Of course I had to create correct directory in blobs repository. Thanks for help. I know see other issues in log that I have to deal with, but I think I can deal with those now. Best Regard

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

PC Engines we had to create our own method [1]. I wonder what would be correct way for tha t. [1] https://github.com/pcengines/coreboot/pull/132/files Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -BEGIN PGP SIGNATURE- iQIzBAEBCAAdFiEE4DCbL

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

I'm reading/using get_blobs incorrectly? Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -BEGIN PGP SIGNATURE- iQIzBAEBCgAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAlr+2MIACgkQsu5x6Weq nkyEDw//b22uIdIB1kOJ4PcskG5MENENbYs/yTSoGqd21Lz0smbjSi/SeYejngcX 8cScWDTDgrxm

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 05/17/2018 06:08 PM, Piotr Król wrote: Hi Subrata, > >> 3. Please check if BIOS_RESET_CPL is already set prior to >> setting 0x121 MSR Refer to code enable_bios_reset_cpl > > Will do that and get back with re

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

aster/blobs/librem_skl/get_blo bs.sh Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -BEGIN PGP SIGNATURE- iQIzBAEBCAAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAlr9qOQACgkQsu5x6Weq nkzDFw//fb4JhiIszuDEbULkASGS9zJu++i+X

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

be relevant, but I don't have serial enabled and all logs are dumped to SPI. I'm not sure if SPI controller interrupts may affect this anyhow. Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -B

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 05/17/2018 01:51 PM, Banik, Subrata wrote: > Piotr Król, Hi Subrata, > > I have submitted a patch today to overcome some AP timeout issue. > > https://review.coreboot.org/#/c/coreboot/+/26286/ > > Can you please pick

[coreboot] Exception on Skylake after enabling ACPI timer emulation

or review "disappeared"? Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -BEGIN PGP SIGNATURE- iQIzBAEBCAAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAlr9a9wACgkQsu5x6Weq nkwXIRAAms9hkcg1E49G1ww30ZdOR0k1XUn1n63B5ccpfGcGQsZPKP

Re: [coreboot] PC Engines apu2 boot regression

he_ > fix? I don't see why it could not. It's pretty much all that we can > do with binaryPI, anything else touches the blobs. Hi Marshall, Kyösti, also confirm that this patch fix regression on recent master. Will you sent patch? Best Regards, - -- Piotr Król Embedde

[coreboot] PC Engines apu2 boot regression

@ offset 5ffdc0 size 7b0e0 CBFS: 'Master Header Locator' located CBFS at [200:7fffc0) CBFS: Locating 'AGESA' CBFS: Found @ offset 5ffdc0 size 7b0e0 Fch OEM config in INIT RESET Done Any idea what can be result of such weird behavior? Best Regards, -- Piotr Król Embedded Systems Consultant https

Re: [coreboot] [URGENT] Full List of AMD-based boards that are going to be removed from coreboot unless people cough up a board status update

-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 On 04/28/2018 03:48 PM, Nico Huber wrote: > Hi Piotr, Hi Nico, > > On 28.04.2018 15:16, Piotr Król wrote: >> Second thing that IMO is problematic in board status is >> assumption that system have to boot

Re: [coreboot] [URGENT] Full List of AMD-based boards that are going to be removed from coreboot unless people cough up a board status update

e status update should be sent at - -rcX stage and then after stable release. We will see how status board update will evolve. Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -BEGIN PGP SIGNATURE- iQIzBAEBCgAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAlrp3

Re: [coreboot] [URGENT] Full List of AMD-based boards that are going to be removed from coreboot unless people cough up a board status update

ematic when you have to use customized version of SeaBIOS or any other payload used for booting system. Because of long weekend we will send board status updates for boards under 3mdeb maintainership before 11 May. Please let me know if feel this is too late. Best Regards, - -- Piotr Król E

Re: [coreboot] Problem with tianocore compilation in coreboot-sdk:1.50

d remote debugging services. We are in preparation of marketing materials, so some offer should appear soon. I already had email discussion with Patrick, but we didn't moved forward. Some blog posts about RTE: https://3mdeb.com/firmware/minnowboard-turbot-remote-firmware-flashing-with-rte-remote-testi

Re: [coreboot] Problem with tianocore compilation in coreboot-sdk:1.50

On 04/04/2018 05:31 PM, Aaron Durbin wrote: > On Wed, Apr 4, 2018 at 4:55 AM, Piotr Król <piotr.k...@3mdeb.com> wrote: >> Hi all, >> I can't compile tianocore payload using coreboot-sdk:1.50 and coreboot 4.7. >> >> VfrUtilityLib.cpp: In member

[coreboot] Problem with tianocore compilation in coreboot-sdk:1.50

it is hard to build 2 the same coreboot-sdk containers. Best Regards, -- Piotr Król Embedded Systems Consultant http://3mdeb.com | @3mdeb_com -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Minnowboard

GitHub is good enough though? I don't have > an RDC portal account. Yes. But if you would like to complain to Intel for performance related stuff they will say "please use recent one" and then you can complain on correct one :) Best

Re: [coreboot] Minnowboard

-p linux_spi:dev=/dev/spidev0.0,spispeed=32000 -l \ layout -i bios -w /tmp/coreboot.rom Our container have default FSP from GitHub which is not the most recent one. Latest you can obtain only through Intel RDC portal. Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.

Re: [coreboot] Serial input / output with SeaBIOS 1.11.0

O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A I believe BSD has alternative. Typical addresses are: ttyS0 address 0x3f8 ttyS1 address 0x2f8 ttyS2 address 0x3e8 ttyS3 address 0x2e8 Hope this help. Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com |

Re: [coreboot] Serial input / output with SeaBIOS 1.11.0

x3f8 (irq = 4, base_baud = 115200) is a 16550A I believe BSD has alternative. Typical addresses are: ttyS0 address 0x3f8 ttyS1 address 0x2f8 ttyS2 address 0x3e8 ttyS3 address 0x2e8 Hope this help. Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3

Re: [coreboot] EARLY_CBMEM_INIT for Geode LX platforms

is module occurs to be a problem on Geode). > > Has anybody maybe done some work yet? > > Best Regards, --- Michał Żygowski https://3mdeb.com | @3mdeb_com > Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -BEGIN PGP SIGNA

Re: [coreboot] coreboot support for Minnowboard Turbot E3845

ecently with E3826 and saw similar behavior when incorrect microcode was used (or no microcode). What are your ucode configuration ? Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -BEGIN PGP SIGNATURE- iQIzBAEBCgAdFiEE4DCbLYWmfoRj

Re: [coreboot] IOMMU/PCI passthrough on the PCENGINES APU2 board

n as Philipp reported. Unfortunately I'm not sure how to prove that pass-through works as expected. If you can help in providing test scenario we would be glad with pushing this work forward. Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com ---

Re: [coreboot] Broadwell-DE NS FSP not support

wledge Intel has separate BWG and other specific documents for that, so I assume FSP also may be different. @Hilbert, did you tried DE FSP, is there anything what not work as you want ? Best Regards, - -- Piotr Król Embedded Systems Consultant http://3mdeb.com | @3mdeb_com -BEGIN P

Re: [coreboot] PC Engines apu2 booting broken

crazy. Sounds like great approach. Any easy way to strip debug and redefine ASSERT in coreboot ? Or you just doing it manually ? Would be great to note exact steps in case anyone would need that in future. Maybe even script. Best Regards, - -- Piotr Król Embedded Systems Consultant https:/

Re: [coreboot] How is depreciating 95% of coreboot boards worth it for such minor improvements?

.2d was pushed to board_status, it also refreshes > .2c and .6 entries even when they don't exist as individual updates > on the wiki. Yes, this is what I meant. We get access to wiki and fixed that issue. Now correct logs were uploaded to supported boards site. Best Regards, - -- Piotr Kr

[coreboot] PC Engines apu2 booting broken

DRIVERS_AMD_PI and CPU_AMD_PI in Kconfig, but those not help. Platform behave like it would not proceed with booting - no serial output, Ethernet led on and blinks after regular cycles (reset ?). Previous commit works fine. Any idea what I'm missing ? Best Regards, - -- Piotr Król Embedded

Re: [coreboot] Coreboot support for atom c3000

or this platform ? Both with Tirumalesh we asked Intel, but they point to documentation that I have no access to. I would at least want to know what are the plans with Denverton support. Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com

Re: [coreboot] How is depreciating 95% of coreboot boards worth it for such minor improvements?

n. We feel responsible for PC Engines platforms and keeping them in coreboot tree. Things that I think we can do better is: 1. Adding missing wiki pages for PC Engines platforms. 2. Adding people from 3mdeb as official maintainers of PC Engines platforms - would that be accepted ? Best Regards, -

Re: [coreboot] Coreboot ECC support in Asrock IMB-A180-H

post=E35B5D34-262B-480E-9887-F7F2A 292E02F=DF5ACB70-99C4-4C61-AFA6-4C0E0DB05B2A=2 [2] https://github.com/3mdeb/edk2/tree/apu2-uefi [3] https://review.coreboot.org/cgit/blobs.git/commit/?id=95b80508d9ba26350b 7e699decd47074f480a2f2 - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3m

Re: [coreboot] iPXE as payload?

isable that behavior. I believe this was the change: https://github.com/pcengines/seabios/commit/ac6d3e213a3867bd586b62924b8255d57333e078 Best Regards, -- Piotr Król Embedded Systems Consultant http://3mdeb.com | @3mdeb_com -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/li

Re: [coreboot] coreboot solidpc

wise the main processor might get damaged Best Regards, -- Piotr Król Embedded Systems Consultant http://3mdeb.com | @3mdeb_com -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot solidpc

ata: 0xfff9839c UPD Data: 0xfff983b0 > Updating UPD values for MemoryInit POST: 0x36 Calling FspMemoryInit: > 0xfffb580f > 0x: NvsBufferPtr 0xfef03e2c: RtBufferPtr 0xfef03dd4: HobListPtr POST: > 0x92 Can I assume this is recent master ? Best Regards, -- Piotr Król Embedded

Re: [coreboot] PC Engines APU2 support

On Tue, Jun 07, 2016 at 09:40:59AM +0200, maxime de Roucy wrote: > Le 7 juin 2016 2:09 AM, "Piotr Król" <piotr.k...@3mdeb.com> a écrit : Hi Maxime, > > I'm working on support for PC Engines APU2 (AMD GX-412TC) board and I > > finally manage to boot Voyage Linux

[coreboot] PC Engines APU2 support

Best Regards, Piotr Król Embedded Systems Consultant http://3mdeb.com | @3mdeb_com -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] qemu-armv7: memcpy to ROMSTAGE_BASE

Hi all, during debugging of qemu-armv7 I found that coreboot performs memcpy to ROMSTAGE_BASE area. This is in src/arch/armv7/memcpy.S: 3: PLD(pld [r1, #124] ) 4: ldr8w r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f subsr2, r2, #32

Re: [coreboot] qemu-armv7: memcpy to ROMSTAGE_BASE

On Sat, Aug 16, 2014 at 01:15:05PM -0700, ron minnich wrote: The ROMSTAGE on ARM is expected to be SRAM. When you know the SRAM address for a given mainboard, you need to set it up in Kconfig for *just* that mainboard. Nice work, I think you're getting close! Thanks :) Meanwhile I was able

Re: [coreboot] qemu-armv7: code execution out of RAM or ROM using latest QEMU

On Mon, Aug 11, 2014 at 04:00:19PM -0700, ron minnich wrote: During debugging I found that stack is initialized in range 0x4-0x7FF00 (using .Stack and .Stack_size). When coreboot code is executed: reset init_stack_loop call_bootblock main +- armv7_invalidate_caches +-

Re: [coreboot] qemu-armv7: code execution out of RAM or ROM using latest QEMU

On Mon, Aug 11, 2014 at 04:00:19PM -0700, ron minnich wrote: Sorry, in other words, how much ROM are you setting up on that qemu board? The 'execute outside ram or rom' is usually a jump to an IP that qemu does not recognize as ROM/RAM. ROM is probably represented in vexpress-a9 as

Re: [coreboot] qemu-armv7: code execution out of RAM or ROM using latest QEMU

On Tue, Aug 12, 2014 at 05:30:03AM +0200, Patrick Georgi wrote: Am 12.08.2014 um 00:37 schrieb Piotr Król: Anyone know how to load bootblock debug symbols to gdb when debugging using '-s -S' option ? add-symbol-file $filename $loadaddr When I try: gdb$ target remote :1234 Remote debugging

Re: [coreboot] qemu-armv7: code execution out of RAM or ROM using latest QEMU

On Mon, Aug 11, 2014 at 12:15:32AM +0200, Peter Stuge wrote: There is no coreboot gdb support There is some gdb support in coreboot, but maybe not for ARM? What I tried to say is that it happens to early to connect to coreboot using gdb support, but maybe I'm wrong. so I used qemu '-s

Re: [coreboot] qemu-armv7: code execution out of RAM or ROM using latest QEMU

11, 2014 at 2:09 AM, Piotr Król pietrush...@gmail.com wrote: On Mon, Aug 11, 2014 at 12:15:32AM +0200, Peter Stuge wrote: There is no coreboot gdb support There is some gdb support in coreboot, but maybe not for ARM? What I tried to say is that it happens to early to connect

Re: [coreboot] qemu-armv7: code execution out of RAM or ROM using latest QEMU

On Mon, Aug 11, 2014 at 01:51:16PM -0700, ron minnich wrote: I can't recall for ARM, it's been more than a year since I used qemu on that platform. That said, ... on the platforms we use ROM is in low memory. What's your coreboot system.map say? I'm not sure what 'coreboot system.map' is but

[coreboot] qemu-armv7: code execution out of RAM or ROM using latest QEMU

=qemu.git;a=commit;h=75c9a1a0473cc5ca9756d11b236c715c7bc0ba67 It was changed by someone from Linaro, can we assume that this change is ok and problem is on coreboot side ? If the problem is on coreboot side than have you got any ideas how to fix it (or where to dig) ? Best Regards, Piotr Król

Re: [coreboot] qemu-armv7: code execution out of RAM or ROM using latest QEMU

On Sun, Aug 10, 2014 at 02:35:46PM -0700, ron minnich wrote: You can't assume much of anything. That commit seems not that harmful. What would help is if you tell us more about when the problem happens. There's just not enough info in your note, but I'd love to try to help. I will try to do

[coreboot] lzma: Deconding error = 1 for QEMU q35 with SeaBIOS

Hi Coreboot experts, I'm trying to use latest Coreboot code(c9babb2) with QEMU(1cf892c) q35 and SeaBIOS(master). Unfortunately, I encounter lzma decoding error (log: http://pastebin.com/aPaPBjZQ). I tried to debug LzmaDecode and it looks like rep0 reach some big value in my case 0x14ed98 after