The email below has an incorrect link to the change in question. The
correct one is: https://gem5-review.googlesource.com/#/c/3760/
//Andreas
On 14/06/2017 15:22, Andreas Sandberg wrote:
Hi Yasir,
We decided to disable these gem5-specific extensions by default due to
reliability issues
: disable GIC extensions
changeset 2c111e634da0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2c111e634da0
description:
arm: disable GIC extensions
Change-Id: If19b9c593b48ded1ea848f2d3710d4369ec8a221
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.
Hi Gabe,
I wasn't around when we implemented the original device model. I suspect
the reasoning was that a touch screens are more reliable when using VNC
since they use absolute coordinates. IIRC, most virtualisation solution
nowadays default to touch screen emulation for this reason.
I started
Hi Juan,
There is probably something from with a configuration script somewhere
that tries to set the interleaving match bits to start at bit 256.
PyBind enforces that the value is small enough to fit in the target C++
type (uint8_t), which 256 clearly doesn't. This is why you get the
somewhat
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3121 )
Change subject: arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMU
..
arm: Fix incorrect handling of PMEVTYPERx_EL0
ings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I2913eedddeb98480660e2d63948f6d727adf5ab8
Gerrit-Change-Number: 3121
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <and
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3221 )
Change subject: sim: Add hooks to implement event reference counting
..
sim: Add hooks to implement event reference
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3222 )
Change subject: python: Fix PyEvent reference counting bug
..
python: Fix PyEvent reference counting bug
The current
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3481 )
Change subject: arch-arm: Fix some poorly done type max and min in NEON
..
arch-arm: Fix some poorly done type max
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/3481
Change subject: arch-arm: Fix some poorly done type max and min in NEON
..
arch-arm: Fix some poorly done type max and min
for
Managed.
Change-Id: I5637984c906a9d44c22780712cf1c521b8297149
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
---
M src/sim/eventq.cc
M src/sim/eventq.hh
M src/sim/eventq_impl.hh
3 files changed, 61 insertions(+),
PI instead.
Change-Id: I4e8e04abc4f61dff238d718065f5371e73b38ab3
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
---
M src/python/m5/event.py
M src/python/pybind11/event.cc
2 files changed, 44 insertions(+), 46 deletions(-)
-
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3225 )
Change subject: ext: Upgrade PyBind11 to version 2.1.1
..
ext: Upgrade PyBind11 to version 2.1.1
Change-Id
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3224 )
Change subject: python: Prevent Python wrappers from deleting SimObjects
..
python: Prevent Python wrappers from
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3223 )
Change subject: python: Fix weird memory issue in wrapped AddrRange vectors
..
python: Fix weird memory issue
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3421 )
Change subject: python: Remove unused readline import
..
python: Remove unused readline import
The readline module
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3420 )
Change subject: base, sim, arch: Fix clang 5.0 warnings
..
base, sim, arch: Fix clang 5.0 warnings
Compiling gem5
to avoid the warning.
* Some templatized classes contain static variables. The
instantiated versions of these variables / templates need to be
explicitly declared to avoid a compiler warning.
Change-Id: Ie8261144836e94ebab7ea04b90927672c257
Signed-off-by: Andreas Sandberg <andreas.sa
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/3421
Change subject: python: Remove unused readline import
..
python: Remove unused readline import
The readline module
is set.
Change-Id: I5637984c906a9d44c22780712cf1c521b8297149
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
---
M src/sim/eventq.cc
M src/sim/eventq.hh
M src/sim/eventq_impl.hh
3 files changed, 53 insertions(+),
PI instead.
Change-Id: I4e8e04abc4f61dff238d718065f5371e73b38ab3
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
---
M src/python/m5/event.py
M src/python/pybind11/event.cc
2 files changed, 46 insertions(+), 46 deletions(-)
-
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3220 )
Change subject: python: Add a helper function to create Python events
..
python: Add a helper function to create
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2620 )
Change subject: arm, dev: stub out GIC distributor interrupt groups
..
arm, dev: stub out GIC distributor interrupt
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3241 )
Change subject: syscall_emul: Fix undefined macro behavior
..
syscall_emul: Fix undefined macro behavior
Clang's
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3240 )
Change subject: arm: Remove unused DumpStatsPCEventF class in FreeBSD system
..
arm: Remove unused DumpStatsPCEventF
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Andreas Hansson <andreas.hans...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
---
M src/sim/syscall_emul.hh
1 file changed, 19 insertions(+), 7 deletions(-)
--
To view, visit https://gem5-revie
Hi Everyone,
Some of our internal users recently ran into various issues related to
the new PyBind wrappers. These are the issues I'm aware of:
* Events implemented in Python aren't reference counted correctly.
There are cases where the Python side of an event gets deallocated, but
not the
Having had a quick look at the code, I'd say that exceptions could
definitely make sense. I would support limited use of exceptions where
it makes sense to make the code flow less entangled. Initially, I would
argue that we should keep exceptions local to SimObjects (interfaces
like ports should
holds a pointer to the root node
as long as the simulator is running.
Prevent SimObject and Param deletion by using a PyBind-prescribed
unique_ptr with a dummy deleter as the pointer wrapper for the Python
world.
Change-Id: Ied14602c9ee69a083a69c5dae1b5fcf8efb4548a
Signed-off-by: Andreas Sandberg
PyBind11 to version 2.1.1
Change-Id: I16870dec402d661295f9d013dc23e362b2b2c169
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
---
M ext/pybind11/.appveyor.yml
A ext/pybind11/.readthedocs.yml
M ext/pybind11/.travis.yml
M
as opaque
types. This slightly changes the semantics of the wrapper since Python
now manipulates the real object rather than a copy that has been
converted to a list.
Change-Id: Ie027c06e7a7262214b43b19a76b24fe4b20426c5
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by:
the Event::getRefManager() method and returning a pointer
to a custom reference manager. Reference counting can then be enabled
by setting the Managed flag at Event creation.
Change-Id: I5637984c906a9d44c22780712cf1c521b8297149
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by:
the public API
when switching to PyBind.
Change-Id: Icbd0e392d9506934ec2c9f541199aa35c1c2df8c
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
---
M src/python/m5/event.py
1 file changed, 27 insertions(+), 1 deletion(-)
diff
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3120 )
Change subject: style: Treat PyBind headers as Python headers
..
style: Treat PyBind headers as Python headers
Some
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3140 )
Change subject: python: Fix debug flag listing regression
..
python: Fix debug flag listing regression
The PyBind11
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2966 )
Change subject: util, arm: Support mmapped m5ops on aarch64
..
util, arm: Support mmapped m5ops on aarch64
Add
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2964 )
Change subject: arm: Add support for memory-mapped m5ops
..
arm: Add support for memory-mapped m5ops
Add support
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2965 )
Change subject: arm: Enable m5ops by default for VExpress_GEM5_V1
..
arm: Enable m5ops by default
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/3140
Change subject: python: Fix debug flag listing regression
..
python: Fix debug flag listing regression
The PyBind11 changes
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2962 )
Change subject: util: Correctly handle short writes in m5 (read|exec)file
..
util: Correctly handle short writes
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2963 )
Change subject: kvm, arm: Fix incorrect PSTATE sync
..
kvm, arm: Fix incorrect PSTATE sync
The state transfer code
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2961 )
Change subject: util: Fix incorrect use of m5_loadsymbol
..
util: Fix incorrect use of m5_loadsymbol
It seems like
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3122 )
Change subject: util: Add the m5_loadsymbol pseudo op to the m5 tool
..
util: Add the m5_loadsymbol pseudo op
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/3122
Change subject: util: Add the m5_loadsymbol pseudo op to the m5 tool
..
util: Add the m5_loadsymbol pseudo op to the m5 tool
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/3121
Change subject: arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMU
..
arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMU
: Id175a4f613960a17f84f98b81bfd02806e905d5a
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
---
M util/style/sort_includes.py
1 file changed, 3 insertions(+), 0 deletions(-)
diff
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2960 )
Change subject: util: Fix incorrect return type in m5 writefile
..
util: Fix incorrect return type in m5 writefile
of PSTATE and cast the value to
a uint64_t.
Change-Id: I0a6ff5b77b897c756b20a20f65c420f42386360f
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M src/arch/arm/kvm/armv8_cpu.cc
1 file changed, 2 insertions(+),
behavior. Add the necessary checks.
Change-Id: If558534d3245aa24cf15edf06bd0af4c6ba3908c
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M util/m5/m5.c
1 file changed, 20 insertions(+), 4 deletions(-)
--
To view,
this information however you like :).
Cheers,
Jason
On Tue, May 2, 2017 at 4:04 AM Andreas Sandberg <andreas.sandb...@arm.com>
wrote:
Hi Gabe,
I'm planning to push the pybind patches today. I'm currently re-running
the full regression suite to ensure that there are no rebasing issues
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2230 )
Change subject: ext: Fix undefined macro in pybind
..
ext: Fix undefined macro in pybind
Change-Id
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2922 )
Change subject: python: Remove SWIG
..
python: Remove SWIG
Remove SWIG-specific Python code.
Change-Id
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2229 )
Change subject: ext: Add pybind rev f4b81b3
..
ext: Add pybind rev f4b81b3
Change-Id
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2921 )
Change subject: base, sim, dev: Remove SWIG
..
base, sim, dev: Remove SWIG
Remove SWIG guards and SWIG-specific C
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2920 )
Change subject: scons: Remove SWIG support
..
scons: Remove SWIG support
Remove remaining SWIG support from
Hi Gabe,
I'm planning to push the pybind patches today. I'm currently re-running
the full regression suite to ensure that there are no rebasing issues.
Once that completes, I'll hit the blue button and submit it.
//Andreas
On 02/05/2017 06:31, Gabe Black wrote:
Hi folks. I've been working on
[1] https://gem5-review.googlesource.com/#/c/2966/
On 20/04/2017 18:56, Andreas Sandberg wrote:
I have a prototype implementation that uses a mechanism very similar to
the one on x86. The main reason I haven't posted it externally is that I
wanted to get the user-space side (the m5 tool
images may be another story though).
Were you thinking about something like a python script in the "util" directory?
If yes, I should be able to do it.
Thanks,
Pau
-Original Message-----
From: Andreas Sandberg [mailto:andreas.sandb...@arm.com]
Sent: jueves, 27 de abril de 2017 15:1
function to call and the lower 8 bits denote the
subfunction.
Change-Id: I55fd8ac1afef4c3cc423b973870c9fe600a843a2
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/ArmTLB.p
: I13e21e48536b9849bf4081411b66b2f350f7a8ac
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M util/m5/m5op_arm_A64.S
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/util/m5/m5op_a
to
a uint64_t.
Change-Id: I0a6ff5b77b897c756b20a20f65c420f42386360f
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M src/arch/arm/kvm/armv8_cpu.cc
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/
: Enable m5ops by default for VExpress_GEM5_V1
Allocate 0x1001-0x1001 for m5 pseudo-ops. This range is a part
of the CS5 address range in the RS1/RS2 memory map.
Change-Id: Ica45cd53bc4ebb62966afa099fa465e27fb0452c
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by:
the necessary checks.
Change-Id: If558534d3245aa24cf15edf06bd0af4c6ba3908c
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M util/m5/m5.c
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/util/m5/m5.c b/
: I83b61c48d6f8d7b1e8b57d884dfca00481c83c3a
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
---
M util/m5/m5.c
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/util/m5/m5.c b/util/m5/m5.c
index 8e6f4fc..ee92134 100644
-
incorrect return type in m5 writefile
Change-Id: Ic24a1c3c1488e970ed27bb6b99262d201f535384
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
---
M util/m5/m5.c
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ut
of warnings before.
I'll take a close look at the patch next Wed. or Thurs. Sorry for the delay.
Jason
On Wed, Mar 29, 2017 at 6:08 AM Andreas Sandberg <andreas.sandb...@arm.com>
wrote:
Hi Everyone,
Some time ago, I posted a series of changes [1] to switch from SWIG to
PyBind for our
, dev: Remove SWIG
Remove SWIG guards and SWIG-specific C++ code.
Change-Id: Icaad6720513b6f48153727ef3f70e0dba0df4bee
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Andreas Hansson <andreas.hans...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com&
Remove SWIG-specific Python code.
Change-Id: If1d1b253d84021c9a8f9a64027ea7a94f2336dff
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Andreas Hansson <andreas.hans...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
---
M src/python/m5/SimObje
SWIG support
Remove remaining SWIG support from the build infrastructure.
Change-Id: I7549cd0f952ca3a51481918eefef3a29f03af359
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Andreas Hansson <andreas.hans...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...
nerated from
system/arm/aarch64_bootloader/boot.S, which got updated on 2015-07-15)
2) binaries/vexpress.aarch64.20140821.dtb (it has a misconfiguration,
as explained by Andreas Sandberg here =>
http://www.mail-archive.com/gem5-dev@gem5.org/msg18440.html)
And I also suspect that the
Hi Gabe,
It seems like one of the stat updates was too big and made hg choke. I
have changed the hg repo config to ignore the file size rules since they
don't make any sense any more.
//Andreas
On 25/04/2017 00:26, Gabe Black wrote:
Hi folks. I've brought this up numerous times before, but I
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2840 )
Change subject: tests: Remove unused options from tests.py
..
tests: Remove unused options from tests.py
The test
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/2840
Change subject: tests: Remove unused options from tests.py
..
tests: Remove unused options from tests.py
The test sub-command
I have a prototype implementation that uses a mechanism very similar to
the one on x86. The main reason I haven't posted it externally is that I
wanted to get the user-space side (the m5 tool) to autodetect the memory
range. We currently have to hard-code it, which isn't ideal if the
memory map
is a Python convenience class to
that warns when an interrupt is triggered.
Change-Id: I181d952f17958549f25883e8aed4b00681550158
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
A src/dev/Interrupt.py
M src/dev/SConscri
ptor makes it possible to
use the same device model to generate both PPIs and SPIs (e.g., the
PMU).
Change-Id: I73d6591c168040faef2443430c4f1da10c387a2a
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M src/dev/ar
: Id77d99c879d69d605e28326d35b8d90c8ef06d56
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Andreas Hansson <andreas.hans...@arm.com>
---
M src/dev/x86/Cmos.py
M src/dev/x86/I8042.py
M src/dev/x86/I82094AA.py
M src/dev/x86/I8254.py
M src/dev/x86/I8259.py
M src/dev/x86/SouthBridge.py
M src/dev/x86/X86Int
is a Python convenience class to
that warns when an interrupt is triggered.
Change-Id: I181d952f17958549f25883e8aed4b00681550158
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
A src/dev/Interrupt.py
M src/dev/SConscri
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2720 )
Change subject: power: Allow global stats in power equations
..
power: Allow global stats in power equations
Allow
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2721 )
Change subject: config, arm: Add an example power model
..
config, arm: Add an example power model
Add a script
, x86: Use the generic InterruptLine interface
Refactor x86 interrupt handling to use the generic InterruptLine
interface instead of the x86-specific
X86IntSourcePin/X86IntSinkPin/X86IntLine interfaces.
Change-Id: Id77d99c879d69d605e28326d35b8d90c8ef06d56
Signed-off-by: Andreas Sandberg
ble to use the same device
model to generate both PPIs and SPIs (e.g., the PMU).
Change-Id: I73d6591c168040faef2443430c4f1da10c387a2a
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M src/dev/arm/Gic.py
M src/dev/arm/bas
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/2721
Change subject: config, arm: Add an example power model
..
config, arm: Add an example power model
Add a script
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/2720
Change subject: power: Allow global stats in power equations
..
power: Allow global stats in power equations
Allow global
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2661 )
Change subject: power: Add error checking to MathExprPowerModel
..
power: Add error checking to MathExprPowerModel
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2662 )
Change subject: power: Add a voltage variable to power expressions
..
power: Add a voltage variable to power
Hi Everyone,
Gabe's heroic effort to refresh the reference stats (thanks Gabe!) have
once again highlighted issues in the current test regime.
My impression is that some of the affected tests are only marginally
useful. Especially for architecture that are largely unmaintained. I
don't want to
a verification step in startup() that
ensures that all of the referenced stats actually exist.
Change-Id: I8f71c73341578d5882c8d93e482f5383fbda5f1d
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-by: Sascha Bischoff &
: Ice3c9a4a221921a542de5da52f83f3f88862d246
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bisch...@arm.com>
---
M src/sim/power/mathexpr_powermodel.cc
1 file changed, 4 insertions(+), 1 d
() that
ensures that all of the referenced stats actually exist.
Change-Id: I8f71c73341578d5882c8d93e482f5383fbda5f1d
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bisch...@arm.com
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2660 )
Change subject: scons: Fix hook installation error caused by stale cache
..
scons: Fix hook installation error caused
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/2660
Change subject: scons: Fix hook installation error caused by stale cache
..
scons: Fix hook installation error caused by stale
On 01/04/2017 12:27, Gabe Black wrote:
Hi folks. I'm working through the nightly regressions to get them to a good
point for a rebase of our internal branch of gem5, and I've noticed a few
things:
1. The stats have been changed but not updated a bunch of times. I've
identified almost all the
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2443 )
Change subject: arm, dev: add basic support for GICC_BPR register
..
arm, dev: add basic support for GICC_BPR
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2442 )
Change subject: arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handling
..
arm, dev: refactor GIC Pl390 GICD_ITARGETSRn
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2444 )
Change subject: arm, kvm: implement GIC state transfer
..
arm, kvm: implement GIC state transfer
This also allows
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2441 )
Change subject: arm: refactor packet processing in Pl390 GIC
..
arm: refactor packet processing in Pl390 GIC
Change
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2281 )
Change subject: arm: Don't panic when checking coprocessor read/write
permissions
..
arm: Don't panic when
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2280 )
Change subject: arm: Treat Write-Through Normal memory as Non-Cacheable
..
arm: Treat Write-Through Normal memory
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2600 )
Change subject: sim: Handle cases where Drainable::resume() creates objects
..
sim: Handle cases where Drainable
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