Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

> On Jan. 5, 2017, 8:32 a.m., Tony Gutierrez wrote: > > Is there anything holding this up from being shipped? > > Andreas Hansson wrote: > In my view the patch needs two things: > > 1) Some thought around the design. I am still hoping there is a less > invasive way of

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

> On Jan. 5, 2017, 4:32 p.m., Tony Gutierrez wrote: > > Is there anything holding this up from being shipped? > > Andreas Hansson wrote: > In my view the patch needs two things: > > 1) Some thought around the design. I am still hoping there is a less > invasive way of

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

> On Jan. 5, 2017, 8:32 a.m., Tony Gutierrez wrote: > > Is there anything holding this up from being shipped? > > Andreas Hansson wrote: > In my view the patch needs two things: > > 1) Some thought around the design. I am still hoping there is a less > invasive way of

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

> On Jan. 5, 2017, 4:32 p.m., Tony Gutierrez wrote: > > Is there anything holding this up from being shipped? > > Andreas Hansson wrote: > In my view the patch needs two things: > > 1) Some thought around the design. I am still hoping there is a less > invasive way of

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

> On Jan. 5, 2017, 8:32 a.m., Tony Gutierrez wrote: > > Is there anything holding this up from being shipped? > > Andreas Hansson wrote: > In my view the patch needs two things: > > 1) Some thought around the design. I am still hoping there is a less > invasive way of

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

> On Jan. 5, 2017, 4:32 p.m., Tony Gutierrez wrote: > > Is there anything holding this up from being shipped? > > Andreas Hansson wrote: > In my view the patch needs two things: > > 1) Some thought around the design. I am still hoping there is a less > invasive way of

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

> On Jan. 5, 2017, 8:32 a.m., Tony Gutierrez wrote: > > Is there anything holding this up from being shipped? > > Andreas Hansson wrote: > In my view the patch needs two things: > > 1) Some thought around the design. I am still hoping there is a less > invasive way of

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

> On Jan. 5, 2017, 4:32 p.m., Tony Gutierrez wrote: > > Is there anything holding this up from being shipped? In my view the patch needs two things: 1) Some thought around the design. I am still hoping there is a less invasive way of accommodating the functionality, possibly with some changes

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2691/#review9228 --- Is there anything holding this up from being shipped? - Tony Gutierrez

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

> On April 13, 2016, 7:38 a.m., Bjoern A. Zeeb wrote: > > Can you please update it? > > It neither applies cleanly nor does it compile afterwards. Done. - Steve --- This is an automatically generated e-mail. To reply, visit:

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2691/ --- (Updated April 14, 2016, 10:42 p.m.) Review request for Default. Changes ---

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2691/#review8197 --- Can you please update it? It neither applies cleanly nor does it compile

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2691/ --- (Updated Jan. 18, 2016, 7:46 p.m.) Review request for Default. Changes ---

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

> On May 7, 2015, 7:55 a.m., Andreas Hansson wrote: > > src/mem/cache/cache_impl.hh, line 639 > > > > > > Is it safe to call this here and ignore the return value? > > > > It would be nice if we do not assume that

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2691/#review6124 --- I vote for the non-goto verison. Is there really no way we can achieve

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

On May 7, 2015, 12:55 a.m., Andreas Hansson wrote: I vote for the non-goto verison. Is there really no way we can achieve this without the extra packets going back and forth? It seems the shortcircuiting we do with packets we should be able to do without them if we tapped in one

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2691/ --- (Updated May 6, 2015, 3:59 p.m.) Review request for Default. Changes ---

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2691/ --- (Updated May 6, 2015, 3:21 p.m.) Review request for Default. Changes ---

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

On April 8, 2015, 1:43 p.m., Stephan Diestelhorst wrote: src/mem/cache/cache_impl.hh, line 1286 http://reviews.gem5.org/r/2691/diff/1/?file=44226#file44226line1286 Why don't you break and drop the early_exit? [Hmm, I had a comment here but reviewboard silently dropped it when I

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

On April 8, 2015, 1:43 p.m., Stephan Diestelhorst wrote: src/mem/cache/cache_impl.hh, line 1359 http://reviews.gem5.org/r/2691/diff/1/?file=44226#file44226line1359 This should really be: if (!mshr.hasTargets()) and all the stuff below has too deep an (or

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2691/#review6028 --- Get the idea, but I am burnt when it comes to debugging request + packet

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2691/#review6026 --- src/mem/cache/cache_impl.hh http://reviews.gem5.org/r/2691/#comment5249

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2691/#review5961 --- Great to see this functionality added. I am not 100% convinced of the

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

On March 17, 2015, 12:07 p.m., Andreas Hansson wrote: src/mem/cache/cache_impl.hh, line 1417 http://reviews.gem5.org/r/2691/diff/1/?file=44226#file44226line1417 the changed order of the write buffer allocation and dealing with the writebacks is important? Good question. I

Re: [gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2691/#review5943 --- src/mem/cache/cache_impl.hh http://reviews.gem5.org/r/2691/#comment5194

[gem5-dev] Review Request 2691: mem: implement x86 locked accesses in timing-mode classic cache

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2691/ --- Review request for Default. Repository: gem5 Description --- Changeset