Re: [gem5-dev] Review Request 2269: mem: Add DRAM cycle time

On May 1, 2014, 11:05 p.m., Nilay Vaish wrote: Why is the clock period associated with each clocked object not enough? There is a difference between the controller clock (which is what the DRAMCtrl clock domain would currently communicate), and the DRAM clock (tCK in DRAM speak). The other

Re: [gem5-dev] Review Request 2254: cpu: Add flag name printing to StaticInst

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2254/ --- (Updated May 2, 2014, 8 a.m.) Review request for Default. Repository: gem5

Re: [gem5-dev] Review Request 2247: arch: teach ISA parser how to split code across files

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2247/ --- (Updated May 7, 2014, 9:44 p.m.) Review request for Default. Repository: gem5

Re: [gem5-dev] Review Request 2266: mem: Remove printing of DRAM params

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2266/ --- (Updated May 7, 2014, 9:49 p.m.) Review request for Default. Summary (updated)

[gem5-dev] changeset in gem5: mem: Add precharge all (PREA) to the DRAM con...

changeset 39eb5d4c400a in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=39eb5d4c400a description: mem: Add precharge all (PREA) to the DRAM controller This patch adds the basic ingredients for a precharge all operation, to be used in conjunction with

[gem5-dev] changeset in gem5: mem: Add tWR to DRAM activate and precharge c...

changeset 793e5ff26e0b in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=793e5ff26e0b description: mem: Add tWR to DRAM activate and precharge constraints This patch adds the write recovery time to the DRAM timing constraints, and changes the current

[gem5-dev] changeset in gem5: mem: Merge DRAM latency calculation and bank ...

changeset e084db2b1527 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e084db2b1527 description: mem: Merge DRAM latency calculation and bank state update This patch merges the two control paths used to estimate the latency and update the bank state.

[gem5-dev] changeset in gem5: mem: Add tRTP to the DRAM controller

changeset acc1131e01d6 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=acc1131e01d6 description: mem: Add tRTP to the DRAM controller This patch adds the tRTP timing constraint, governing the minimum time between a read command and a precharge.

[gem5-dev] changeset in gem5: tests: Reflect name change in DRAM tests

changeset 5a45f124a2f7 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=5a45f124a2f7 description: tests: Reflect name change in DRAM tests This patch reflects the recent name change in the DRAM TrafficGen tests and also tidies up the test directory.

[gem5-dev] changeset in gem5: config: Bump DRAM sweep bus speed to match DD...

changeset 4161cfba9658 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=4161cfba9658 description: config: Bump DRAM sweep bus speed to match DDR4 config This patch bumps the bus clock speed such that the interconnect does not become a bottleneck with a

[gem5-dev] changeset in gem5: mem: Make DRAM read/write switching less cons...

changeset 823f7fd1a82f in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=823f7fd1a82f description: mem: Make DRAM read/write switching less conservative This patch changes the read/write event loop to use a single event (nextReqEvent), along with a

[gem5-dev] changeset in gem5: mem: Ensure DRAM refresh respects timings

changeset 3112b31596f0 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=3112b31596f0 description: mem: Ensure DRAM refresh respects timings This patch adds a state machine for the refresh scheduling to ensure that no accesses are allowed while the

[gem5-dev] changeset in gem5: mem: Remove printing of DRAM params

changeset 2e630c6c2042 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=2e630c6c2042 description: mem: Remove printing of DRAM params This patch removes the redundant printing of DRAM params. diffstat: src/mem/dram_ctrl.cc | 57

[gem5-dev] changeset in gem5: mem: Simplify DRAM response scheduling

changeset 52d46098c1b6 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=52d46098c1b6 description: mem: Simplify DRAM response scheduling This patch simplifies the DRAM response scheduling based on the assumption that they are always returned in order.

[gem5-dev] changeset in gem5: mem: Merge DRAM page-management calculations

changeset ac71c857e1e1 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ac71c857e1e1 description: mem: Merge DRAM page-management calculations This patch treats the closed page policy as yet another case of auto-precharging, and thus merges the code

[gem5-dev] changeset in gem5: mem: Add DRAM power states to the controller

changeset c249f7660eb7 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=c249f7660eb7 description: mem: Add DRAM power states to the controller This patch adds power states to the controller. These states and the transitions can be used together with

[gem5-dev] changeset in gem5: mem: Add DRAM cycle time

changeset 52c869140fc2 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=52c869140fc2 description: mem: Add DRAM cycle time This patch extends the current timing parameters with the DRAM cycle time. This is needed as the DRAMPower tool expects

[gem5-dev] changeset in gem5: mem: Update DDR3 and DDR4 based on datasheets

changeset baf8754fd5be in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=baf8754fd5be description: mem: Update DDR3 and DDR4 based on datasheets This patch makes a more firm connection between the DDR3-1600 configuration and the corresponding datasheet,

[gem5-dev] changeset in gem5: stats: Bump stats for the fixes, and mostly D...

changeset 9eab5efc02e8 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=9eab5efc02e8 description: stats: Bump stats for the fixes, and mostly DRAM controller changes diffstat: tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

Re: [gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression --scratch all

Steve, is there any chance you could bump the t1000 test as well? The pc-switcheroo-full seems to suffering from different stats on different systems (I haven¹t dug any deeper). Andreas On 11/05/2014 11:07, Cron Daemon via gem5-dev gem5-dev@gem5.org wrote: *

Re: [gem5-dev] changeset in gem5: tests: update t1000 pc-switcheroo-full stats

Thanks a million. On 12/05/2014 14:18, Steve Reinhardt via gem5-dev gem5-dev@gem5.org wrote: changeset d51e31eef415 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d51e31eef415 description: tests: update t1000 pc-switcheroo-full stats committed reference

Re: [gem5-dev] Review Request 2273: cache: enable multiple stores per cycle

On May 14, 2014, 2:55 p.m., Ali Saidi wrote: This looks fine to me, but I'm going to guess Andreas will have a comment. This patch fixes the lovelock you mentioned, correct? Steve Reinhardt wrote: Yea, getting rid of the '+ 1' in PacketQueue::scheduleSend is needed to do two

Re: [gem5-dev] Review Request 2272: x86: fix table walker assertion

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2272/#review5102 --- src/arch/x86/pagetable_walker.cc

Re: [gem5-dev] Review Request 2276: ruby: don't make O3 CPU squash on loads that hit outstanding requests

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2276/#review5104 --- src/mem/ruby/system/Sequencer.cc

Re: [gem5-dev] Review Request 2277: o3: issue excl. prefetch as soon as store address is available

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2277/#review5105 --- src/cpu/o3/lsq_unit_impl.hh http://reviews.gem5.org/r/2277/#comment4623

Re: [gem5-dev] Review Request 2109: Different SimpleDRAM latency for read and write access

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2109/#review5106 --- With the last patches that went in, the DRAM controller now has e.g. tWR

Re: [gem5-dev] changeset in gem5: stats: changes due to o3 cpu and ruby message...

Hi Nilay, I think something went wrong in the last push: * build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full CHANGED! * build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing CHANGED! * build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing CHANGED!

[gem5-dev] Bumping gcc to 4.6

Hi all, What are your thoughts on bumping the gcc requirement from 4.4 to 4.6? From a syntactic sugar point of view this means e.g. range-based for loops and lambdas (and minor things like constant nullexpr). Most importantly, from a functionality point of view it means fully functional

Re: [gem5-dev] Review Request 2109: Different SimpleDRAM latency for read and write access

On May 30, 2014, 9:19 a.m., Ahmad Hassan wrote: Hi Andreas, According to the literature, both tCL and tWR should be independent of the memory technology because they are buffer constraint timings and they reduce the bandwidth (Source: http://dl.acm.org/citation.cfm?id=1555758).

Re: [gem5-dev] Review Request 2109: Different SimpleDRAM latency for read and write access

On May 30, 2014, 9:19 a.m., Ahmad Hassan wrote: Hi Andreas, According to the literature, both tCL and tWR should be independent of the memory technology because they are buffer constraint timings and they reduce the bandwidth (Source: http://dl.acm.org/citation.cfm?id=1555758).

Re: [gem5-dev] Review Request 2109: Different SimpleDRAM latency for read and write access

On May 30, 2014, 9:19 a.m., Ahmad Hassan wrote: Hi Andreas, According to the literature, both tCL and tWR should be independent of the memory technology because they are buffer constraint timings and they reduce the bandwidth (Source: http://dl.acm.org/citation.cfm?id=1555758).

Re: [gem5-dev] Review Request 2281: style: eliminate equality tests with true and false

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2281/#review5117 --- Ship it! Ship It! - Andreas Hansson On June 1, 2014, 12:47 a.m.,

Re: [gem5-dev] Review Request 2281: style: eliminate equality tests with true and false

On June 1, 2014, 8:22 p.m., Andreas Hansson wrote: Ship It! Perhaps we should add style to the official keywords on http://www.gem5.org/Commit_Access - Andreas --- This is an automatically generated e-mail. To reply, visit:

Re: [gem5-dev] Review Request 2109: Different SimpleDRAM latency for read and write access

On May 30, 2014, 9:19 a.m., Ahmad Hassan wrote: Hi Andreas, According to the literature, both tCL and tWR should be independent of the memory technology because they are buffer constraint timings and they reduce the bandwidth (Source: http://dl.acm.org/citation.cfm?id=1555758).

[gem5-dev] Review Request 2282: scons: Bump the compiler version to gcc 4.6 and clang 3.0

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2282/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2284: mem: Add bank and rank indices as fields to the DRAM bank

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2284/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2285: mem: DRAMPower trace output

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2285/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2286: mem: DRAMPower trace formatting script

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2286/ --- Review request for Default. Repository: gem5 Description --- Changeset

Re: [gem5-dev] Review Request 2287: sim: More rigorous clocking comments

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2287/#review5133 --- Ship it! Looks great. Thanks for the additions.

Re: [gem5-dev] Review Request 2275: o3: make LSQ full check more selective

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2275/#review5134 --- Ship it! Seems like a good first step. - Andreas Hansson On May 14,

Re: [gem5-dev] Is CoherentBus actually a bus or is it a crossbar?

Hi Pavlos, It is a crossbar implemented by muxes. I am in the process of renaming the class XBar (from Bus) to avoid any confusion. Andreas On 10/06/2014 15:50, Pavlos Maniotis via gem5-dev gem5-dev@gem5.org wrote: Hello everyone, I have read the following thread and I feel that I have not

Re: [gem5-dev] Is CoherentBus actually a bus or is it a crossbar?

is it like the configuration in the following image with three layers (1 for requests, 1 for snoops and 1 for responses)? http://www.doulos.com/knowhow/arm/Migrating_from_AHB_to_AXI/multilayer_bus _simple.png Thanks again, Pavlos On Tue, Jun 10, 2014 at 5:55 PM, Andreas Hansson via gem5-dev

[gem5-dev] changeset in gem5: scons: Bump the compiler version to gcc 4.6 a...

changeset b21b3aad6bd1 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=b21b3aad6bd1 description: scons: Bump the compiler version to gcc 4.6 and clang 3.0 This patch bumps the supported version of gcc from 4.4 to 4.6, and clang from 2.9 to 3.0. This

[gem5-dev] Review Request 2289: power: Add basic DVFS support for gem5

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2289/ --- Review request for Default. Repository: gem5 Description --- Changeset

Re: [gem5-dev] KvmCPU Behaviour

Hi Alex, That sounds rather odd. The only event that should happen when there are no request going through the memory system (the KVM CPU operates directly on the underlying backing store), is the refresh, which happens roughly every 64 ms. Could you elaborate on what event it is you are

Re: [gem5-dev] Review Request 2301: config: add ethernet support for x86 fullsystem

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2301/#review5136 --- configs/common/FSConfig.py http://reviews.gem5.org/r/2301/#comment4657

Re: [gem5-dev] Review Request 2286: mem: DRAMPower trace formatting script

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2286/#review5138 --- It would be great to get some feedback if anyone has actually used this.

Re: [gem5-dev] Review Request 2301: config: add ethernet support for x86 fullsystem

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2301/#review5139 --- configs/common/FSConfig.py http://reviews.gem5.org/r/2301/#comment4659

Re: [gem5-dev] Review Request 2302: x86: make PioBus return BadAddress errors

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2302/#review5156 --- Perhaps I am missing something, but why would Ruby forward the packet to

Re: [gem5-dev] Review Request 2302: x86: make PioBus return BadAddress errors

On June 25, 2014, 2 p.m., Andreas Hansson wrote: Perhaps I am missing something, but why would Ruby forward the packet to the iobus in the first place if the address is not valid? Steve Reinhardt wrote: This is an FS thing, where you misspeculate in the kernel and generate a

[gem5-dev] changeset in gem5: mem: Add bank and rank indices as fields to t...

changeset e0e3efe3b1d5 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e0e3efe3b1d5 description: mem: Add bank and rank indices as fields to the DRAM bank This patch adds the index of the bank and rank as a field so that we can determine the identity

[gem5-dev] changeset in gem5: mem: DRAMPower trace formatting script

changeset 72277952d444 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=72277952d444 description: mem: DRAMPower trace formatting script This patch adds a first version of a script that processes the debug output and generates a command trace for

[gem5-dev] changeset in gem5: mem: DRAMPower trace output

changeset 0ad233f0a77d in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=0ad233f0a77d description: mem: DRAMPower trace output This patch adds a DRAMPower flag to enable off-line DRAM power analysis using the DRAMPower tool. A new DRAMPower flag is

[gem5-dev] changeset in gem5: mem: Extend DRAM row bits from 16 to 32 for l...

changeset 70333502b9b5 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=70333502b9b5 description: mem: Extend DRAM row bits from 16 to 32 for larger densities This patch extends the DRAM row bits to 32 to support larger density memories. Additional

Re: [gem5-dev] About changeset: 6bbb7ae309ac

Hi all, Apologies for the hiccup. The checkpoint upgrade script is now reflecting the change. Andreas On 01/07/2014 13:49, Stephan Diestelhorst via gem5-dev gem5-dev@gem5.org wrote: On Tuesday 01 July 2014 13:04:52 Nilay Vaish via gem5-dev wrote: The following changeset breaks existing

Re: [gem5-dev] Review Request 2279: cpu: `Minor' in-order CPU model

Hi Steve, Just to chime in here. There are definitely objects that are clocked and not ticked. Thus, as Andrew already suggested, the most sensible thing to do is derive TickedObject from ClockedObject. Andreas On 01/07/2014 18:44, Steve Reinhardt via gem5-dev gem5-dev@gem5.org wrote: Yes,

[gem5-dev] Livelock in twosys regression with lastest changeset

Hi all, It seems that the regression build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic livelocks with the latest changeset: changeset: 10251:878f2f30b12d tag: tip user:Anthony Gutierrez atgut...@umich.edu date:Wed Jul 02

Re: [gem5-dev] Review Request 2310: base: fix operator== for comparing EthAddr objects

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2310/#review5180 --- Ship it! Thanks for chasing this down - Andreas Hansson On July 7,

Re: [gem5-dev] Review Request 2302: x86: make PioBus return BadAddress errors

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2302/#review5181 --- Ship it! As I mentioned before, I'm not opposed this going in as is if

Re: [gem5-dev] Review Request 2305: dev: add an ethernet switch model

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2305/#review5182 --- src/dev/Ethernet.py http://reviews.gem5.org/r/2305/#comment4695

Re: [gem5-dev] Review Request 2315: config: force IO devices mapped to 0xC0000000-0xFFFF0000 and bridge these address to iobus for x86

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2315/#review5198 --- configs/common/FSConfig.py http://reviews.gem5.org/r/2315/#comment4752

Re: [gem5-dev] Review Request 2314: config, x86: swap bus_id of ISA/PCI in X86 IntelMPTable

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2314/#review5209 --- Ship it! I assume this changes the X86 FS regressions? If so, I've got

Re: [gem5-dev] Review Request 2315: config, x86: Ensure that PCI devs get bridged to the memory bus

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2315/#review5210 --- Ship it! Ship It! - Andreas Hansson On July 17, 2014, 9:40 a.m.,

Re: [gem5-dev] Review Request 2315: config, x86: Ensure that PCI devs get bridged to the memory bus

On July 17, 2014, 12:25 p.m., Andreas Hansson wrote: Ship It! I think this should be combined with http://reviews.gem5.org/r/2302/ such that any address that is now forwarded to the iobus, but not actually used is sent to a badaddr responder. - Andreas

Re: [gem5-dev] Review Request 2167: mem: refactor LRU cache tags and add random replacment tags

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2167/#review5218 --- src/mem/cache/tags/base_set_assoc.cc

Re: [gem5-dev] Review Request 2305: dev: add an ethernet switch model

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2305/#review5223 --- src/dev/etherswitch.cc http://reviews.gem5.org/r/2305/#comment4773

Re: [gem5-dev] Review Request 2316: mem: add tCCD to DRAM controller

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2316/#review5228 --- Thanks for the input Amin. One high-level question: what is the main aim

Re: [gem5-dev] Review Request 2305: dev: add an ethernet switch model

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2305/#review5229 --- Ship it! Ship It! - Andreas Hansson On July 24, 2014, 7:44 p.m.,

[gem5-dev] changeset in gem5: stats: Bump stats for the regressions using t...

changeset dc198e224a85 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=dc198e224a85 description: stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour. diffstat:

Re: [gem5-dev] Review Request 2246: config: Add hooks to enable new config sys

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2246/ --- (Updated July 28, 2014, 5:49 a.m.) Review request for Default. Repository: gem5

[gem5-dev] Review Request 2317: scons: Warn for incompatible gcc and binutils

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2317/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2318: config: Add SubSystem container for simobjects

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2318/ --- Review request for Default. Repository: gem5 Description --- Changeset

Re: [gem5-dev] Review Request 2316: mem: add tCCD to DRAM controller

On July 28, 2014, 12:34 a.m., Andreas Hansson wrote: Thanks for the input Amin. One high-level question: what is the main aim of the patch? Until now we have tried to keep the timing constraints to a minimum (without sacrificing fidelity). In general you could argue that tBURST can

[gem5-dev] changeset in gem5: cpu: Ensure the traffic generator suppresses ...

changeset d4090f0cab30 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d4090f0cab30 description: cpu: Ensure the traffic generator suppresses non-memory packets This patch adds a check to ensure that packets which are not going to a memory range are

[gem5-dev] Review Request 2324: sim: bump checkpoint version for multiple event queues

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2324/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2327: arm: support 16kb vm granules

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2327/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2325: mem: Fix address interleaving bug in DRAM controller

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2325/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2331: style: Add support for a style ignore list and ignore ext/

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2331/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2330: style: Fixup strange semantics in hg m5style

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2330/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2333: arm: Mark v7 cbz instructions as direct branches

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2333/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2336: arm: ISA X31 destination register fix

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2336/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2332: cpu: Fix cached block load behavior in o3 cpu

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2332/ --- Review request for Default. Repository: gem5 Description --- Changeset

Re: [gem5-dev] Review Request 2341: mem: write streaming support via WriteInvalidate promotion

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2341/ --- (Updated Aug. 14, 2014, 7:54 a.m.) Review request for Default. Repository: gem5

Re: [gem5-dev] Review Request 2340: cpu, mem: Make software prefetches non-blocking

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2340/ --- (Updated Aug. 15, 2014, 2:24 p.m.) Review request for Default. Repository: gem5

Re: [gem5-dev] Review Request 2325: mem: Fix address interleaving bug in DRAM controller

On Aug. 16, 2014, 2:13 a.m., Nilay Vaish wrote: While I don't understand why there are column bits at the lower end of the address, I suggest we change the name of the addressing policy to reflect that column address bits have two subsets. Obviously I need to work on my

[gem5-dev] Review Request 2351: misc: Update dependencies in README and fit in 80 char

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2351/ --- Review request for Default. Repository: gem5 Description --- Changeset

Re: [gem5-dev] Review Request 2337: arm: use condition code registers for ARM ISA

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2337/ --- (Updated Aug. 17, 2014, 10:48 a.m.) Review request for Default. Repository: gem5

[gem5-dev] Review Request 2352: base: Use the global Mersenne twister throughout

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2352/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2353: base: Use STL C++11 random number generation

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2353/ --- Review request for Default. Repository: gem5 Description --- Changeset

Re: [gem5-dev] Review Request 2325: mem: Fix address interleaving bug in DRAM controller

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2325/ --- (Updated Aug. 18, 2014, 12:27 p.m.) Review request for Default. Repository: gem5

Re: [gem5-dev] Review Request 2351: misc: Update dependencies in README and fit in 80 char

On Aug. 18, 2014, 5:03 p.m., Nilay Vaish wrote: I am fine with the patch as such. I think we should either maintain the dependencies here in this file or on the website. I don't see why we would like maintain them in two different places unless we can link them so that one

Re: [gem5-dev] Review Request 2327: arm: support 16kb vm granules

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2327/ --- (Updated Aug. 18, 2014, 9:55 p.m.) Review request for Default. Repository: gem5

[gem5-dev] Review Request 2354: arch, cpu: Factor out the ExecContext into a proper base class

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2354/ --- Review request for Default. Repository: gem5 Description --- Changeset

Re: [gem5-dev] Review Request 2351: misc: Update dependencies in README and fit in 80 char

On Aug. 18, 2014, 5:03 p.m., Nilay Vaish wrote: I am fine with the patch as such. I think we should either maintain the dependencies here in this file or on the website. I don't see why we would like maintain them in two different places unless we can link them so that one

Re: [gem5-dev] Review Request 2351: misc: README direct to website for dependencies

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2351/ --- (Updated Aug. 19, 2014, 9:22 p.m.) Review request for Default. Summary (updated)

[gem5-dev] Review Request 2357: config: Add port splicing capability to PortRef class

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2357/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2356: config: Update Streamline scripts and configs

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2356/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2355: config: Refactor RealviewEMM to fit into new config system

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2355/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2359: arm: Assume we have a kernel that supports pci devices

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2359/ --- Review request for Default. Repository: gem5 Description --- Changeset

[gem5-dev] Review Request 2360: arm: Support 2GB of memory for AArch64 systems

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2360/ --- Review request for Default. Repository: gem5 Description --- Changeset

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