[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Partial SVE2 Implementation

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70277?usp=email ) Change subject: arch-arm: Partial SVE2 Implementation .. arch-arm: Partial SVE2 Implementation

[gem5-dev] [S] Change in gem5/gem5[develop]: mem: Fix SW prefetch asynchronous handling

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70117?usp=email ) Change subject: mem: Fix SW prefetch asynchronous handling .. mem: Fix SW prefetch asynchronous

[gem5-dev] [XS] Change in gem5/gem5[develop]: misc: Update the .git-blame-ignore-revs to ignore flynt commit

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/69037?usp=email ) Change subject: misc: Update the .git-blame-ignore-revs to ignore flynt commit .. misc: Update the .git-

[gem5-dev] [XS] Change in gem5/gem5[develop]: base: Remove unnecessary DEBUG guard

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/69077?usp=email ) Change subject: base: Remove unnecessary DEBUG guard .. base: Remove unnecessary DEBUG guard There is no p

[gem5-dev] [S] Change in gem5/gem5[develop]: sim: Remove unused SimObject::debugObjectBreak

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/69078?usp=email ) Change subject: sim: Remove unused SimObject::debugObjectBreak .. sim: Remove unused SimObject::debugObject

[gem5-dev] [M] Change in gem5/gem5[develop]: misc: Rename DEBUG macro into GEM5_DEBUG

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/69079?usp=email ) Change subject: misc: Rename DEBUG macro into GEM5_DEBUG .. misc: Rename DEBUG macro into GEM5_DEBUG The D

[gem5-dev] [S] Change in gem5/gem5[develop]: sim: Remove unused SimObject::debugObjectBreak

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/69078?usp=email ) Change subject: sim: Remove unused SimObject::debugObjectBreak .. sim: Remove unused SimObject::

[gem5-dev] [M] Change in gem5/gem5[develop]: misc: Rename DEBUG macro into GEM5_DEBUG

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/69079?usp=email ) Change subject: misc: Rename DEBUG macro into GEM5_DEBUG .. misc: Rename DEBUG macro into GEM5_D

[gem5-dev] [XS] Change in gem5/gem5[develop]: base: Remove unnecessary DEBUG guard

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/69077?usp=email ) Change subject: base: Remove unnecessary DEBUG guard .. base: Remove unnecessary DEBUG guard Th

[gem5-dev] [XS] Change in gem5/gem5[develop]: misc: Update the .git-blame-ignore-revs to ignore flynt commit

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/69037?usp=email ) Change subject: misc: Update the .git-blame-ignore-revs to ignore flynt commit .. misc: Updat

[gem5-dev] [XL] Change in gem5/gem5[develop]: misc: Use python f-strings for string formatting

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68957?usp=email ) Change subject: misc: Use python f-strings for string formatting .. misc: Use python f-strings for string f

[gem5-dev] [XL] Change in gem5/gem5[develop]: misc: Use python f-strings for string formatting

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68957?usp=email ) Change subject: misc: Use python f-strings for string formatting .. misc: Use python f-strings f

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Replace Loader with loader namespace in SME code

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/67333?usp=email ) Change subject: arch-arm: Replace Loader with loader namespace in SME code .. arch-arm: Replace Loader with

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Replace Loader with loader namespace in SME code

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/67333?usp=email ) Change subject: arch-arm: Replace Loader with loader namespace in SME code .. arch-arm: Replace

[gem5-dev] [S] Change in gem5/gem5[develop]: system-arm: Enable SME in the bootloader

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/64341?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: system-arm: Enable SME in the bo

[gem5-dev] [M] Change in gem5/gem5[develop]: arch,cpu: Add boilerplate support for matrix registers

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/64333?usp=email ) Change subject: arch,cpu: Add boilerplate support for matrix registers .. arch,cpu: Add boilerplate support

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Add system registers added/used by SME

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/64335?usp=email ) Change subject: arch-arm: Add system registers added/used by SME .. arch-arm: Add system registers added/us

[gem5-dev] [M] Change in gem5/gem5[develop]: arch, arch-arm, cpu: Add matrix reg support to the ISA Parser

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/64338?usp=email ) Change subject: arch, arch-arm, cpu: Add matrix reg support to the ISA Parser .. arch, arch-arm, cpu: Ad

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement SME access traps and extend the SVE ones

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/64337?usp=email ) Change subject: arch-arm: Implement SME access traps and extend the SVE ones .. arch-arm: Implement SME acc

[gem5-dev] [M] Change in gem5/gem5[develop]: cpu-o3: Remove obsolete getRegIds and getTrueId

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/64332?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: cpu-o3: Remove obsolete getRegId

[gem5-dev] [S] Change in gem5/gem5[develop]: mem-cache: masked writes are not whole-line writes

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/64340?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mem-cache: masked writes are not

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add interfaces to set and get SME vector length

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/64336?usp=email ) Change subject: arch-arm: Add interfaces to set and get SME vector length .. arch-arm: Add interfaces to se

[gem5-dev] [S] Change in gem5/gem5[develop]: cpu-o3: print VecPredReg not VecReg

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/64342?usp=email ) Change subject: cpu-o3: print VecPredReg not VecReg .. cpu-o3: print VecPredReg not VecReg Fix a DPRINTF t

[gem5-dev] [S] Change in gem5/gem5[develop]: util: use origin/develop as default upstream branch

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/67331?usp=email ) Change subject: util: use origin/develop as default upstream branch .. util: use origin/develop as default

[gem5-dev] [S] Change in gem5/gem5[develop]: util: use origin/develop as default upstream branch

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/67331?usp=email ) Change subject: util: use origin/develop as default upstream branch .. util: use origin/develop

[gem5-dev] [M] Change in gem5/gem5[develop]: cpu: Formalize a CPU cluster class in the gem5 standard library

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/65891?usp=email ) Change subject: cpu: Formalize a CPU cluster class in the gem5 standard library .. cpu: Formalize a CPU

[gem5-dev] [M] Change in gem5/gem5[develop]: configs: Start using the new CpuCluster class in example/arm

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/65892?usp=email ) Change subject: configs: Start using the new CpuCluster class in example/arm .. configs: Start using the ne

[gem5-dev] [S] Change in gem5/gem5[develop]: util: Update run_gem5_fs.sh script with AArch64 platform

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66856?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util: Update run_gem5_fs.sh scri

[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Include libraries when building gem5 as a shared object

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66855?usp=email ) Change subject: scons: Include libraries when building gem5 as a shared object .. scons: Include librari

[gem5-dev] [S] Change in gem5/gem5[develop]: util: Update util-tlm to require C++17

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66853?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util: Update util-tlm to require

[gem5-dev] [S] Change in gem5/gem5[develop]: util: Fix missing include of sim/core.hh in util-tlm

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66852?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util: Fix missing include of sim

[gem5-dev] [S] Change in gem5/gem5[develop]: util: ext/systemc is importing env Environment instead of main

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66854?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util: ext/systemc is importing en

[gem5-dev] [S] Change in gem5/gem5[develop]: util: cxxConfigInit has been removed by gem5

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66851?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util: cxxConfigInit has been rem

[gem5-dev] [S] Change in gem5/gem5[develop]: dev: Fix -Wunused-variable in structured binding

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66891?usp=email ) Change subject: dev: Fix -Wunused-variable in structured binding .. dev: Fix -Wunused-variable in structure

[gem5-dev] [S] Change in gem5/gem5[develop]: dev: Fix -Wunused-variable in structured binding

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66891?usp=email ) Change subject: dev: Fix -Wunused-variable in structured binding .. dev: Fix -Wunused-variable i

[gem5-dev] [S] Change in gem5/gem5[develop]: util: ext/systemc is importing env Environment instead of main

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66854?usp=email ) Change subject: util: ext/systemc is importing env Environment instead of main .. util: ext/s

[gem5-dev] [S] Change in gem5/gem5[develop]: util: Update util-tlm to require C++17

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66853?usp=email ) Change subject: util: Update util-tlm to require C++17 .. util: Update util-tlm to require C++17

[gem5-dev] [S] Change in gem5/gem5[develop]: util: Fix missing include of sim/core.hh in util-tlm

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66852?usp=email ) Change subject: util: Fix missing include of sim/core.hh in util-tlm .. util: Fix missing includ

[gem5-dev] [S] Change in gem5/gem5[develop]: util: Update run_gem5_fs.sh script with AArch64 platform

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66856?usp=email ) Change subject: util: Update run_gem5_fs.sh script with AArch64 platform .. util: Update run_gem

[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Include libraries when building gem5 as a shared object

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66855?usp=email ) Change subject: scons: Include libraries when building gem5 as a shared object .. scons: Incl

[gem5-dev] [S] Change in gem5/gem5[develop]: util: cxxConfigInit has been removed by gem5

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66851?usp=email ) Change subject: util: cxxConfigInit has been removed by gem5 .. util: cxxConfigInit has been rem

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove deprecated Armv7 debug Vector Catch

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66251?usp=email ) Change subject: arch-arm: Remove deprecated Armv7 debug Vector Catch .. arch-arm: Remove deprecated Armv7 d

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Allow GICv3 to be externally(publicly) updated

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66271?usp=email ) Change subject: dev-arm: Allow GICv3 to be externally(publicly) updated .. dev-arm: Allow GICv3 to be exter

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Setup TC/ISA at construction time 2nd attempt

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/65931?usp=email ) Change subject: arch-arm: Setup TC/ISA at construction time 2nd attempt .. arch-arm: Setup TC/ISA at constr

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Allow GICv3 to be externally(publicly) updated

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66271?usp=email ) Change subject: dev-arm: Allow GICv3 to be externally(publicly) updated .. dev-arm: Allow GICv3

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove deprecated Armv7 debug Vector Catch

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66251?usp=email ) Change subject: arch-arm: Remove deprecated Armv7 debug Vector Catch .. arch-arm: Remove depreca

[gem5-dev] [M] Change in gem5/gem5[develop]: Revert "arch-arm: Revert 'Setup TC/ISA at construction time..'"

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/65931?usp=email ) Change subject: Revert "arch-arm: Revert 'Setup TC/ISA at construction time..'" .. Revert "ar

[gem5-dev] [M] Change in gem5/gem5[develop]: configs: Start using the new CpuCluster class in example/arm

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/65892?usp=email ) Change subject: configs: Start using the new CpuCluster class in example/arm .. configs: Start u

[gem5-dev] [M] Change in gem5/gem5[develop]: cpu: Formalize a CPU cluster class in the gem5 standard library

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/65891?usp=email ) Change subject: cpu: Formalize a CPU cluster class in the gem5 standard library .. cpu: Forma

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Setup TC/ISA at construction time of Gicv3CPUInterface

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/65291?usp=email ) Change subject: dev-arm: Setup TC/ISA at construction time of Gicv3CPUInterface .. dev-arm: Setup TC/ISA

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Setup ISA::gicv3CpuInterface on demand only

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/65174?usp=email ) Change subject: arch-arm: Setup ISA::gicv3CpuInterface on demand only .. arch-arm: Setup ISA::gicv3CpuInter

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Setup TC/ISA at construction time of Gicv3CPUInterface

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/65291?usp=email ) Change subject: dev-arm: Setup TC/ISA at construction time of Gicv3CPUInterface .. dev-arm: S

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Fix GICv3 List register mapping

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/65172?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Fix GICv3 List registe

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Fix access permissions for GICv3 cpu registers

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/65171?usp=email ) Change subject: arch-arm: Fix access permissions for GICv3 cpu registers .. arch-arm: Fix access permission

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::haveGICv3CpuIfc method

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/65173?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Remove ISA::haveGICv3C

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::haveGICv3CpuIfc method

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/65173?usp=email ) Change subject: arch-arm: Remove ISA::haveGICv3CpuIfc method .. arch-arm: Remove ISA::haveGICv3C

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Fix GICv3 List register mapping

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/65172?usp=email ) Change subject: arch-arm: Fix GICv3 List register mapping .. arch-arm: Fix GICv3 List register m

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Fix access permissions for GICv3 cpu registers

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/65171?usp=email ) Change subject: arch-arm: Fix access permissions for GICv3 cpu registers .. arch-arm: Fix access

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Setup ISA::gicv3CpuInterface on demand only

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/65174?usp=email ) Change subject: arch-arm: Setup ISA::gicv3CpuInterface on demand only .. arch-arm: Setup ISA::gi

[gem5-dev] [S] Change in gem5/gem5[develop]: sim, arch: Remove Fault debug flag

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/59152 ) Change subject: sim, arch: Remove Fault debug flag .. sim, arch: Remove Fault debug flag There is already

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Memoize computeAddrTop in the MMU code

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/59151 ) Change subject: arch-arm: Memoize computeAddrTop in the MMU code .. arch-arm: Memoize computeAddrTop in th

[gem5-dev] [L] Change in gem5/gem5[develop]: base: Add generic Memoizer class

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/59149 ) Change subject: base: Add generic Memoizer class .. base: Add generic Memoizer class This class implement

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Split purifyTaggedAddr in two sub-functions

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/59150 ) Change subject: arch-arm: Split purifyTaggedAddr in two sub-functions .. arch-arm: Split purifyTaggedAddr

[gem5-dev] [M] Change in gem5/gem5[develop]: mem-ruby: Support for unaddressed mem requests in the Sequencer

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/57294 ) Change subject: mem-ruby: Support for unaddressed mem requests in the Sequencer .. mem-ruby: Support for unaddress

[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby: CHI fix for WUs on local+upstream line

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/57299 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mem-ruby: CHI fix for WUs on local+upstrea

[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby: Added upstream_nodes to AbstractController

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/57296 ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mem-ruby: Added upstream_nodes to Abstract

[gem5-dev] [M] Change in gem5/gem5[develop]: mem-ruby: AbstractController unaddressed profiling

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/57297 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mem-ruby: AbstractController unaddressed p

[gem5-dev] [M] Change in gem5/gem5[develop]: cpu: Handle external TLBI Sync requests in O3CPU

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/57292 ) Change subject: cpu: Handle external TLBI Sync requests in O3CPU .. cpu: Handle external TLBI Sync requests in O3CPU

[gem5-dev] [M] Change in gem5/gem5[develop]: mem-ruby: Support for unaddressed mem requests in the RubyRequest

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/57293 ) Change subject: mem-ruby: Support for unaddressed mem requests in the RubyRequest .. mem-ruby: Support for unaddre

[gem5-dev] [M] Change in gem5/gem5[develop]: mem-ruby: Add TLBI callbacks to the RubyPort

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/57295 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mem-ruby: Add TLBI callbacks to the RubyPo

[gem5-dev] [S] Change in gem5/gem5[develop]: cpu: Handle external TLBI Sync requests in TimingCPU

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/57291 ) Change subject: cpu: Handle external TLBI Sync requests in TimingCPU .. cpu: Handle external TLBI Sync requests in Ti

[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby: Support for mem commands in the Sequencer

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58510 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mem-ruby: Support for mem commands in the

[gem5-dev] [M] Change in gem5/gem5[develop]: cpu, arch-arm: Rename initiateSpecialMemCmd to initateMemMgmtCmd

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58511 ) Change subject: cpu, arch-arm: Rename initiateSpecialMemCmd to initateMemMgmtCmd .. cpu, arch-arm: Rename initiate

[gem5-dev] [S] Change in gem5/gem5[develop]: mem: Introduce Request::isMemMgmt to cover memory management cmds

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58509 ) Change subject: mem: Introduce Request::isMemMgmt to cover memory management cmds .. mem: Introduce Request::isMem

[gem5-dev] [S] Change in gem5/gem5[develop]: mem: Add Request factory method for memory management command

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58357 ) Change subject: mem: Add Request factory method for memory management command .. mem: Add Request factory method f

[gem5-dev] Change in gem5/gem5[develop]: cpu, arch-arm: Rename initiateSpecialMemCmd to initateMemMgmtCmd

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58511 ) Change subject: cpu, arch-arm: Rename initiateSpecialMemCmd to initateMemMgmtCmd .. cpu, arch-arm: Rena

[gem5-dev] Change in gem5/gem5[develop]: mem: Introduce Request::isMemCmd to cover memory commands

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58509 ) Change subject: mem: Introduce Request::isMemCmd to cover memory commands .. mem: Introduce Request::isMem

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Support for mem commands in the Sequencer

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58510 ) Change subject: mem-ruby: Support for mem commands in the Sequencer .. mem-ruby: Support for mem commands

[gem5-dev] Change in gem5/gem5[develop]: mem: Add Request constructor for special memory command

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58357 ) Change subject: mem: Add Request constructor for special memory command .. mem: Add Request constructor fo

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Move ISA::redirectRegVHE to .cc file

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58116 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Move ISA::redirectRegVHE to .cc

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix ISA::redirectRegVHE method

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58117 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Fix ISA::redirectRegVHE method .

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: _NS used in AArch32 if EL3 is AArch64

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58118 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: _NS used in AArch32 if EL3 is AA

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix RW permission access for _EL12 registers

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58114 ) Change subject: arch-arm: Fix RW permission access for _EL12 registers .. arch-arm: Fix RW permission access for _EL1

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Remove unused ELIsInHost redirection for CNTKCTL_EL1

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58115 ) Change subject: dev-arm: Remove unused ELIsInHost redirection for CNTKCTL_EL1 .. dev-arm: Remove unused ELIsInHost

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Use uint64_t for AArch64 MiscReg operands

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58113 ) Change subject: arch-arm: Use uint64_t for AArch64 MiscReg operands .. arch-arm: Use uint64_t for AArch64 MiscReg ope

[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Implement EL2 Secure Virtual Timer

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58112 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm, dev-arm: Implement EL2 Secure Vi

[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Implement EL2 Secure Physical Timer

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58111 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm, dev-arm: Implement EL2 Secure Ph

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Rename GenericTimer interrupts

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58109 ) Change subject: dev-arm: Rename GenericTimer interrupts .. dev-arm: Rename GenericTimer interrupts The Arm Architect

[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Implement EL2 Non-secure Virtual Timer

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58110 ) Change subject: arch-arm, dev-arm: Implement EL2 Non-secure Virtual Timer .. arch-arm, dev-arm: Implement EL2 Non-sec

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix ISA::redirectRegVHE method

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58117 ) Change subject: arch-arm: Fix ISA::redirectRegVHE method .. arch-arm: Fix ISA::redirectRegVHE method This

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix RW permission access for _EL12 registers

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58114 ) Change subject: arch-arm: Fix RW permission access for _EL12 registers .. arch-arm: Fix RW permission acce

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Rename GenericTimer interrupts

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58109 ) Change subject: dev-arm: Rename GenericTimer interrupts .. dev-arm: Rename GenericTimer interrupts The Ar

[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Implement EL2 Secure Virtual Timer

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58112 ) Change subject: arch-arm, dev-arm: Implement EL2 Secure Virtual Timer .. arch-arm, dev-arm: Implement EL2

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: _NS used in AArch32 if EL3 is AArch64

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58118 ) Change subject: arch-arm: _NS used in AArch32 if EL3 is AArch64 .. arch-arm: _NS used in AArch32 if EL3 is

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Move ISA::redirectRegVHE to .cc file

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58116 ) Change subject: arch-arm: Move ISA::redirectRegVHE to .cc file .. arch-arm: Move ISA::redirectRegVHE to .c

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Use uint64_t for AArch64 MiscReg operands

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58113 ) Change subject: arch-arm: Use uint64_t for AArch64 MiscReg operands .. arch-arm: Use uint64_t for AArch64

[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Implement EL2 Secure Physical Timer

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58111 ) Change subject: arch-arm, dev-arm: Implement EL2 Secure Physical Timer .. arch-arm, dev-arm: Implement EL2

[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Implement EL2 Non-secure Virtual Timer

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58110 ) Change subject: arch-arm, dev-arm: Implement EL2 Non-secure Virtual Timer .. arch-arm, dev-arm: Implement

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Remove unused ELIsInHost redirection for CNTKCTL_EL1

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58115 ) Change subject: dev-arm: Remove unused ELIsInHost redirection for CNTKCTL_EL1 .. dev-arm: Remove unused

[gem5-dev] Change in gem5/gem5[develop]: util: Remove python3-six package from dockerfiles

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/57969 ) Change subject: util: Remove python3-six package from dockerfiles .. util: Remove python3-six package from dockerfile

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