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Joel, I have pushed in the patch the removes the options trace-help and
trace-flags. But trace-start and trace-file work as before. You can use
them in conjunction with debug-flags.
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On Fri, 6 May 2011, Nilay Vaish wrote:
I was thinking og doing it since Nate is not around. I'll do
I was thinking og doing it since Nate is not around. I'll do it soon.
instance, trace-flags, and trace-file are still accepted, but they
don't
do anything now. They should be eliminated from the message. We're also
missing the equivalent of trace-start and trace-file. Do you mind
Hey guys,
I wasn't sure what the intended outcome with tracing v. debugging was
going to be. It sounds like the move is to debug as a more general term,
though it will support all of the trace functionality. In that case, my
confusion arose from the naming of the flags. Since trace-file and
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Hey Nilay,
It looks like the tracing (debug) functionality is now working again,
but the M5 help message is still incorrect (and extremely misleading). For
instance, trace-flags, and trace-file are still accepted, but they don't
do anything now. They should be eliminated from the message.
I was thinking og doing it since Nate is not around. I'll do it soon.
--
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On Fri, 6 May 2011, Joel Hestness wrote:
Hey Nilay,
It looks like the tracing (debug) functionality is now working again,
but the M5 help message is still incorrect (and extremely misleading). For
instance,
Diff: http://reviews.m5sim.org/r/531/diff
Testing
---
Thanks,
Gabe
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Forwarding this from m5-users to m5-dev:
While we are on this point, is there any reason that we still use the
cpu/smt.hh file?
The only thing that this file does is set a global variable extern int
maxThreadsPerCPU which is in turn used to setup the cache stats talked
about in this discussion
Can we impose restriction on the membership of the wiki? It seems that
bogus pages are being created. For example --
http://m5sim.org/wiki/index.php/User:MiriamGSpeights
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Well, in requires a valid email address and clicking a link to create an
account and an account is required to edit a page. Any more work and I don't
think people would contribute. I've gone around and cleaned up stuff from the
last year.
Captcha to create the account?
nate
A long time ago we thought about putting a m5/system/ directory where
we would put architecture dependent code system code (boot loaders,
alpha console, etc). How do we feel about this? We could move the alpha
code in there now that HP relicensed it. Additionally, I've got a tiny
ARM boot loader
A long time ago we thought about putting a m5/system/arch directory where
we would put architecture dependent code system code (boot loaders, alpha
console, etc). How do we feel about this? We could move the alpha code in
there now that HP relicensed it. Additionally, I've got a tiny ARM boot
The best place to look is in the .py files in the src directory. These
are where the parameters are set up, and there isn't really any other
documentation. You shouldn't change the values in those files since
those just set the defaults, but that will let you know what
parameters there are
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hi all,
i have not found m5.object module but in the web page it is
mentioned
These Python classes are defined in a Python module called m5.objects.
(The Python class definitions for these objects can be found in the source
tree in the src/python/m5/objects directory.
i am having this
Aside from building a Linux kernel, you will need to build and configure a
disk image as well, which is also a fair amount of work. I've found that,
unfortunately due to the long simulation time of Linux boot up, the
iteration time to debug the X86_FS bootup is quite long.
Really, bootup is
Hi,
This is probably a question for Nate, Gabe or Ali:
I have built the m5 util application for x86 and I have been testing it
under X86_FS simulation. It looks like /sbin/m5 readfile is failing to
print the script to the console of the simulated system. I have been able
to verify that the
This is probably a question for Nate, Gabe or Ali:
I have built the m5 util application for x86 and I have been testing it
under X86_FS simulation. It looks like /sbin/m5 readfile is failing to
print the script to the console of the simulated system. I have been able
to verify that the
://www.csee.usf.edu/~sroy
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--
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Ph.D. Candidate
Department of Computer Science and Engineering
University of South Florida, Tampa
http://www.csee.usf.edu/~sroy
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Ph.D. Candidate
Department of Computer Science and Engineering
University of South Florida, Tampa
http://www.csee.usf.edu/~sroy
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Ph.D. Candidate
Department of Computer Science and Engineering
University of South Florida, Tampa
http://www.csee.usf.edu/~sroy
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Department of Computer Science and Engineering
University of South Florida, Tampa
http://www.csee.usf.edu/~sroy
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[I am replying to m5-dev instead of m5-users]
Hello Ali,
Which benchmarks should one use to test the implementation of these
instructions?
Either I or Vidya Sangkar, a labmate of mine, can work on it. But it
has to be after Nov 17th. Is that timeline is ok?
regards,
Soumyaroop
On 10/29/09,
[Sorry, Alex hit send last time]
Awesome!
As a note, I was looking into this a little bit and there was some
stuff about tomcat 6 not working. I'm not sure if this is still true,
but just in case.
Nate
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Hi,
well if you are interested in doing a some debugging you can start to
uncover the problem. So that probably would signal this conversation
go to the m5-dev list instead of m5-users (I think at least).
If I were you, these would be my steps to figure out the problem.
(1) Run a Sparc Hello
I'm sorta just dreaming here, but I'm getting used to occasionally browsing
the code through repo.m5sim.org, and it would be really nice if:
1. We had a web-based cross-reference (like lxr), so I don't have to switch
from firefox to an ssh session running cscope.
2a. Better yet, if there was a
changeset 94c016415053 in /z/repo/m5-stable
details: http://repo.m5sim.org/m5-stable?cmd=changeset;node=94c016415053
summary: SPARC: Fix the parenthesis in inUserMode.
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
src/arch/sparc/utility.hh |4 ++--
diffs (14 lines):
diff -r
Thanks for updating these Gabe!
On Sun, Jul 5, 2009 at 12:44 AM, Gabe Blackgbl...@eecs.umich.edu wrote:
changeset eae881827513 in /z/repo/m5-stable
details: http://repo.m5sim.org/m5-stable?cmd=changeset;node=eae881827513
summary: inorder: Fix up some reference stats.
diffstat:
6 files
changeset eae881827513 in /z/repo/m5-stable
details: http://repo.m5sim.org/m5-stable?cmd=changeset;node=eae881827513
summary: inorder: Fix up some reference stats.
diffstat:
6 files changed, 112 insertions(+), 112 deletions(-)
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini |2
Dear M5,
the M5 page DynInst has been changed on 06:07, 24 June 2009 by 3shmaoy, see
http://www.m5sim.org/wiki/index.php/DynInst for the current version.
See http://www.m5sim.org/wiki/index.php?title=DynInstdiff=0oldid=1649
for all changes since your last visit.
Editor's summary: - This is a
ASHMAWY Amr wrote:
Hi,
I was following the replies/discussion for my question
I just want to confirm,
- I got the point that M5 can support heterogeneous multicores but only they
have the same ISA
- The problem would be if the different cores use different ISA, (this can be
added with
To avoid spamming the other folks on m5-users who might not be
interested in the discussion I'm moving this over to m5-dev.
I think making the ISA a class with only (or mostly) static members
would be reasonable since I expect the compiler would pretty much
figure out they're just in a
Hi,
I was following the replies/discussion for my question
I just want to confirm,
- I got the point that M5 can support heterogeneous multicores but only they
have the same ISA
- The problem would be if the different cores use different ISA, (this can be
added with considerable effort.
was
This definitely isnt a pressing issue, but is there any facility in
M5 so that I can give assert a message to go along with breaking
execution. I remember at Intel we had something
like this available in the simulator.
Panic, Fatal, etc. dont quite do the trick since you still typically
need to
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The m5 binary on the disk image that we distribute doesn't support the
pin command. You'll need to compile it yourself. Additionally, I don't
believe libc on the disk image supports sched_setaffinity (needed by
pin). This is something we need to fix, but it unfortunately involves
distributing
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changeset b1beee9351a4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b1beee9351a4
summary: eventq: Clean up the Event class so that it uses fewer bytes. This
diffstat:
2 files changed, 2 insertions(+), 4 deletions(-)
src/sim/eventq.cc |3 +--
src/sim/eventq.hh |3 +--
changeset f0f8a3ee5aad in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f0f8a3ee5aad
summary: eventq: new eventq data structure. The new data structure is singly
diffstat:
2 files changed, 7 insertions(+), 1 deletion(-)
src/sim/eventq.cc |1 +
src/sim/eventq.hh |7
changeset cf464d02bc57 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cf464d02bc57
summary: eventq: change the event datastructure back to LIFO.
diffstat:
2 files changed, 2 insertions(+), 4 deletions(-)
src/sim/eventq.cc |5 ++---
src/sim/eventq.hh |1 -
diffs (270
One unknown is whether or not to uncomment the call to
disconnectFromPeer() in Port::setPort(). Conceptually it should be
there, and I believe having it commented out was the source of the
memory leak that was giving Ali trouble. If Ali's fix got rid of all
the places where we have N:1
changeset 6899b894166f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6899b894166f
summary: After a checkpoint (and thus a stats reset), the
not_idle_fraction/notIdleFraction statistic is really wrong.
changeset 89a6483d7047 in /z/repo/m5
details:
::disconnectFromPeer()
-{
-if (peer) {
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) {
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DefaultPeerPort(this)),
+owner(_owner)
{
}
Port::~Port()
{
+disconnectFromPeer();
+}
+
+void
+Port::disconnectFromPeer()
+{
+if (peer) {
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I thought about that and got rid of the ones in CopyString*().
However, without passing the tc object and creating a new port the
getfile (m5 op that stucks in the config file) fails to work
correctly. There must be something more going on there, but I couldn't
figure out what was happening.
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changeset ebec0a848220 in /z/repo/m5-stable
details: http://repo.m5sim.org/m5-stable?cmd=changeset;node=ebec0a848220
summary: Checkpoinging/SWIG: Undo part of changeset 5464 since it broke
checkpointing.
diffstat:
1 file changed, 1 deletion(-)
src/python/swig/event.i |1 -
diffs (14 lines):
*object, Tick when);
-class CountedDrainEvent
-{
+class Event;
+class CountedDrainEvent : public Event {
public:
void setCount(int _count);
};
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changeset 94a7bb476fca in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=94a7bb476fca
summary: Generate more useful error messages for unconnected ports.
changeset 88f1e9295945 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=88f1e9295945
summary: Make bus
changeset 840f91d062a9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=840f91d062a9
summary: Ethernet: share statistics between all ethernet devices and apply some
changeset c12f0b8833d2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c12f0b8833d2
summary:
changeset c8571e8ce7b6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c8571e8ce7b6
summary: imported patch sim_object_params.diff
diffstat:
2 files changed, 31 insertions(+)
src/python/m5/SimObject.py |7 +++
src/sim/sim_object_params.hh | 24
changeset ca055528a3b3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ca055528a3b3
summary: Rename SimConsole to Terminal since it makes more sense
changeset 6130dd6ee658 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6130dd6ee658
summary: Change the
changeset 2830b6c18c9f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2830b6c18c9f
summary: PacketFifo: Get slack out of the EthPacketData structure. This allows
diffstat:
4 files changed, 36 insertions(+), 17 deletions(-)
src/dev/etherpkt.hh |8
changeset dc6a459769a1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=dc6a459769a1
summary: inet: initialization fixes.
diffstat:
2 files changed, 15 insertions(+), 15 deletions(-)
src/base/inet.hh | 15 ++-
src/dev/ns_gige.cc | 15 +--
diffs (204
I don't think this works, given that you've (still) got a single
global static instance of DefaultPeerPort... right? I ask because
this patch looks frighteningly familiar... I just did the same thing
last week (including the identical class rename :-) ) but mine was
more complicated because
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I sympathize with Ali's concerns... the current situation is pretty
much the opposite extreme of the 3-6 month release cycle I was
advocating not that long ago. My main motivation was that a longer
cycle would allow more time for people to find problems, and the
criticism was that a lot of the
I think the bottom line is that as long as you want to do extensive
non-automated testing before declaring something as stable then you
have to have (1) some sort of freeze prior to that point so that your
testers are all testing the same thing (modulo bug fixes) and (2) some
group of people
In the case of some bug fix that needs to be released immediately that
fix could be pushed directly to m5-stable and pulled into m5.
This is an intriguing idea. OpenBSD does this on a 6 month schedule
and it works pretty well. Several other groups (ubuntu for example)
have also started on
I figured we'd make an exception for this month until all the pending
changes get in. We can start the new schedule in July (so the
earliest m5-stable update under the new plan would be ~Aug 1). Should
we should freeze m5-stable where it is now, or if not, when?
Ok, I like that. I think
changeset a9b2504432d1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a9b2504432d1
summary: add compile flags to m5
diffstat:
2 files changed, 29 insertions(+)
src/python/swig/core.i |1 +
src/sim/compile_info.cc | 28
diffs (102 lines):
changeset 7c18f61da616 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7c18f61da616
summary: params: Prevent people from setting attributes on vector params.
diffstat:
1 file changed, 2 insertions(+)
src/python/m5/params.py |2 ++
diffs (14 lines):
diff -r a9b2504432d1 -r
nathan binkert wrote:
We should probably open this discussion up to the m5-users list a bit
to get some feedback and see how many people even plan to track us.
We're likely to want to sync with a stable, well tested, m5 state a few
times a year. Having an m5 stability point every 6 months
On Sun, Jun 15, 2008 at 9:37 PM, Nathan Binkert [EMAIL PROTECTED] wrote:
changeset 758c2413765a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=758c2413765a
summary: port: Clean up default port setup and port switchover code.
[...]
diff -r 7c18f61da616 -r 758c2413765a
Thanks to everyone for all the effort.
BTW, the wiki page lists the development repo as m5-dev thought in
reality it's just m5 (as always). Which name should we stick with?
I vote m5.
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changeset 7eb7f0f5e79f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7eb7f0f5e79f
summary: Fix various SWIG warnings
diffstat:
4 files changed, 2 insertions(+), 2 deletions(-)
src/arch/mips/MipsTLB.py |1 +
src/arch/x86/X86TLB.py |1 -
src/python/swig/event.i |1
changeset 4cff095bbf2b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4cff095bbf2b
summary: Add hg commands for style check so you can check at times other than
commit
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
util/style.py |2 +-
diffs (123 lines):
diff
changeset a1981d557252 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a1981d557252
summary: MemReq: Add option to reset the time on a request.
diffs (11 lines):
diff -r 4cff095bbf2b -r a1981d557252 src/mem/request.hh
--- a/src/mem/request.hhSat Jun 14 19:37:26 2008
Dear M5 Users,
Today, it is our pleasure to announce the public availability of the
M5 repository.
It was quite a bit of work, but we've managed to get the copyright
holders on M5 code to agree to a single BSD style license for M5. The
one major exception to this is the new x86 code. This code
Today, it is our pleasure to announce the public availability of the
M5 repository.
Great job everybody. Hopefully Friday the 13th doesn't turn out to be
a problem :)
Nate
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changeset 943f436efe9b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=943f436efe9b
summary: scons: fix program_info.cc generation
diffstat:
1 file changed, 1 deletion(-)
src/SConscript |1 -
diffs (25 lines):
diff -r 58bee6bdae6f -r 943f436efe9b src/SConscript
---
On Fri, Jun 13, 2008 at 3:33 PM, nathan binkert [EMAIL PROTECTED] wrote:
Today, it is our pleasure to announce the public availability of the
M5 repository.
Great job everybody. Hopefully Friday the 13th doesn't turn out to be
a problem :)
Thanks to everyone for all the effort.
BTW, the
changeset 9ffc2be2d925 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9ffc2be2d925
summary: Get rid of bogus cache assertion.
changeset b84a60dbf862 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b84a60dbf862
summary: Get rid of bogus bus assertion.
changeset 1af0b428ac2f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1af0b428ac2f
summary: Make sure that output files are always checked success before they're
used.
diffstat:
5 files changed, 14 insertions(+), 14 deletions(-)
src/base/output.cc |4 ++--
changeset 7738a042628b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7738a042628b
summary: SCons: More scons fixing for SCons bug 2006
diffstat:
1 file changed, 6 insertions(+)
src/kern/SConscript |6 ++
diffs (13 lines):
diff -r e4987b6ca365 -r 7738a042628b
Yea, it should definitely be a parameter... maybe a system parameter
rather than a workload parameter though (since in multi-programmed workloads
you actually have multiple workload objects).
I actually spoke to soon about this fix. Right now, I'm going through a
bunch of minor changes that
I sort of started adding Extending M5 tutorials in the documentation
on the WIKI page a while back so people can see how easy the
extension
capabilities of M5 are ( Making Your Own ISA/CPU Model)
However, i also think it would very cool if we have some example
scripts (and tutorials using those
I cloned a fresh M5 out the repo and I'm trying to build
ALPHA_SE/AtomicSimpleCPU M5 in Cygwin and I get the following error:
g++ -o build/ALPHA_SE/python/swig/core_wrap.do -c -pipe
-fno-strict-aliasing -Wall -Wno-sign-compare -Werror -Wundef
-Wno-uninitialized -ggdb3 -DTHE_ISA=ALPHA_ISA -DDEBUG
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