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Re: [m5-dev] sparc_fs follow-up
Sure, I will. I didn't make any changes really, but I think my code must be different from yours by a little because for example I don't have function tc-contextId()), instead I had to use tc-readCpuId() I am not sure why our code base would be different and by how much, but that could be why yours is running fine and mine segfaults. Also, I think that you were right to try to change CPU in 1g2p.pdesc but the thing is that guest is assigned pid 0x1, so I am not sure if this could be a problem or not if guest pid is the same as CPU pid. I'm trying it out now. Polina On Thu, Mar 5, 2009 at 12:52 PM, Ali Saidi sa...@umich.edu wrote: Could you run m5 in gdb and give us a backtrace? That would probably identify the problem. What additional changes did you make? Ali On Mar 5, 2009, at 11:57 AM, Polina Dudnik wrote: Hi Ali, Would you mind sending me the console output you are getting for booting 2 processors, because I am getting the seg fault right now and I am trying to locate it. Here's what I get: warn: Ignoring write to SPARC ERROR regsiter warn: Ignoring write to SPARC ERROR regsiter warn: Don't know what interrupt to clear for console. warn: Ignoring write to SPARC ERROR regsiter warn: Ignoring write to SPARC ERROR regsiter Segmentation fault and on the console: SunOS Release 5.10 Version Generic_118822-23 64-bit Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. Ethernet address = 0:80:3:de:ad:3 mem = 262144K (0x1000) avail mem = 237879296 root nexus = Sun Fire T2000 pseudo0 at root pseudo0 is /pseudo scsi_vhci0 at root scsi_vhci0 is /scsi_vhci virtual-device: hsimd0 hsimd0 is /virtual-devi...@100/d...@0 root on /virtual-devi...@100/d...@0:a fstype ufs pseudo-device: dld0 dld0 is /pseudo/d...@0 cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz) cpu1: UltraSPARC-T1 (cpuid 1 clock 5 MHz) On Tue, Mar 3, 2009 at 11:35 PM, Ali Saidi sa...@umich.edu wrote: On Mar 3, 2009, at 9:48 PM, Polina wrote: Hi Ali, Thanks for your help. I hate to keep asking things, but there's little documentation. I appreciate you taking the time to respond to my emails. Oh, I see now. Would I follow the procedure outline in OpenSPARC readme files for creating checkpoints and copying stuff into the booted sparc? Not for creating a checkpoint, that needs to be done within M5, but the instructions for putting stuff on the disk image should be about the same. Mount the image on a solaris machine, copy files in there, done. Also, did you have any problems compiling things like hypervisor? I keep getting all kinds of errors, like ../../..//hypervisor-tools/bin/qas: ../../..//greatlakes/common/src/version.s, line 62: error: redefinition of symbol qversion ../../..//hypervisor-tools/bin/qas: ../../..//greatlakes/common/src/version.s, line 67: error: redefinition of symbol eqversion ../../..//hypervisor-tools/bin/qas: ../../..//greatlakes/common/src/version.s, line 69: error: redefinition of symbol printversion ../../..//hypervisor-tools/bin/qas: ../../..//greatlakes/common/src/version.s, line 78: warning: size of printversion redefined What could be causing them? You need to compile it on a Solaris machine. You don't really need to compile the hypervisor unless you want to modify it. The files you care about are in legion/src/config/niagara/*.conf and the associated make files in there. These too need to be compiled on a solaris machine. If you look at 1g2p.hdesc you'll see: CPU(0,guest0,0) CPU(4,guest0,1) I tried changing that 4 to 1 (e.g. CPU id 4 - 1) and it didn't convince the hypervisor that I was interested in CPU1 not 4. Perhaps there is another place that it is used or something else. Ali Thank you. Polina Ali Saidi wrote: T1 The hv and md description files need to match the configuration you're running. If you're only running 1 processor you need to change the hv and md files to the 1up configuration (as opposed to the 1g2p versions). Ali On Mar 3, 2009, at 9:10 PM, Polina wrote: Ali, Just to be sure, are you using T1 or T2 release of OpenSparc? Thanks. Polina Well, it's probably best to actually make 2 CPUs work and then go back and fix things for N CPUs. It should be possible to make the hypervisor description file (1g2p-hv.bin) understand that CPU 1 should be id 1 and not 4. However, my attempt at doing so didn't seem to work. The files required to build the hv.bin and md.bin files are available as part of the OpenSPARC Architecture toolkit that is available from Sun's website. The packets are generated by uncached writes to the IOB device registers that the hypervisor code does to get things going. Ali On Mar 2,
Re: [m5-dev] sparc_fs follow-up
I am doing it in m5. Polina On Thu, Mar 5, 2009 at 1:04 PM, Steve Reinhardt ste...@gmail.com wrote: 2009/3/5 Polina Dudnik pdud...@gmail.com: I am not sure why our code base would be different and by how much, but that could be why yours is running fine and mine segfaults. Hi Polina, If you're doing this in the gem5 repository then that is getting stale wrt the main m5 tree. It might be best if all you're doing is working on SPARC functionality to do that based on the m5 tree. I really want to have a do-over on the gem5 tree and make it such that Ruby vs. the classic M5 memory system is a compile-time option so that we don't have to have a permanent fork like we do now. Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] sparc_fs follow-up
My output looks like this: M5 compiled Mar 5 2009 13:51:37 M5 revision 632115b48346 5955 default qtip tip start_sparc_2cpu.diff qbase M5 started Mar 5 2009 14:03:22 M5 executing on zeep command line: ./build/SPARC_FS/m5.opt configs/example/fs.py -n 2 Global frequency set at 1 ticks per second info: No kernel set for full system simulation. Assuming you know what you're doing... Listening for t1000 connection on port 3456 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.t1000.htod: Real-time clock set to 1230768000 Listening for t1000 connection on port 3457 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7000 REAL SIMULATION info: Entering event queue @ 0. Starting simulation... hack: Processor 2 is virtual processor 4. Swizzle the numbers(this will only work for = 2 processors) hack: Processor 2 is virtual processor 4. Swizzle the numbers(this will only work for = 2 processors) info: Ignoring write to SPARC ERROR regsiter info: Ignoring write to SPARC ERROR regsiter warn: Don't know what interrupt to clear for console. For more information see: http://www.m5sim.org/warn/7fe1004f info: Ignoring write to SPARC ERROR regsiter info: Ignoring write to SPARC ERROR regsiter and the console output looks like: cpu cpu Sun Fire T2000, No Keyboard Copyright 2006 Sun Microsystems, Inc. All rights reserved. OpenBoot 4.23.0, 256 MB memory available, Serial #1122867. [saidi obp #30] Ethernet address 0:80:3:de:ad:3, Host ID: 80112233. Boot device: /virtual-devices/d...@0 File and args: -vV Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54. FCode UFS Reader 1.12 00/07/17 15:48:16. Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot Loading: /platform/sun4v/ufsboot device path '/virtual-devi...@100/d...@0:a' The boot filesystem is logging. The ufs log is empty and will not be used. standalone = `kernel/sparcv9/unix', args = `-v' Elf64 client Size: 0x76e40+0x1c872+0x3123a Bytes modpath: /platform/sun4v/kernel /kernel /usr/kernel module /platform/sun4v/kernel/sparcv9/unix: text at [0x100, 0x1076e3f] data at 0x180 module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0 module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0 module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0 module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300 SunOS Release 5.10 Version Generic_118822-23 64-bit Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. Ethernet address = 0:80:3:de:ad:3 mem = 262144K (0x1000) avail mem = 237879296 root nexus = Sun Fire T2000 pseudo0 at root pseudo0 is /pseudo scsi_vhci0 at root scsi_vhci0 is /scsi_vhci virtual-device: hsimd0 hsimd0 is /virtual-devi...@100/d...@0 root on /virtual-devi...@100/d...@0:a fstype ufs pseudo-device: dld0 dld0 is /pseudo/d...@0 cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz) cpu1: UltraSPARC-T1 (cpuid 1 clock 5 MHz) At this point there is no futher output. I imagine that one cpu is waiting for another one or something and whatever condition it's waiting for is not being reached. It is still interesting to know why it's crashing for you, since it might shed some light on the reason. The thing to do now is look through the solaris source to see what is going on right after the cpuX: ... lines are printed and look at an exec trace and try to debug the problem. Ali On Mar 5, 2009, at 2:30 PM, Polina Dudnik wrote: It is m5-stable. Maybe I should change to m5. I can do that. Also, are any of the binaries dependent on 1g2p-md.bin or 1g2p- hv.bin by any chance? Polina On Thu, Mar 5, 2009 at 1:24 PM, Steve Reinhardt ste...@gmail.com wrote: m5 or m5-stable? The contextId change is in the former but not the latter. 2009/3/5 Polina Dudnik pdud...@gmail.com: I am doing it in m5. Polina - Show quoted text - On Thu, Mar 5, 2009 at 1:04 PM, Steve Reinhardt ste...@gmail.com wrote: - Show quoted text - 2009/3/5 Polina Dudnik pdud...@gmail.com: I am not sure why our code base would be different and by how much, but that could be why yours is running fine and mine segfaults. Hi Polina, If you're doing this in the gem5 repository then that is getting stale wrt the main m5 tree. It might be best if all you're doing is working on SPARC functionality to do that based on the m5 tree. I really want to have a do-over on the gem5 tree and make it such that Ruby vs. the classic M5 memory system is a compile-time option so that we don't have to have a permanent fork like we do now. Steve ___ m5-dev mailing list m5-dev@m5sim.org
Re: [m5-dev] sparc_fs follow-up
Yes, I am trying to figure it out right now by running it withing gdb. It is pretty interesting that my output only differs from yours by one line which is segfault. It will be a little bit before I can install the most recent m5-dev because the scons was upgraded to 0.98 and we are still on 0.97 and I need to wait for the lab to upgrade scons. Polina On Thu, Mar 5, 2009 at 2:26 PM, Ali Saidi sa...@umich.edu wrote: My output looks like this: M5 compiled Mar 5 2009 13:51:37 M5 revision 632115b48346 5955 default qtip tip start_sparc_2cpu.diff qbase M5 started Mar 5 2009 14:03:22 M5 executing on zeep command line: ./build/SPARC_FS/m5.opt configs/example/fs.py -n 2 Global frequency set at 1 ticks per second info: No kernel set for full system simulation. Assuming you know what you're doing... Listening for t1000 connection on port 3456 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.t1000.htod: Real-time clock set to 1230768000 Listening for t1000 connection on port 3457 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7000 REAL SIMULATION info: Entering event queue @ 0. Starting simulation... hack: Processor 2 is virtual processor 4. Swizzle the numbers(this will only work for = 2 processors) hack: Processor 2 is virtual processor 4. Swizzle the numbers(this will only work for = 2 processors) info: Ignoring write to SPARC ERROR regsiter info: Ignoring write to SPARC ERROR regsiter warn: Don't know what interrupt to clear for console. For more information see: http://www.m5sim.org/warn/7fe1004f info: Ignoring write to SPARC ERROR regsiter info: Ignoring write to SPARC ERROR regsiter and the console output looks like: cpu cpu Sun Fire T2000, No Keyboard Copyright 2006 Sun Microsystems, Inc. All rights reserved. OpenBoot 4.23.0, 256 MB memory available, Serial #1122867. [saidi obp #30] Ethernet address 0:80:3:de:ad:3, Host ID: 80112233. Boot device: /virtual-devices/d...@0 File and args: -vV Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54. FCode UFS Reader 1.12 00/07/17 15:48:16. Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot Loading: /platform/sun4v/ufsboot device path '/virtual-devi...@100/d...@0:a' The boot filesystem is logging. The ufs log is empty and will not be used. standalone = `kernel/sparcv9/unix', args = `-v' Elf64 client Size: 0x76e40+0x1c872+0x3123a Bytes modpath: /platform/sun4v/kernel /kernel /usr/kernel module /platform/sun4v/kernel/sparcv9/unix: text at [0x100, 0x1076e3f] data at 0x180 module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0 module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0 module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0 module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300 SunOS Release 5.10 Version Generic_118822-23 64-bit Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. Ethernet address = 0:80:3:de:ad:3 mem = 262144K (0x1000) avail mem = 237879296 root nexus = Sun Fire T2000 pseudo0 at root pseudo0 is /pseudo scsi_vhci0 at root scsi_vhci0 is /scsi_vhci virtual-device: hsimd0 hsimd0 is /virtual-devi...@100/d...@0 root on /virtual-devi...@100/d...@0:a fstype ufs pseudo-device: dld0 dld0 is /pseudo/d...@0 cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz) cpu1: UltraSPARC-T1 (cpuid 1 clock 5 MHz) At this point there is no futher output. I imagine that one cpu is waiting for another one or something and whatever condition it's waiting for is not being reached. It is still interesting to know why it's crashing for you, since it might shed some light on the reason. The thing to do now is look through the solaris source to see what is going on right after the cpuX: ... lines are printed and look at an exec trace and try to debug the problem. Ali On Mar 5, 2009, at 2:30 PM, Polina Dudnik wrote: It is m5-stable. Maybe I should change to m5. I can do that. Also, are any of the binaries dependent on 1g2p-md.bin or 1g2p- hv.bin by any chance? Polina On Thu, Mar 5, 2009 at 1:24 PM, Steve Reinhardt ste...@gmail.com wrote: m5 or m5-stable? The contextId change is in the former but not the latter. 2009/3/5 Polina Dudnik pdud...@gmail.com: I am doing it in m5. Polina - Show quoted text - On Thu, Mar 5, 2009 at 1:04 PM, Steve Reinhardt ste...@gmail.com wrote: - Show quoted text - 2009/3/5 Polina Dudnik pdud...@gmail.com: I am not sure why our code base would be different and by how much, but that could be why yours is running fine and mine segfaults. Hi Polina, If you're doing this in the gem5 repository then that
Re: [m5-dev] sparc_fs follow-up
If you want to get going quickly, you can download the scons-local package and just stick it somewhere. Nate 2009/3/5 Polina Dudnik pdud...@gmail.com: Yes, I am trying to figure it out right now by running it withing gdb. It is pretty interesting that my output only differs from yours by one line which is segfault. It will be a little bit before I can install the most recent m5-dev because the scons was upgraded to 0.98 and we are still on 0.97 and I need to wait for the lab to upgrade scons. Polina On Thu, Mar 5, 2009 at 2:26 PM, Ali Saidi sa...@umich.edu wrote: My output looks like this: M5 compiled Mar 5 2009 13:51:37 M5 revision 632115b48346 5955 default qtip tip start_sparc_2cpu.diff qbase M5 started Mar 5 2009 14:03:22 M5 executing on zeep command line: ./build/SPARC_FS/m5.opt configs/example/fs.py -n 2 Global frequency set at 1 ticks per second info: No kernel set for full system simulation. Assuming you know what you're doing... Listening for t1000 connection on port 3456 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.t1000.htod: Real-time clock set to 1230768000 Listening for t1000 connection on port 3457 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7000 REAL SIMULATION info: Entering event queue @ 0. Starting simulation... hack: Processor 2 is virtual processor 4. Swizzle the numbers(this will only work for = 2 processors) hack: Processor 2 is virtual processor 4. Swizzle the numbers(this will only work for = 2 processors) info: Ignoring write to SPARC ERROR regsiter info: Ignoring write to SPARC ERROR regsiter warn: Don't know what interrupt to clear for console. For more information see: http://www.m5sim.org/warn/7fe1004f info: Ignoring write to SPARC ERROR regsiter info: Ignoring write to SPARC ERROR regsiter and the console output looks like: cpu cpu Sun Fire T2000, No Keyboard Copyright 2006 Sun Microsystems, Inc. All rights reserved. OpenBoot 4.23.0, 256 MB memory available, Serial #1122867. [saidi obp #30] Ethernet address 0:80:3:de:ad:3, Host ID: 80112233. Boot device: /virtual-devices/d...@0 File and args: -vV Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54. FCode UFS Reader 1.12 00/07/17 15:48:16. Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot Loading: /platform/sun4v/ufsboot device path '/virtual-devi...@100/d...@0:a' The boot filesystem is logging. The ufs log is empty and will not be used. standalone = `kernel/sparcv9/unix', args = `-v' Elf64 client Size: 0x76e40+0x1c872+0x3123a Bytes modpath: /platform/sun4v/kernel /kernel /usr/kernel module /platform/sun4v/kernel/sparcv9/unix: text at [0x100, 0x1076e3f] data at 0x180 module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0 module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0 module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0 module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300 SunOS Release 5.10 Version Generic_118822-23 64-bit Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. Ethernet address = 0:80:3:de:ad:3 mem = 262144K (0x1000) avail mem = 237879296 root nexus = Sun Fire T2000 pseudo0 at root pseudo0 is /pseudo scsi_vhci0 at root scsi_vhci0 is /scsi_vhci virtual-device: hsimd0 hsimd0 is /virtual-devi...@100/d...@0 root on /virtual-devi...@100/d...@0:a fstype ufs pseudo-device: dld0 dld0 is /pseudo/d...@0 cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz) cpu1: UltraSPARC-T1 (cpuid 1 clock 5 MHz) At this point there is no futher output. I imagine that one cpu is waiting for another one or something and whatever condition it's waiting for is not being reached. It is still interesting to know why it's crashing for you, since it might shed some light on the reason. The thing to do now is look through the solaris source to see what is going on right after the cpuX: ... lines are printed and look at an exec trace and try to debug the problem. Ali On Mar 5, 2009, at 2:30 PM, Polina Dudnik wrote: It is m5-stable. Maybe I should change to m5. I can do that. Also, are any of the binaries dependent on 1g2p-md.bin or 1g2p- hv.bin by any chance? Polina On Thu, Mar 5, 2009 at 1:24 PM, Steve Reinhardt ste...@gmail.com wrote: m5 or m5-stable? The contextId change is in the former but not the latter. 2009/3/5 Polina Dudnik pdud...@gmail.com: I am doing it in m5. Polina - Show quoted text - On Thu, Mar 5, 2009 at 1:04 PM, Steve Reinhardt ste...@gmail.com wrote: - Show quoted text - 2009/3/5 Polina Dudnik pdud...@gmail.com: I am not sure why our code base would be different and
Re: [m5-dev] sparc_fs follow-up
There's actually a bug in the CPU wakeup code which prevents any CPU that isn't activated and then suspended, like SPARCs APs which are suspended directly, from waking up on interrupts, etc. I have a partial fix which I've been using to work around the problem, but we need to come up with a full solution. I don't know if this is what the problem is, but it sounds like it could be. Gabe Quoting Ali Saidi sa...@umich.edu: My output looks like this: M5 compiled Mar 5 2009 13:51:37 M5 revision 632115b48346 5955 default qtip tip start_sparc_2cpu.diff qbase M5 started Mar 5 2009 14:03:22 M5 executing on zeep command line: ./build/SPARC_FS/m5.opt configs/example/fs.py -n 2 Global frequency set at 1 ticks per second info: No kernel set for full system simulation. Assuming you know what you're doing... Listening for t1000 connection on port 3456 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.t1000.htod: Real-time clock set to 1230768000 Listening for t1000 connection on port 3457 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7000 REAL SIMULATION info: Entering event queue @ 0. Starting simulation... hack: Processor 2 is virtual processor 4. Swizzle the numbers(this will only work for = 2 processors) hack: Processor 2 is virtual processor 4. Swizzle the numbers(this will only work for = 2 processors) info: Ignoring write to SPARC ERROR regsiter info: Ignoring write to SPARC ERROR regsiter warn: Don't know what interrupt to clear for console. For more information see: http://www.m5sim.org/warn/7fe1004f info: Ignoring write to SPARC ERROR regsiter info: Ignoring write to SPARC ERROR regsiter and the console output looks like: cpu cpu Sun Fire T2000, No Keyboard Copyright 2006 Sun Microsystems, Inc. All rights reserved. OpenBoot 4.23.0, 256 MB memory available, Serial #1122867. [saidi obp #30] Ethernet address 0:80:3:de:ad:3, Host ID: 80112233. Boot device: /virtual-devices/d...@0 File and args: -vV Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54. FCode UFS Reader 1.12 00/07/17 15:48:16. Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot Loading: /platform/sun4v/ufsboot device path '/virtual-devi...@100/d...@0:a' The boot filesystem is logging. The ufs log is empty and will not be used. standalone = `kernel/sparcv9/unix', args = `-v' Elf64 client Size: 0x76e40+0x1c872+0x3123a Bytes modpath: /platform/sun4v/kernel /kernel /usr/kernel module /platform/sun4v/kernel/sparcv9/unix: text at [0x100, 0x1076e3f] data at 0x180 module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0 module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0 module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0 module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300 SunOS Release 5.10 Version Generic_118822-23 64-bit Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. Ethernet address = 0:80:3:de:ad:3 mem = 262144K (0x1000) avail mem = 237879296 root nexus = Sun Fire T2000 pseudo0 at root pseudo0 is /pseudo scsi_vhci0 at root scsi_vhci0 is /scsi_vhci virtual-device: hsimd0 hsimd0 is /virtual-devi...@100/d...@0 root on /virtual-devi...@100/d...@0:a fstype ufs pseudo-device: dld0 dld0 is /pseudo/d...@0 cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz) cpu1: UltraSPARC-T1 (cpuid 1 clock 5 MHz) At this point there is no futher output. I imagine that one cpu is waiting for another one or something and whatever condition it's waiting for is not being reached. It is still interesting to know why it's crashing for you, since it might shed some light on the reason. The thing to do now is look through the solaris source to see what is going on right after the cpuX: ... lines are printed and look at an exec trace and try to debug the problem. Ali On Mar 5, 2009, at 2:30 PM, Polina Dudnik wrote: It is m5-stable. Maybe I should change to m5. I can do that. Also, are any of the binaries dependent on 1g2p-md.bin or 1g2p- hv.bin by any chance? Polina On Thu, Mar 5, 2009 at 1:24 PM, Steve Reinhardt ste...@gmail.com wrote: m5 or m5-stable? The contextId change is in the former but not the latter. 2009/3/5 Polina Dudnik pdud...@gmail.com: I am doing it in m5. Polina - Show quoted text - On Thu, Mar 5, 2009 at 1:04 PM, Steve Reinhardt ste...@gmail.com wrote: - Show quoted text - 2009/3/5 Polina Dudnik pdud...@gmail.com: I am not sure why our code base would be different and by how much, but that could be why yours is running fine and mine segfaults. Hi Polina, If you're doing this in the gem5 repository then that is getting stale
Re: [m5-dev] sparc_fs follow-up
On Thu, Mar 5, 2009 at 3:38 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: There's actually a bug in the CPU wakeup code which prevents any CPU that isn't activated and then suspended, like SPARCs APs which are suspended directly, from waking up on interrupts, etc. I have a partial fix which I've been using to work around the problem, but we need to come up with a full solution. I don't know if this is what the problem is, but it sounds like it could be. Gabe Are you talking about the seg fault in m5-stable that I get? Or the CPU ids? Polina Quoting Ali Saidi sa...@umich.edu: My output looks like this: M5 compiled Mar 5 2009 13:51:37 M5 revision 632115b48346 5955 default qtip tip start_sparc_2cpu.diff qbase M5 started Mar 5 2009 14:03:22 M5 executing on zeep command line: ./build/SPARC_FS/m5.opt configs/example/fs.py -n 2 Global frequency set at 1 ticks per second info: No kernel set for full system simulation. Assuming you know what you're doing... Listening for t1000 connection on port 3456 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.t1000.htod: Real-time clock set to 1230768000 Listening for t1000 connection on port 3457 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7000 REAL SIMULATION info: Entering event queue @ 0. Starting simulation... hack: Processor 2 is virtual processor 4. Swizzle the numbers(this will only work for = 2 processors) hack: Processor 2 is virtual processor 4. Swizzle the numbers(this will only work for = 2 processors) info: Ignoring write to SPARC ERROR regsiter info: Ignoring write to SPARC ERROR regsiter warn: Don't know what interrupt to clear for console. For more information see: http://www.m5sim.org/warn/7fe1004f info: Ignoring write to SPARC ERROR regsiter info: Ignoring write to SPARC ERROR regsiter and the console output looks like: cpu cpu Sun Fire T2000, No Keyboard Copyright 2006 Sun Microsystems, Inc. All rights reserved. OpenBoot 4.23.0, 256 MB memory available, Serial #1122867. [saidi obp #30] Ethernet address 0:80:3:de:ad:3, Host ID: 80112233. Boot device: /virtual-devices/d...@0 File and args: -vV Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54. FCode UFS Reader 1.12 00/07/17 15:48:16. Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot Loading: /platform/sun4v/ufsboot device path '/virtual-devi...@100/d...@0:a' The boot filesystem is logging. The ufs log is empty and will not be used. standalone = `kernel/sparcv9/unix', args = `-v' Elf64 client Size: 0x76e40+0x1c872+0x3123a Bytes modpath: /platform/sun4v/kernel /kernel /usr/kernel module /platform/sun4v/kernel/sparcv9/unix: text at [0x100, 0x1076e3f] data at 0x180 module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0 module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0 module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0 module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300 SunOS Release 5.10 Version Generic_118822-23 64-bit Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. Ethernet address = 0:80:3:de:ad:3 mem = 262144K (0x1000) avail mem = 237879296 root nexus = Sun Fire T2000 pseudo0 at root pseudo0 is /pseudo scsi_vhci0 at root scsi_vhci0 is /scsi_vhci virtual-device: hsimd0 hsimd0 is /virtual-devi...@100/d...@0 root on /virtual-devi...@100/d...@0:a fstype ufs pseudo-device: dld0 dld0 is /pseudo/d...@0 cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz) cpu1: UltraSPARC-T1 (cpuid 1 clock 5 MHz) At this point there is no futher output. I imagine that one cpu is waiting for another one or something and whatever condition it's waiting for is not being reached. It is still interesting to know why it's crashing for you, since it might shed some light on the reason. The thing to do now is look through the solaris source to see what is going on right after the cpuX: ... lines are printed and look at an exec trace and try to debug the problem. Ali On Mar 5, 2009, at 2:30 PM, Polina Dudnik wrote: It is m5-stable. Maybe I should change to m5. I can do that. Also, are any of the binaries dependent on 1g2p-md.bin or 1g2p- hv.bin by any chance? Polina On Thu, Mar 5, 2009 at 1:24 PM, Steve Reinhardt ste...@gmail.com wrote: m5 or m5-stable? The contextId change is in the former but not the latter. 2009/3/5 Polina Dudnik pdud...@gmail.com: I am doing it in m5. Polina - Show quoted text - On Thu, Mar 5, 2009 at 1:04 PM, Steve Reinhardt ste...@gmail.com wrote: -
[m5-dev] changeset in m5: SCons: Fix bug with .hg dir not existing.
changeset 886da6fa6d4a in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=886da6fa6d4a description: SCons: Fix bug with .hg dir not existing. diffstat: 1 file changed, 2 insertions(+), 3 deletions(-) SConstruct |5 ++--- diffs (30 lines): diff -r 4ed2100efa84 -r 886da6fa6d4a SConstruct --- a/SConstructWed Mar 04 22:37:45 2009 -0500 +++ b/SConstructThu Mar 05 17:05:06 2009 -0500 @@ -211,17 +211,15 @@ run the style hook. It is important. +hg_info = Unknown if hgdir.exists(): # 1) Grab repository revision if we know it. cmd = hg id -n -i -t -b try: hg_info = read_command(cmd, cwd=env.root.abspath).strip() except OSError: -hg_info = Unknown print mercurial_bin_not_found -env['HG_INFO'] = hg_info - # 2) Ensure that the style hook is in place. try: ui = None @@ -240,6 +238,7 @@ sys.exit(1) else: print .hg directory not found +env['HG_INFO'] = hg_info ### # ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] FS benchmark description
There are multiple benchmarks that can be run in FS mode (like ValStream). Where can I find a precise description of what those benchmarks do exactly? The reason I ask is because I would like to verify their behavior on SPARC_FS. I don't know if much has been written down other than in papers that people have written using M5. (I'm not sure what ValStream even is.) Also a lot of those benchmarks use tsunami, so they are inherently only benchmarking Alpha. Are there equivalents for SPARC? I'm not sure why you think any of the benchmarks we've used are inherently only for alpha. If you're talking about how the binaries are compiled for alpha, that's true, but most things can be compiled for whichever architecture you want. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] FS benchmark description
On Thu, Mar 5, 2009 at 4:50 PM, nathan binkert n...@binkert.org wrote: There are multiple benchmarks that can be run in FS mode (like ValStream). Where can I find a precise description of what those benchmarks do exactly? The reason I ask is because I would like to verify their behavior on SPARC_FS. I don't know if much has been written down other than in papers that people have written using M5. (I'm not sure what ValStream even is.) I see. OK. Also a lot of those benchmarks use tsunami, so they are inherently only benchmarking Alpha. Are there equivalents for SPARC? I'm not sure why you think any of the benchmarks we've used are inherently only for alpha. If you're talking about how the binaries are compiled for alpha, that's true, but most things can be compiled for whichever architecture you want. I guess I was misguided by seeing tsunami referenced in the context of alpha, and I guess it is just that the scripts are set up for alpha so they are asking for tsunami. My understanding is that benchmark binaries are located on the disk that gets booted by ALPHA_FS and SPARC_FS. So, all these benchmark configuration files have a path to a binary which probably points to binaries on a booted disk image. I guess my question is, regarding the benchmarks provided for the FS mode, can I expect to find any of those binaries in the SPARC_FS disk image? Where can I find the source code for the benchmarks so I can figure out what they do and recompile them? Thank you. Polina Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] sparc_fs follow-up
Quoting Polina Dudnik pdud...@gmail.com: On Thu, Mar 5, 2009 at 3:38 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: There's actually a bug in the CPU wakeup code which prevents any CPU that isn't activated and then suspended, like SPARCs APs which are suspended directly, from waking up on interrupts, etc. I have a partial fix which I've been using to work around the problem, but we need to come up with a full solution. I don't know if this is what the problem is, but it sounds like it could be. Gabe Are you talking about the seg fault in m5-stable that I get? Or the CPU ids? Polina I was talking about the hang Ali described. If the BP is waiting for an AP to tell it it's alive and the AP never wakes up, the system will likely hang. I ran into that problem in X86_FS. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] sparc_fs follow-up
Oh, I see. Do you think you can distribute the partial patch you have? Thank you. Polina On Thu, Mar 5, 2009 at 4:48 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: Quoting Polina Dudnik pdud...@gmail.com: On Thu, Mar 5, 2009 at 3:38 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: There's actually a bug in the CPU wakeup code which prevents any CPU that isn't activated and then suspended, like SPARCs APs which are suspended directly, from waking up on interrupts, etc. I have a partial fix which I've been using to work around the problem, but we need to come up with a full solution. I don't know if this is what the problem is, but it sounds like it could be. Gabe Are you talking about the seg fault in m5-stable that I get? Or the CPU ids? Polina I was talking about the hang Ali described. If the BP is waiting for an AP to tell it it's alive and the AP never wakes up, the system will likely hang. I ran into that problem in X86_FS. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] sparc_fs follow-up
The change is simple enough that I'll just describe it. This deals solely with the simple CPU, so if your trying to use O3, for example, it won't help you directly. The code here: http://repo.m5sim.org/m5/file/886da6fa6d4a/src/cpu/simple/base.cc#l307 should return if the thread is suspended -or- unallocated. After you change that, I think you'll also run into an assert in the CPU. I just got rid of the assert and haven't had any problems, but that might not be the right thing to do. Gabe Quoting Polina Dudnik pdud...@gmail.com: Oh, I see. Do you think you can distribute the partial patch you have? Thank you. Polina On Thu, Mar 5, 2009 at 4:48 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: Quoting Polina Dudnik pdud...@gmail.com: On Thu, Mar 5, 2009 at 3:38 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: There's actually a bug in the CPU wakeup code which prevents any CPU that isn't activated and then suspended, like SPARCs APs which are suspended directly, from waking up on interrupts, etc. I have a partial fix which I've been using to work around the problem, but we need to come up with a full solution. I don't know if this is what the problem is, but it sounds like it could be. Gabe Are you talking about the seg fault in m5-stable that I get? Or the CPU ids? Polina I was talking about the hang Ali described. If the BP is waiting for an AP to tell it it's alive and the AP never wakes up, the system will likely hang. I ran into that problem in X86_FS. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] sparc_fs follow-up
OK. Thanks. I will try that. On Thu, Mar 5, 2009 at 5:10 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: The change is simple enough that I'll just describe it. This deals solely with the simple CPU, so if your trying to use O3, for example, it won't help you directly. The code here: http://repo.m5sim.org/m5/file/886da6fa6d4a/src/cpu/simple/base.cc#l307 should return if the thread is suspended -or- unallocated. After you change that, I think you'll also run into an assert in the CPU. I just got rid of the assert and haven't had any problems, but that might not be the right thing to do. Gabe Quoting Polina Dudnik pdud...@gmail.com: Oh, I see. Do you think you can distribute the partial patch you have? Thank you. Polina On Thu, Mar 5, 2009 at 4:48 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: Quoting Polina Dudnik pdud...@gmail.com: On Thu, Mar 5, 2009 at 3:38 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: There's actually a bug in the CPU wakeup code which prevents any CPU that isn't activated and then suspended, like SPARCs APs which are suspended directly, from waking up on interrupts, etc. I have a partial fix which I've been using to work around the problem, but we need to come up with a full solution. I don't know if this is what the problem is, but it sounds like it could be. Gabe Are you talking about the seg fault in m5-stable that I get? Or the CPU ids? Polina I was talking about the hang Ali described. If the BP is waiting for an AP to tell it it's alive and the AP never wakes up, the system will likely hang. I ran into that problem in X86_FS. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] sparc_fs follow-up
I know why it wouldn't compile now. For some reason it just wasn't happy with SUNW,Sun-Fire-880 but once I moved to SUNW,Sun-Fire-T200 it worked like a charm! On Tue, Mar 3, 2009 at 11:35 PM, Ali Saidi sa...@umich.edu wrote: SUNW,Sun-Fire-T200 On Mar 3, 2009, at 9:48 PM, Polina wrote: Hi Ali, Thanks for your help. I hate to keep asking things, but there's little documentation. I appreciate you taking the time to respond to my emails. Oh, I see now. Would I follow the procedure outline in OpenSPARC readme files for creating checkpoints and copying stuff into the booted sparc? Not for creating a checkpoint, that needs to be done within M5, but the instructions for putting stuff on the disk image should be about the same. Mount the image on a solaris machine, copy files in there, done. Also, did you have any problems compiling things like hypervisor? I keep getting all kinds of errors, like ../../..//hypervisor-tools/bin/qas: ../../..//greatlakes/common/src/version.s, line 62: error: redefinition of symbol qversion ../../..//hypervisor-tools/bin/qas: ../../..//greatlakes/common/src/version.s, line 67: error: redefinition of symbol eqversion ../../..//hypervisor-tools/bin/qas: ../../..//greatlakes/common/src/version.s, line 69: error: redefinition of symbol printversion ../../..//hypervisor-tools/bin/qas: ../../..//greatlakes/common/src/version.s, line 78: warning: size of printversion redefined What could be causing them? You need to compile it on a Solaris machine. You don't really need to compile the hypervisor unless you want to modify it. The files you care about are in legion/src/config/niagara/*.conf and the associated make files in there. These too need to be compiled on a solaris machine. If you look at 1g2p.hdesc you'll see: CPU(0,guest0,0) CPU(4,guest0,1) I tried changing that 4 to 1 (e.g. CPU id 4 - 1) and it didn't convince the hypervisor that I was interested in CPU1 not 4. Perhaps there is another place that it is used or something else. Ali Thank you. Polina Ali Saidi wrote: T1 The hv and md description files need to match the configuration you're running. If you're only running 1 processor you need to change the hv and md files to the 1up configuration (as opposed to the 1g2p versions). Ali On Mar 3, 2009, at 9:10 PM, Polina wrote: Ali, Just to be sure, are you using T1 or T2 release of OpenSparc? Thanks. Polina Well, it's probably best to actually make 2 CPUs work and then go back and fix things for N CPUs. It should be possible to make the hypervisor description file (1g2p-hv.bin) understand that CPU 1 should be id 1 and not 4. However, my attempt at doing so didn't seem to work. The files required to build the hv.bin and md.bin files are available as part of the OpenSPARC Architecture toolkit that is available from Sun's website. The packets are generated by uncached writes to the IOB device registers that the hypervisor code does to get things going. Ali On Mar 2, 2009, at 5:29 PM, Polina Dudnik wrote: Never mind, I started the console and got ERROR: 1 CPUs in PD did not start without the hack. So, you are right, there is something wrong with the cpu numbers. But I want to fix it for arbitrary numCpus. SO, to do that I want to find a place where the requests generate their data. So, the place where bits(12, 8) get generated. So, I guess my question is: where are the packets generated? Polina On Mon, Mar 2, 2009 at 3:26 PM, Polina Dudnik pdud...@gmail.com wrote: Hi Ali, Why do you say: Additionally, I had to put two hacks in to swizzle the CPU id numbers. For whatever reason the hypervisor insists that the second CPU should be id 4 while m5 would like it to be id 1. I tried changing the hypervisor description file and changing cpu4 to cpu1, however that didn't seem to change the id. What makes you think that hypervisor assigns #4 to processor #1? I removed this hack and everything works fine. Polina ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] namespace usage
Just a note: you should NEVER have a 'using namespace' declaration at the top level of a normal header file. This forces all the names in that namespace into the global namespace of any source file including that header file, which basically completely defeats the point of namespaces. It is OK to use using declarations at the top level of a source (.cc) file since the effect is entirely local to that .cc file. It's also OK to use them in _impl.hh files, since for practical purposes these are source (not header) files despite their extension. I just ran into a case where Ruby doesn't compile with MIPS because arch/mips/isa_traits.hh has using namespace MipsISA; at the end of it, so all of the MipsISA registers are globals, and there's a Debug in the MiscRegTags enum that conflicts with a Ruby class name. I just added a note to this effect at http://m5sim.org/wiki/index.php/Coding_Style#File_structure_and_modularity. Fortunately the fixes weren't too bad; I'll be pushing them soon. Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: Get rid of 'using namespace' declarations in he...
changeset 3ca926101a5c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3ca926101a5c
description:
Get rid of 'using namespace' declarations in headers.
diffstat:
8 files changed, 4 insertions(+), 19 deletions(-)
src/arch/alpha/linux/system.hh |5 +
src/arch/mips/bare_iron/system.hh |2 --
src/arch/mips/isa_traits.hh |2 --
src/arch/mips/linux/linux.hh|3 ---
src/arch/mips/linux/system.hh |5 +
src/arch/mips/mt.hh |3 +--
src/arch/mips/regfile/misc_regfile.cc |1 +
src/cpu/inorder/resources/fetch_seq_unit.hh |2 --
diffs (122 lines):
diff -r 886da6fa6d4a -r 3ca926101a5c src/arch/alpha/linux/system.hh
--- a/src/arch/alpha/linux/system.hhThu Mar 05 17:05:06 2009 -0500
+++ b/src/arch/alpha/linux/system.hhThu Mar 05 17:15:31 2009 -0800
@@ -43,9 +43,6 @@
#include kern/linux/events.hh
#include params/LinuxAlphaSystem.hh
-using namespace AlphaISA;
-using namespace Linux;
-
/**
* This class contains linux specific system code (Loading, Events).
* It points to objects that are the system binaries to load and patches them
@@ -109,7 +106,7 @@
* PC based event to skip the dprink() call and emulate its
* functionality
*/
-DebugPrintkEvent *debugPrintkEvent;
+Linux::DebugPrintkEvent *debugPrintkEvent;
/**
* Skip calculate_delay_loop() rather than waiting for this to be
diff -r 886da6fa6d4a -r 3ca926101a5c src/arch/mips/bare_iron/system.hh
--- a/src/arch/mips/bare_iron/system.hh Thu Mar 05 17:05:06 2009 -0500
+++ b/src/arch/mips/bare_iron/system.hh Thu Mar 05 17:15:31 2009 -0800
@@ -39,8 +39,6 @@
#include arch/mips/system.hh
#include params/BareIronMipsSystem.hh
-using namespace MipsISA;
-
/**
* This class contains linux specific system code (Loading, Events).
* It points to objects that are the system binaries to load and patches them
diff -r 886da6fa6d4a -r 3ca926101a5c src/arch/mips/isa_traits.hh
--- a/src/arch/mips/isa_traits.hh Thu Mar 05 17:05:06 2009 -0500
+++ b/src/arch/mips/isa_traits.hh Thu Mar 05 17:15:31 2009 -0800
@@ -381,6 +381,4 @@
};
-using namespace MipsISA;
-
#endif // __ARCH_MIPS_ISA_TRAITS_HH__
diff -r 886da6fa6d4a -r 3ca926101a5c src/arch/mips/linux/linux.hh
--- a/src/arch/mips/linux/linux.hh Thu Mar 05 17:05:06 2009 -0500
+++ b/src/arch/mips/linux/linux.hh Thu Mar 05 17:15:31 2009 -0800
@@ -32,9 +32,6 @@
#define __ARCH_MIPS_LINUX_LINUX_HH__
#include kern/linux/linux.hh
-#include string
-
-using std::string;
class MipsLinux : public Linux
{
diff -r 886da6fa6d4a -r 3ca926101a5c src/arch/mips/linux/system.hh
--- a/src/arch/mips/linux/system.hh Thu Mar 05 17:05:06 2009 -0500
+++ b/src/arch/mips/linux/system.hh Thu Mar 05 17:15:31 2009 -0800
@@ -43,9 +43,6 @@
#include kern/linux/events.hh
#include params/LinuxMipsSystem.hh
-using namespace MipsISA;
-using namespace Linux;
-
/**
* This class contains linux specific system code (Loading, Events).
* It points to objects that are the system binaries to load and patches them
@@ -112,7 +109,7 @@
* PC based event to skip the dprink() call and emulate its
* functionality
*/
-DebugPrintkEvent *debugPrintkEvent;
+Linux::DebugPrintkEvent *debugPrintkEvent;
/**
* Skip calculate_delay_loop() rather than waiting for this to be
diff -r 886da6fa6d4a -r 3ca926101a5c src/arch/mips/mt.hh
--- a/src/arch/mips/mt.hh Thu Mar 05 17:05:06 2009 -0500
+++ b/src/arch/mips/mt.hh Thu Mar 05 17:15:31 2009 -0800
@@ -45,7 +45,6 @@
#include base/misc.hh
#include iostream
-using namespace std;
namespace MipsISA
{
@@ -164,7 +163,7 @@
success = 1;
}
} else {
-std::cerr Bad VPEs endl;
+std::cerr Bad VPEs std::endl;
}
}
diff -r 886da6fa6d4a -r 3ca926101a5c src/arch/mips/regfile/misc_regfile.cc
--- a/src/arch/mips/regfile/misc_regfile.cc Thu Mar 05 17:05:06 2009 -0500
+++ b/src/arch/mips/regfile/misc_regfile.cc Thu Mar 05 17:15:31 2009 -0800
@@ -43,6 +43,7 @@
//#include params/DerivO3CPU.hh
using namespace std;
+using namespace MipsISA;
std::string MiscRegFile::miscRegNames[NumMiscRegs] =
{
diff -r 886da6fa6d4a -r 3ca926101a5c src/cpu/inorder/resources/fetch_seq_unit.hh
--- a/src/cpu/inorder/resources/fetch_seq_unit.hh Thu Mar 05 17:05:06
2009 -0500
+++ b/src/cpu/inorder/resources/fetch_seq_unit.hh Thu Mar 05 17:15:31
2009 -0800
@@ -41,8 +41,6 @@
#include cpu/inorder/pipeline_traits.hh
#include cpu/inorder/cpu.hh
-using namespace ThePipeline;
-
class FetchSeqUnit : public Resource {
public:
typedef ThePipeline::DynInstPtr DynInstPtr;
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Re: [m5-dev] locked memory accesses
Quoting Steve Reinhardt ste...@gmail.com: On Wed, Mar 4, 2009 at 7:03 AM, Steve Reinhardt ste...@gmail.com wrote: I think there are two possible solutions: 1. Add a retry response code for atomic requests (along the lines of the error codes we alrady have in packet.hh) and then make sure that all the places where we issue atomic requests can deal with them appropriately. Oddly enough it's reminiscent of the LL/SC solution, though this is different since it only applies in atomic mode. 2. Force any cpu or device that wants to do locked accesses in atomic mode to do both the lock and unlock accesses back-to-back within the same event (e.g., in the same call to tick()). Neither of these sound particularly attractive. I like #2 better [...] Another advantage of #2 is that atomic-mode atomicity comes for free without touching the memory system at all. This is nice since it gives you a baseline that will work on any memory system (e.g., Ruby). There's also some possibility that we could avoid implementing timing-mode locking in main memory with this approach, by making the reasonable restriction that if you want to run in timing mode then you have to use caches. That may not hold if we have to deal with locked uncached accesses... I know these exist in real life, but I'm hoping that that's one of the features we can avoid by only running modern 64-bit software. Gabe, do you know off hand if there are locked uncached accesses in any of the code you've run so far? Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev I haven't reached a conclusion on what to do, but I have a few thoughts. First, I don't know if we'd be able to use #2 to get away with not implementing locking in the main memory for timing accesses. It would be impossible to do a read and write of a location in the same event because you'd have to wait around for each to complete. You'd either have to force all other accesses to wait around which might be a big performance hit. Also things might get really sticky with speculative accesses, although I think that may be true in general. I like the idea of having lock and unlock flags, although I think it would be a good idea to not allow intervening operations even from the same source. With that restriction, locks could set up a condition where you'd only allow an access to happen if it was an unlock. If everything obeyed the rule of a lock and then an unlock that would guarantee atomicity and has the nice property that you don't have to keep track of -who- the access was originally from, just where the access was to. It may be next to impossible to actually know who has a lock if you have, for instance, a shared cache intervening. You could lock the address all the way up though, I suppose. All of the accesses I mentioned before and all of the CPU maintained data structure updates can happen with a single load-op-store, although I could believe there's some other ISA that needs something more elaborate. I have never directly seen an uncached, locked access, but I've been completely ignoring locked accesses in general up to now so I wouldn't consider that very authoritative. I'd be pretty surprised (but not shocked) if something somewhere used them. As far as how to make atomic mode atomic (which -is- weird), I don't really like either of the options you mentioned either. The first one seems more naturally analogous to timing mode, but then why do we need atomic mode? The second one limits the effects of supporting this sort of instruction/operation, but it would probably really complicate the CPU and I'd bet have a lot of unintended consequences. I've been thinking about this in the background and I haven't been able to come up with a better idea though. I'll keep trying. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] locked memory accesses
On Thu, Mar 5, 2009 at 6:33 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: Quoting Steve Reinhardt ste...@gmail.com: On Wed, Mar 4, 2009 at 7:03 AM, Steve Reinhardt ste...@gmail.com wrote: I think there are two possible solutions: 1. Add a retry response code for atomic requests (along the lines of the error codes we alrady have in packet.hh) and then make sure that all the places where we issue atomic requests can deal with them appropriately. Oddly enough it's reminiscent of the LL/SC solution, though this is different since it only applies in atomic mode. 2. Force any cpu or device that wants to do locked accesses in atomic mode to do both the lock and unlock accesses back-to-back within the same event (e.g., in the same call to tick()). Neither of these sound particularly attractive. I like #2 better [...] Another advantage of #2 is that atomic-mode atomicity comes for free without touching the memory system at all. This is nice since it gives you a baseline that will work on any memory system (e.g., Ruby). There's also some possibility that we could avoid implementing timing-mode locking in main memory with this approach, by making the reasonable restriction that if you want to run in timing mode then you have to use caches. That may not hold if we have to deal with locked uncached accesses... I know these exist in real life, but I'm hoping that that's one of the features we can avoid by only running modern 64-bit software. Gabe, do you know off hand if there are locked uncached accesses in any of the code you've run so far? Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev I haven't reached a conclusion on what to do, but I have a few thoughts. First, I don't know if we'd be able to use #2 to get away with not implementing locking in the main memory for timing accesses. It would be impossible to do a read and write of a location in the same event because you'd have to wait around for each to complete. You'd either have to force all other accesses to wait around which might be a big performance hit. Also things might get really sticky with speculative accesses, although I think that may be true in general. Yea, you're right, but that wasn't my point... what I was trying to say was that if you (1) use option #2 to make atomicity just work in atomic mode from the memory system's point of view and (2) require the use of caches in timing mode so that you can rely on the cache coherence protocol to handle atomicity in timing mode (which probably isn't that hard, since you already have mechanisms for deferring invalidations), then the main memory object would never have to worry about implementing atomicity. (In contrast to the current situation, where main memory has its own independent implementation of LL/SC support just to deal with cacheless configs.) I like the idea of having lock and unlock flags, although I think it would be a good idea to not allow intervening operations even from the same source. With that restriction, locks could set up a condition where you'd only allow an access to happen if it was an unlock. If everything obeyed the rule of a lock and then an unlock that would guarantee atomicity and has the nice property that you don't have to keep track of -who- the access was originally from, just where the access was to. It may be next to impossible to actually know who has a lock if you have, for instance, a shared cache intervening. Yes, that's exactly what I was thinking already. All of the accesses I mentioned before and all of the CPU maintained data structure updates can happen with a single load-op-store, although I could believe there's some other ISA that needs something more elaborate. I'm not sure that it matters, as long as the CPU doesn't do any intervening unlocked memory accesses to the same block. As far as how to make atomic mode atomic (which -is- weird), I don't really like either of the options you mentioned either. The first one seems more naturally analogous to timing mode, but then why do we need atomic mode? The second one limits the effects of supporting this sort of instruction/operation, but it would probably really complicate the CPU and I'd bet have a lot of unintended consequences. I've been thinking about this in the background and I haven't been able to come up with a better idea though. I'll keep trying. What if for AtomicSimpleCPU we execute a macroinstruction on each tick instead of a microop? We're not really caring that much about timing anyway, and all of the other CPU models only work in timing mode so they won't be affected. The only place where this gets really ridiculous is for REP prefixes, but if it's not too hard we could only execute one iteration of a REP instead of the whole macroinstruction in just that case. Steve ___ m5-dev
[m5-dev] changeset in m5: serialize: Allow floats and doubles to be seria...
changeset 9c04119e93af in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=9c04119e93af description: serialize: Allow floats and doubles to be serialized diffstat: 1 file changed, 2 insertions(+) src/sim/serialize.cc |2 ++ diffs (12 lines): diff -r 3ca926101a5c -r 9c04119e93af src/sim/serialize.cc --- a/src/sim/serialize.cc Thu Mar 05 17:15:31 2009 -0800 +++ b/src/sim/serialize.cc Thu Mar 05 19:09:53 2009 -0800 @@ -351,6 +351,8 @@ INSTANTIATE_PARAM_TEMPLATES(signed long long) INSTANTIATE_PARAM_TEMPLATES(unsigned long long) INSTANTIATE_PARAM_TEMPLATES(bool) +INSTANTIATE_PARAM_TEMPLATES(float) +INSTANTIATE_PARAM_TEMPLATES(double) INSTANTIATE_PARAM_TEMPLATES(string) ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: stats: miscellaneous cleanup
changeset 71e56052768f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=71e56052768f
description:
stats: miscellaneous cleanup
diffstat:
1 file changed, 7 insertions(+), 9 deletions(-)
src/base/statistics.hh | 16 +++-
diffs (82 lines):
diff -r 9c04119e93af -r 71e56052768f src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -468,7 +468,7 @@
/**
* Set the precision and marks this stat to print at the end of simulation.
- * @param p The new precision
+ * @param _precision The new precision
* @return A reference to this stat.
*/
Parent
@@ -728,7 +728,7 @@
void
reset(Info *info)
{
-total = 0;
+total = 0.0;
last = curTick;
}
@@ -1253,7 +1253,7 @@
Result
total() const
{
-Result total = 0;
+Result total = 0.0;
for (off_type i = 0; i size(); ++i)
total += data(i)-result();
return total;
@@ -1471,7 +1471,6 @@
* Add a value to the distribution for the given number of times.
* @param val The value to add.
* @param number The number of times to add the value.
- * @param params The paramters of the distribution.
*/
void
sample(Counter val, int number)
@@ -1595,7 +1594,6 @@
* values seen by the given number.
* @param val The value to add.
* @param number The number of times to add the value.
- * @param p The parameters of this stat.
*/
void
sample(Counter val, int number)
@@ -1973,7 +1971,7 @@
Result
VectorDistBaseStorage::total(off_type index) const
{
-Result total = 0;
+Result total = 0.0;
for (off_type i = 0; i x_size(); ++i)
total += data(i)-result();
}
@@ -2215,7 +2213,7 @@
total() const
{
const VResult vec = this-result();
-Result total = 0;
+Result total = 0.0;
for (off_type i = 0; i size(); i++)
total += vec[i];
return total;
@@ -2277,7 +2275,7 @@
total() const
{
const VResult vec = this-result();
-Result total = 0;
+Result total = 0.0;
for (off_type i = 0; i size(); i++)
total += vec[i];
return total;
@@ -2853,7 +2851,7 @@
* Return the node pointer.
* @return the node pointer.
*/
-operator NodePtr() { return node;}
+operator NodePtr() { return node; }
public:
/**
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[m5-dev] changeset in m5: stats: get rid of meaningless uses of virtual
changeset 19131d568007 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=19131d568007
description:
stats: get rid of meaningless uses of virtual
diffstat:
1 file changed, 79 insertions(+), 79 deletions(-)
src/base/statistics.hh | 158
diffs (truncated from 391 to 300 lines):
diff -r 71e56052768f -r 19131d568007 src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -155,7 +155,7 @@
virtual Counter value() const = 0;
virtual Result result() const = 0;
virtual Result total() const = 0;
-virtual void visit(Visit visitor) { visitor.visit(*this); }
+void visit(Visit visitor) { visitor.visit(*this); }
};
template class Stat
@@ -167,12 +167,12 @@
public:
ScalarInfo(Stat stat) : s(stat) {}
-virtual bool check() const { return s.check(); }
-virtual Counter value() const { return s.value(); }
-virtual Result result() const { return s.result(); }
-virtual Result total() const { return s.total(); }
-virtual void reset() { s.reset(); }
-virtual bool zero() const { return s.zero(); }
+bool check() const { return s.check(); }
+Counter value() const { return s.value(); }
+Result result() const { return s.result(); }
+Result total() const { return s.total(); }
+void reset() { s.reset(); }
+bool zero() const { return s.zero(); }
};
class VectorInfoBase : public Info
@@ -183,10 +183,10 @@
mutable std::vectorstd::string subdescs;
public:
-virtual size_type size() const = 0;
+virtual size_type size() const = 0;
virtual const VCounter value() const = 0;
virtual const VResult result() const = 0;
-virtual Result total() const = 0;
+virtual Result total() const = 0;
void
update()
@@ -213,29 +213,29 @@
public:
VectorInfo(Stat stat) : s(stat) {}
-virtual bool check() const { return s.check(); }
-virtual bool zero() const { return s.zero(); }
-virtual void reset() { s.reset(); }
+bool check() const { return s.check(); }
+bool zero() const { return s.zero(); }
+void reset() { s.reset(); }
-virtual size_type size() const { return s.size(); }
+size_type size() const { return s.size(); }
-virtual VCounter
+VCounter
value() const
{
s.value(cvec);
return cvec;
}
-virtual const VResult
+const VResult
result() const
{
s.result(rvec);
return rvec;
}
-virtual Result total() const { return s.total(); }
+Result total() const { return s.total(); }
-virtual void
+void
visit(Visit visitor)
{
update();
@@ -274,11 +274,11 @@
public:
DistInfo(Stat stat) : s(stat) {}
-virtual bool check() const { return s.check(); }
-virtual void reset() { s.reset(); }
-virtual bool zero() const { return s.zero(); }
+bool check() const { return s.check(); }
+void reset() { s.reset(); }
+bool zero() const { return s.zero(); }
-virtual void
+void
visit(Visit visitor)
{
s.update(this);
@@ -323,12 +323,12 @@
public:
VectorDistInfo(Stat stat) : s(stat) {}
-virtual bool check() const { return s.check(); }
-virtual void reset() { s.reset(); }
-virtual size_type size() const { return s.size(); }
-virtual bool zero() const { return s.zero(); }
+bool check() const { return s.check(); }
+void reset() { s.reset(); }
+size_type size() const { return s.size(); }
+bool zero() const { return s.zero(); }
-virtual void
+void
visit(Visit visitor)
{
update();
@@ -368,11 +368,11 @@
public:
Vector2dInfo(Stat stat) : s(stat) {}
-virtual bool check() const { return s.check(); }
-virtual void reset() { s.reset(); }
-virtual bool zero() const { return s.zero(); }
+bool check() const { return s.check(); }
+void reset() { s.reset(); }
+bool zero() const { return s.zero(); }
-virtual void
+void
visit(Visit visitor)
{
update();
@@ -862,12 +862,12 @@
class ProxyInfo : public ScalarInfoBase
{
public:
-virtual void visit(Visit visitor) { visitor.visit(*this); }
-virtual std::string str() const { return to_string(value()); }
-virtual size_type size() const { return 1; }
-virtual bool zero() const { return value() == 0; }
-virtual bool check() const { return true; }
-virtual void reset() { }
+void visit(Visit visitor) { visitor.visit(*this); }
+std::string str() const { return to_string(value()); }
+size_type size() const { return 1; }
+bool zero() const { return value() == 0; }
+bool check() const { return true; }
+void reset() { }
};
template class T
@@ -878,9 +878,9 @@
public:
ValueProxy(T val) : scalar(val) {}
-virtual Counter value() const { return *scalar;
[m5-dev] changeset in m5: stats: better naming of template parameters for...
changeset 2c9823c60c8c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2c9823c60c8c
description:
stats: better naming of template parameters for the wrapper stuff
Parent and Child are bad names. Derived and Base are better.
diffstat:
1 file changed, 25 insertions(+), 25 deletions(-)
src/base/statistics.hh | 50
diffs (144 lines):
diff -r 19131d568007 -r 2c9823c60c8c src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -397,16 +397,16 @@
const Info *info() const;
};
-template class Parent, class Child, template class class Info
-class Wrap : public Child
+template class Derived, class Base, template class class Info
+class Wrap : public Base
{
public:
-typedef Parent ParentType;
-typedef Child ChildType;
-typedef InfoChild InfoType;
+typedef Derived DerivedType;
+typedef Base BaseType;
+typedef InfoBase InfoType;
protected:
-Parent self() { return *reinterpret_castParent *(this); }
+Derived self() { return *reinterpret_castDerived *(this); }
protected:
InfoType *
@@ -444,7 +444,7 @@
* @param name The new name.
* @return A reference to this stat.
*/
-Parent
+Derived
name(const std::string _name)
{
InfoType *info = this-info();
@@ -459,7 +459,7 @@
* @param desc The new description.
* @return A reference to this stat.
*/
-Parent
+Derived
desc(const std::string _desc)
{
this-info()-desc = _desc;
@@ -471,7 +471,7 @@
* @param _precision The new precision
* @return A reference to this stat.
*/
-Parent
+Derived
precision(int _precision)
{
this-info()-precision = _precision;
@@ -483,7 +483,7 @@
* @param f The new flags.
* @return A reference to this stat.
*/
-Parent
+Derived
flags(StatFlags _flags)
{
this-info()-flags |= _flags;
@@ -497,7 +497,7 @@
* @return A reference to this stat.
*/
template class Stat
-Parent
+Derived
prereq(const Stat prereq)
{
this-info()-prereq = prereq.info();
@@ -505,13 +505,13 @@
}
};
-template class Parent, class Child, template class Child class Info
-class WrapVec : public WrapParent, Child, Info
+template class Derived, class Base, template class Base class Info
+class WrapVec : public WrapDerived, Base, Info
{
public:
-typedef Parent ParentType;
-typedef Child ChildType;
-typedef InfoChild InfoType;
+typedef Derived DerivedType;
+typedef Base BaseType;
+typedef InfoBase InfoType;
public:
// The following functions are specific to vectors. If you use them
@@ -524,7 +524,7 @@
* @param name The new name of the subfield.
* @return A reference to this stat.
*/
-Parent
+Derived
subname(off_type index, const std::string name)
{
std::vectorstd::string subn = this-info()-subnames;
@@ -541,7 +541,7 @@
* @param desc The new description of the subfield
* @return A reference to this stat.
*/
-Parent
+Derived
subdesc(off_type index, const std::string desc)
{
std::vectorstd::string subd = this-info()-subdescs;
@@ -554,20 +554,20 @@
};
-template class Parent, class Child, template class Child class Info
-class WrapVec2d : public WrapVecParent, Child, Info
+template class Derived, class Base, template class Base class Info
+class WrapVec2d : public WrapVecDerived, Base, Info
{
public:
-typedef Parent ParentType;
-typedef Child ChildType;
-typedef InfoChild InfoType;
+typedef Derived DerivedType;
+typedef Base BaseType;
+typedef InfoBase InfoType;
public:
/**
* @warning This makes the assumption that if you're gonna subnames a 2d
* vector, you're subnaming across all y
*/
-Parent
+Derived
ysubnames(const char **names)
{
InfoType *info = this-info();
@@ -577,7 +577,7 @@
return this-self();
}
-Parent
+Derived
ysubname(off_type index, const std::string subname)
{
InfoType *info = this-info();
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[m5-dev] changeset in m5: stats: Add a wrapper class for the information ...
changeset 7674070ccc92 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7674070ccc92
description:
stats: Add a wrapper class for the information side of things.
This provides an easy way to provide the callbacks into the data side
of things from the info side of things. Rename Wrap to DataWrap so it
is more easily distinguishable from InfoWrap
diffstat:
1 file changed, 98 insertions(+), 125 deletions(-)
src/base/statistics.hh | 223 +---
diffs (truncated from 538 to 300 lines):
diff -r 2c9823c60c8c -r 7674070ccc92 src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -115,7 +115,7 @@
virtual ~Info();
/**
- * Reset the corresponding stat to the default state.
+ * Reset the stat to the default state.
*/
virtual void reset() = 0;
@@ -149,6 +149,20 @@
static bool less(Info *stat1, Info *stat2);
};
+template class Stat, class Base
+class InfoWrap : public Base
+{
+ protected:
+Stat s;
+
+ public:
+InfoWrap(Stat stat) : s(stat) {}
+
+bool check() const { return s.check(); }
+void reset() { s.reset(); }
+bool zero() const { return s.zero(); }
+};
+
class ScalarInfoBase : public Info
{
public:
@@ -159,20 +173,14 @@
};
template class Stat
-class ScalarInfo : public ScalarInfoBase
+class ScalarInfo : public InfoWrapStat, ScalarInfoBase
{
- protected:
-Stat s;
+ public:
+ScalarInfo(Stat stat) : InfoWrapStat, ScalarInfoBase(stat) {}
- public:
-ScalarInfo(Stat stat) : s(stat) {}
-
-bool check() const { return s.check(); }
-Counter value() const { return s.value(); }
-Result result() const { return s.result(); }
-Result total() const { return s.total(); }
-void reset() { s.reset(); }
-bool zero() const { return s.zero(); }
+Counter value() const { return this-s.value(); }
+Result result() const { return this-s.result(); }
+Result total() const { return this-s.total(); }
};
class VectorInfoBase : public Info
@@ -203,43 +211,38 @@
};
template class Stat
-class VectorInfo : public VectorInfoBase
+class VectorInfo : public InfoWrapStat, VectorInfoBase
{
protected:
-Stat s;
mutable VCounter cvec;
mutable VResult rvec;
public:
-VectorInfo(Stat stat) : s(stat) {}
+VectorInfo(Stat stat) : InfoWrapStat, VectorInfoBase(stat) {}
-bool check() const { return s.check(); }
-bool zero() const { return s.zero(); }
-void reset() { s.reset(); }
-
-size_type size() const { return s.size(); }
+size_type size() const { return this-s.size(); }
VCounter
value() const
{
-s.value(cvec);
+this-s.value(cvec);
return cvec;
}
const VResult
result() const
{
-s.result(rvec);
+this-s.result(rvec);
return rvec;
}
-Result total() const { return s.total(); }
+Result total() const { return this-s.total(); }
void
visit(Visit visitor)
{
-update();
-s.update(this);
+this-update();
+this-s.update(this);
visitor.visit(*this);
}
};
@@ -266,22 +269,15 @@
};
template class Stat
-class DistInfo : public DistInfoBase
+class DistInfo : public InfoWrapStat, DistInfoBase
{
- protected:
-Stat s;
-
public:
-DistInfo(Stat stat) : s(stat) {}
-
-bool check() const { return s.check(); }
-void reset() { s.reset(); }
-bool zero() const { return s.zero(); }
+DistInfo(Stat stat) : InfoWrapStat, DistInfoBase(stat) {}
void
visit(Visit visitor)
{
-s.update(this);
+this-s.update(this);
visitor.visit(*this);
}
};
@@ -315,24 +311,18 @@
};
template class Stat
-class VectorDistInfo : public VectorDistInfoBase
+class VectorDistInfo : public InfoWrapStat, VectorDistInfoBase
{
- protected:
-Stat s;
+ public:
+VectorDistInfo(Stat stat) : InfoWrapStat, VectorDistInfoBase(stat) {}
- public:
-VectorDistInfo(Stat stat) : s(stat) {}
-
-bool check() const { return s.check(); }
-void reset() { s.reset(); }
-size_type size() const { return s.size(); }
-bool zero() const { return s.zero(); }
+size_type size() const { return this-s.size(); }
void
visit(Visit visitor)
{
-update();
-s.update(this);
+this-update();
+this-s.update(this);
visitor.visit(*this);
}
};
@@ -360,23 +350,16 @@
};
template class Stat
-class Vector2dInfo : public Vector2dInfoBase
+class Vector2dInfo : public InfoWrapStat, Vector2dInfoBase
{
- protected:
-Stat s;
-
public:
-Vector2dInfo(Stat stat) : s(stat) {}
-
-bool check() const { return s.check(); }
-void reset() { s.reset(); }
-bool zero() const { return s.zero(); }
+Vector2dInfo(Stat stat) : InfoWrapStat,
[m5-dev] changeset in m5: stats: stick the distribution's fancy parameter...
changeset 471090ec173e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=471090ec173e
description:
stats: stick the distribution's fancy parameter into the parameters
structure.
diffstat:
3 files changed, 22 insertions(+), 26 deletions(-)
src/base/statistics.hh | 23 ++-
src/base/stats/mysql.cc |8
src/base/stats/text.cc | 17 -
diffs (130 lines):
diff -r 7674070ccc92 -r 471090ec173e src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -257,8 +257,6 @@
Counter sum;
Counter squares;
Counter samples;
-
-bool fancy;
};
class DistInfoBase : public Info
@@ -1419,8 +1417,9 @@
Counter bucket_size;
/** The number of buckets. Equal to (max-min)/bucket_size. */
size_type buckets;
+
+enum { fancy = false };
};
-enum { fancy = false };
private:
/** The minimum value to track. */
@@ -1556,10 +1555,10 @@
class FancyStor
{
public:
-struct Params : public StorageParams {};
-
- public:
-enum { fancy = true };
+struct Params : public StorageParams
+{
+enum { fancy = true };
+};
private:
/** The current sum. */
@@ -1632,10 +1631,10 @@
class AvgFancy
{
public:
-struct Params : public StorageParams {};
-
- public:
-enum { fancy = true };
+struct Params : public StorageParams
+{
+enum { fancy = true };
+};
private:
/** Current total. */
@@ -1765,7 +1764,6 @@
void
update(DistInfoBase *base)
{
-base-data.fancy = Storage::fancy;
data()-update(info(), base-data);
}
@@ -1881,7 +1879,6 @@
size_type size = this-size();
base-data.resize(size);
for (off_type i = 0; i size; ++i) {
-base-data[i].fancy = Storage::fancy;
data(i)-update(info(), base-data[i]);
}
}
diff -r 7674070ccc92 -r 471090ec173e src/base/stats/mysql.cc
--- a/src/base/stats/mysql.cc Thu Mar 05 19:09:53 2009 -0800
+++ b/src/base/stats/mysql.cc Thu Mar 05 19:09:53 2009 -0800
@@ -583,8 +583,8 @@
if (!configure(info, DIST))
return;
-if (!info.data.fancy) {
-const Params *params = safe_castconst Params *(info.storageParams);
+const Params *params = safe_castconst Params *(info.storageParams);
+if (!params-fancy) {
stat.size = params-buckets;
stat.min = params-min;
stat.max = params-max;
@@ -599,8 +599,8 @@
if (!configure(info, VECTORDIST))
return;
-if (!info.data[0].fancy) {
-const Params *params = safe_castconst Params *(info.storageParams);
+const Params *params = safe_castconst Params *(info.storageParams);
+if (!params-fancy) {
stat.size = params-buckets;
stat.min = params-min;
stat.max = params-max;
diff -r 7674070ccc92 -r 471090ec173e src/base/stats/text.cc
--- a/src/base/stats/text.ccThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/stats/text.ccThu Mar 05 19:09:53 2009 -0800
@@ -673,12 +673,11 @@
print.squares = data.squares;
print.samples = data.samples;
-print.fancy = data.fancy;
+const DistStor::Params *params =
+safe_castconst DistStor::Params *(info.storageParams);
-if (!data.fancy) {
-const DistStor::Params *params =
-safe_castconst DistStor::Params *(info.storageParams);
-
+print.fancy = params-fancy;
+if (!params-fancy) {
print.min = params-min;
print.max = params-max;
print.bucket_size = params-bucket_size;
@@ -716,11 +715,11 @@
print.squares = info.data[i].squares;
print.samples = info.data[i].samples;
-print.fancy = info.data[i].fancy;
-if (!print.fancy) {
-const DistStor::Params *params =
-safe_castconst DistStor::Params *(info.storageParams);
+const DistStor::Params *params =
+safe_castconst DistStor::Params *(info.storageParams);
+print.fancy = params-fancy;
+if (!params-fancy) {
print.min = params-min;
print.max = params-max;
print.bucket_size = params-bucket_size;
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: stats: remove the template wart left over from ...
changeset a4c935e9cf99 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a4c935e9cf99
description:
stats: remove the template wart left over from the ancient binning stuff
diffstat:
1 file changed, 14 insertions(+), 28 deletions(-)
src/base/statistics.hh | 42 ++
diffs (151 lines):
diff -r 471090ec173e -r a4c935e9cf99 src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -2350,8 +2350,7 @@
* This is a simple scalar statistic, like a counter.
* @sa Stat, ScalarBase, StatStor
*/
-templateint N = 0
-class Scalar : public DataWrapScalarN, ScalarBaseStatStor, ScalarInfo
+class Scalar : public DataWrapScalar, ScalarBaseStatStor, ScalarInfo
{
public:
/** The base implementation. */
@@ -2398,8 +2397,7 @@
* A stat that calculates the per tick average of a value.
* @sa Stat, ScalarBase, AvgStor
*/
-templateint N = 0
-class Average : public DataWrapAverageN, ScalarBaseAvgStor, ScalarInfo
+class Average : public DataWrapAverage, ScalarBaseAvgStor, ScalarInfo
{
public:
/** The base implementation. */
@@ -2427,8 +2425,7 @@
* A vector of scalar stats.
* @sa Stat, VectorBase, StatStor
*/
-templateint N = 0
-class Vector : public DataWrapVecVectorN, VectorBaseStatStor, VectorInfo
+class Vector : public DataWrapVecVector, VectorBaseStatStor, VectorInfo
{
public:
/** The base implementation. */
@@ -2451,9 +2448,8 @@
* A vector of Average stats.
* @sa Stat, VectorBase, AvgStor
*/
-templateint N = 0
class AverageVector
-: public DataWrapVecAverageVectorN, VectorBaseAvgStor, VectorInfo
+: public DataWrapVecAverageVector, VectorBaseAvgStor, VectorInfo
{
public:
/**
@@ -2473,9 +2469,8 @@
* A 2-Dimensional vecto of scalar stats.
* @sa Stat, Vector2dBase, StatStor
*/
-templateint N = 0
class Vector2d
-: public DataWrapVec2dVector2dN, Vector2dBaseStatStor, Vector2dInfo
+: public DataWrapVec2dVector2d, Vector2dBaseStatStor, Vector2dInfo
{
public:
Vector2d
@@ -2490,9 +2485,8 @@
* A simple distribution stat.
* @sa Stat, DistBase, DistStor
*/
-templateint N = 0
class Distribution
-: public DataWrapDistributionN, DistBaseDistStor, DistInfo
+: public DataWrapDistribution, DistBaseDistStor, DistInfo
{
public:
/** Base implementation. */
@@ -2524,9 +2518,8 @@
* Calculates the mean and variance of all the samples.
* @sa Stat, DistBase, FancyStor
*/
-templateint N = 0
class StandardDeviation
-: public DataWrapStandardDeviationN, DistBaseFancyStor, DistInfo
+: public DataWrapStandardDeviation, DistBaseFancyStor, DistInfo
{
public:
/** The base implementation */
@@ -2546,9 +2539,8 @@
* Calculates the per tick mean and variance of the samples.
* @sa Stat, DistBase, AvgFancy
*/
-templateint N = 0
class AverageDeviation
-: public DataWrapAverageDeviationN, DistBaseAvgFancy, DistInfo
+: public DataWrapAverageDeviation, DistBaseAvgFancy, DistInfo
{
public:
/** The base implementation */
@@ -2568,9 +2560,8 @@
* A vector of distributions.
* @sa Stat, VectorDistBase, DistStor
*/
-templateint N = 0
class VectorDistribution
-: public DataWrapVecVectorDistributionN,
+: public DataWrapVecVectorDistribution,
VectorDistBaseDistStor,
VectorDistInfo
{
@@ -2605,9 +2596,8 @@
* This is a vector of StandardDeviation stats.
* @sa Stat, VectorDistBase, FancyStor
*/
-templateint N = 0
class VectorStandardDeviation
-: public DataWrapVecVectorStandardDeviationN,
+: public DataWrapVecVectorStandardDeviation,
VectorDistBaseFancyStor,
VectorDistInfo
{
@@ -2633,9 +2623,8 @@
* This is a vector of AverageDeviation stats.
* @sa Stat, VectorDistBase, AvgFancy
*/
-templateint N = 0
class VectorAverageDeviation
-: public DataWrapVecVectorAverageDeviationN,
+: public DataWrapVecVectorAverageDeviation,
VectorDistBaseAvgFancy,
VectorDistInfo
{
@@ -2828,8 +2817,7 @@
* Create a new ScalarStatNode.
* @param s The ScalarStat to place in a node.
*/
-template int N
-Temp(const ScalarN s)
+Temp(const Scalar s)
: node(new ScalarStatNode(s.info()))
{ }
@@ -2845,8 +2833,7 @@
* Create a new ScalarStatNode.
* @param s The ScalarStat to place in a node.
*/
-template int N
-Temp(const AverageN s)
+Temp(const Average s)
: node(new ScalarStatNode(s.info()))
{ }
@@ -2854,8 +2841,7 @@
* Create a new VectorStatNode.
* @param s The VectorStat to place in a node.
*/
-template int N
-Temp(const VectorN s)
+Temp(const Vector s)
: node(new VectorStatNode(s.info()))
{ }
___
m5-dev mailing list
[m5-dev] changeset in m5: stats: Fix all stats usages to deal with templa...
changeset 3cf8e71257e0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3cf8e71257e0
description:
stats: Fix all stats usages to deal with template fixes
diffstat:
50 files changed, 486 insertions(+), 486 deletions(-)
src/arch/alpha/kernel_stats.hh| 12 +--
src/arch/alpha/tlb.hh | 22 ++---
src/arch/mips/tlb.hh | 16 ++--
src/base/hybrid_pred.hh | 12 +--
src/base/sat_counter.hh | 12 +--
src/cpu/base.hh |2
src/cpu/inorder/cpu.hh| 14 +--
src/cpu/inorder/pipeline_stage.hh | 14 +--
src/cpu/inorder/resource.hh |2
src/cpu/inorder/resources/bpred_unit.hh | 16 ++--
src/cpu/inorder/resources/branch_predictor.hh |4 -
src/cpu/inorder/resources/execution_unit.hh |4 -
src/cpu/inorder/resources/inst_buffer.hh |2
src/cpu/inorder/resources/mult_div_unit.hh|4 -
src/cpu/memtest/memtest.hh|6 -
src/cpu/o3/bpred_unit.hh | 16 ++--
src/cpu/o3/commit.hh | 28 +++
src/cpu/o3/cpu.hh |8 +-
src/cpu/o3/decode.hh | 20 ++---
src/cpu/o3/fetch.hh | 24 +++---
src/cpu/o3/iew.hh | 54 +++---
src/cpu/o3/inst_queue.hh | 38 +-
src/cpu/o3/lsq_unit.hh| 20 ++---
src/cpu/o3/mem_dep_unit.hh|8 +-
src/cpu/o3/rename.hh | 38 +-
src/cpu/ozone/back_end.hh | 92 -
src/cpu/ozone/cpu.hh |4 -
src/cpu/ozone/front_end.hh| 40 +-
src/cpu/ozone/inorder_back_end.hh |2
src/cpu/ozone/inst_queue.hh | 32
src/cpu/ozone/lsq_unit.hh |2
src/cpu/ozone/lw_back_end.hh | 84 +++---
src/cpu/ozone/lw_lsq.hh |4 -
src/cpu/simple/base.hh| 14 +--
src/cpu/thread_state.hh |4 -
src/dev/copy_engine.hh|4 -
src/dev/etherdevice.hh| 64 -
src/dev/ide_disk.hh | 12 +--
src/dev/sinic.hh | 38 +-
src/kern/kernel_stats.hh | 16 ++--
src/mem/cache/base.hh | 32
src/mem/cache/prefetch/base.hh| 18 ++--
src/mem/cache/tags/base.hh| 10 +-
src/mem/cache/tags/fa_lru.hh |6 -
src/mem/cache/tags/iic.hh | 14 +--
src/mem/cache/tags/iic_repl/gen.hh|6 -
src/mem/dram.hh | 36 -
src/sim/faults.hh |2
src/sim/process.hh|2
src/unittest/stattest.cc | 38 +-
diffs (truncated from 1953 to 300 lines):
diff -r a4c935e9cf99 -r 3cf8e71257e0 src/arch/alpha/kernel_stats.hh
--- a/src/arch/alpha/kernel_stats.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/arch/alpha/kernel_stats.hhThu Mar 05 19:09:53 2009 -0800
@@ -62,15 +62,15 @@
void changeMode(cpu_mode newmode, ThreadContext *tc);
private:
-Stats::Vector _callpal;
-//Stats::Vector _faults;
+Stats::Vector _callpal;
+//Stats::Vector _faults;
-Stats::Vector _mode;
-Stats::Vector _modeGood;
+Stats::Vector _mode;
+Stats::Vector _modeGood;
Stats::Formula _modeFraction;
-Stats::Vector _modeTicks;
+Stats::Vector _modeTicks;
-Stats::Scalar _swap_context;
+Stats::Scalar _swap_context;
public:
Statistics(System *system);
diff -r a4c935e9cf99 -r 3cf8e71257e0 src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh Thu Mar 05 19:09:53 2009 -0800
+++ b/src/arch/alpha/tlb.hh Thu Mar 05 19:09:53 2009 -0800
@@ -121,9 +121,9 @@
class ITB : public TLB
{
protected:
-mutable Stats::Scalar hits;
-mutable Stats::Scalar misses;
-mutable Stats::Scalar acv;
+mutable Stats::Scalar hits;
+mutable Stats::Scalar misses;
+mutable Stats::Scalar acv;
mutable Stats::Formula accesses;
public:
@@ -139,14 +139,14 @@
class DTB : public TLB
{
protected:
-mutable Stats::Scalar read_hits;
-mutable Stats::Scalar read_misses;
-mutable Stats::Scalar read_acv;
-mutable Stats::Scalar read_accesses;
-mutable Stats::Scalar write_hits;
-mutable Stats::Scalar write_misses;
-mutable Stats::Scalar write_acv;
-mutable Stats::Scalar write_accesses;
+mutable Stats::Scalar read_hits;
+mutable Stats::Scalar read_misses;
+mutable Stats::Scalar read_acv;
+mutable Stats::Scalar
[m5-dev] changeset in m5: stats: clean up how templates are used on the d...
changeset 4f887be9e1b6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4f887be9e1b6
description:
stats: clean up how templates are used on the data side.
This basically works by taking advantage of the curiously recurring
template
pattern in an intelligent way so as to reduce the number of lines of
code
and hopefully make things a little bit clearer.
diffstat:
2 files changed, 326 insertions(+), 413 deletions(-)
src/base/statistics.cc | 100 +++
src/base/statistics.hh | 639
diffs (truncated from 1375 to 300 lines):
diff -r 3cf8e71257e0 -r 4f887be9e1b6 src/base/statistics.cc
--- a/src/base/statistics.ccThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.ccThu Mar 05 19:09:53 2009 -0800
@@ -158,7 +158,7 @@
bool
Info::baseCheck() const
{
-if (!(flags init)) {
+if (!(flags Stats::init)) {
#ifdef DEBUG
cprintf(this is stat number %d\n, id);
#endif
@@ -175,55 +175,6 @@
}
-void
-FormulaBase::result(VResult vec) const
-{
-if (root)
-vec = root-result();
-}
-
-Result
-FormulaBase::total() const
-{
-return root ? root-total() : 0.0;
-}
-
-size_type
-FormulaBase::size() const
-{
-if (!root)
-return 0;
-else
-return root-size();
-}
-
-void
-FormulaBase::reset()
-{
-}
-
-bool
-FormulaBase::zero() const
-{
-VResult vec;
-result(vec);
-for (off_t i = 0; i vec.size(); ++i)
-if (vec[i] != 0.0)
-return false;
-return true;
-}
-
-void
-FormulaBase::update(Info *)
-{
-}
-
-string
-FormulaBase::str() const
-{
-return root ? root-str() : ;
-}
-
Formula::Formula()
{
setInit();
@@ -256,6 +207,55 @@
}
void
+Formula::result(VResult vec) const
+{
+if (root)
+vec = root-result();
+}
+
+Result
+Formula::total() const
+{
+return root ? root-total() : 0.0;
+}
+
+size_type
+Formula::size() const
+{
+if (!root)
+return 0;
+else
+return root-size();
+}
+
+void
+Formula::reset()
+{
+}
+
+bool
+Formula::zero() const
+{
+VResult vec;
+result(vec);
+for (off_t i = 0; i vec.size(); ++i)
+if (vec[i] != 0.0)
+return false;
+return true;
+}
+
+void
+Formula::update()
+{
+}
+
+string
+Formula::str() const
+{
+return root ? root-str() : ;
+}
+
+void
check()
{
typedef listInfo *::iterator iter_t;
diff -r 3cf8e71257e0 -r 4f887be9e1b6 src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -115,6 +115,14 @@
virtual ~Info();
/**
+ * Check that this stat has been set up properly and is ready for
+ * use
+ * @return true for success
+ */
+virtual bool check() const = 0;
+bool baseCheck() const;
+
+/**
* Reset the stat to the default state.
*/
virtual void reset() = 0;
@@ -126,14 +134,6 @@
virtual bool zero() const = 0;
/**
- * Check that this stat has been set up properly and is ready for
- * use
- * @return true for success
- */
-virtual bool check() const = 0;
-bool baseCheck() const;
-
-/**
* Visitor entry for outputing statistics data
*/
virtual void visit(Visit visitor) = 0;
@@ -187,8 +187,8 @@
{
public:
/** Names and descriptions of subfields. */
-mutable std::vectorstd::string subnames;
-mutable std::vectorstd::string subdescs;
+std::vectorstd::string subnames;
+std::vectorstd::string subdescs;
public:
virtual size_type size() const = 0;
@@ -242,7 +242,7 @@
visit(Visit visitor)
{
this-update();
-this-s.update(this);
+this-s.update();
visitor.visit(*this);
}
};
@@ -275,7 +275,7 @@
void
visit(Visit visitor)
{
-this-s.update(this);
+this-s.update();
visitor.visit(*this);
}
};
@@ -285,9 +285,9 @@
public:
std::vectorDistData data;
- /** Names and descriptions of subfields. */
-mutable std::vectorstd::string subnames;
-mutable std::vectorstd::string subdescs;
+/** Names and descriptions of subfields. */
+std::vectorstd::string subnames;
+std::vectorstd::string subdescs;
protected:
/** Local storage for the entry values, used for printing. */
@@ -320,7 +320,7 @@
visit(Visit visitor)
{
this-update();
-this-s.update(this);
+this-s.update();
visitor.visit(*this);
}
};
@@ -333,10 +333,11 @@
std::vectorstd::string subdescs;
std::vectorstd::string y_subnames;
+size_type x;
+size_type y;
+
/** Local storage for the entry values, used for printing. */
mutable VCounter cvec;
-mutable size_type x;
-mutable size_type y;
public:
void
@@ -357,7 +358,7 @@
visit(Visit visitor)
{
this-update();
-this-s.update(this);
+this-s.update();
[m5-dev] changeset in m5: stats: create an enable phase, and a prepare ph...
changeset 00251eb95de7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=00251eb95de7
description:
stats: create an enable phase, and a prepare phase.
Enable more or less takes the place of check, but also allows stats to
do some other configuration. Prepare moves all of the code that readies
a stat for dumping into a separate function in preparation for
supporting
serialization of certain pieces of statistics data.
While we're at it, clean up the visitor code and some of the python
code.
diffstat:
7 files changed, 215 insertions(+), 162 deletions(-)
src/base/statistics.cc| 67 ---
src/base/statistics.hh| 264 +
src/base/stats/output.cc |3
src/python/m5/core.py |7 +
src/python/m5/simulate.py | 14 +-
src/python/m5/stats.py| 19 ++-
src/python/swig/stats.i |3
diffs (truncated from 758 to 300 lines):
diff -r 4f887be9e1b6 -r 00251eb95de7 src/base/statistics.cc
--- a/src/base/statistics.ccThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.ccThu Mar 05 19:09:53 2009 -0800
@@ -32,6 +32,7 @@
#include fstream
#include list
#include map
+#include set
#include string
#include base/callback.hh
@@ -174,6 +175,41 @@
return true;
}
+void
+Info::enable()
+{
+}
+
+void
+VectorInfoBase::enable()
+{
+size_type s = size();
+if (subnames.size() s)
+subnames.resize(s);
+if (subdescs.size() s)
+subdescs.resize(s);
+}
+
+void
+VectorDistInfoBase::enable()
+{
+size_type s = size();
+if (subnames.size() s)
+subnames.resize(s);
+if (subdescs.size() s)
+subdescs.resize(s);
+}
+
+void
+Vector2dInfoBase::enable()
+{
+if (subnames.size() x)
+subnames.resize(x);
+if (subdescs.size() x)
+subdescs.resize(x);
+if (y_subnames.size() y)
+y_subnames.resize(y);
+}
Formula::Formula()
{
@@ -244,11 +280,6 @@
return true;
}
-void
-Formula::update()
-{
-}
-
string
Formula::str() const
{
@@ -256,7 +287,7 @@
}
void
-check()
+enable()
{
typedef listInfo *::iterator iter_t;
@@ -277,17 +308,21 @@
statsList().sort(Info::less);
-if (i == end)
-return;
+for (i = statsList().begin(); i != end; ++i) {
+Info *info = *i;
+info-enable();
+}
+}
-iter_t last = i;
-++i;
-
-for (i = statsList().begin(); i != end; ++i) {
-if ((*i)-name == (*last)-name)
-panic(same name used twice! name=%s\n, (*i)-name);
-
-last = i;
+void
+prepare()
+{
+listInfo *::iterator i = statsList().begin();
+listInfo *::iterator end = statsList().end();
+while (i != end) {
+Info *info = *i;
+info-prepare();
+++i;
}
}
diff -r 4f887be9e1b6 -r 00251eb95de7 src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -123,6 +123,16 @@
bool baseCheck() const;
/**
+ * Enable the stat for use
+ */
+virtual void enable();
+
+/**
+ * Prepare the stat for dumping.
+ */
+virtual void prepare() = 0;
+
+/**
* Reset the stat to the default state.
*/
virtual void reset() = 0;
@@ -159,7 +169,13 @@
InfoWrap(Stat stat) : s(stat) {}
bool check() const { return s.check(); }
+void prepare() { s.prepare(); }
void reset() { s.reset(); }
+void
+visit(Visit visitor)
+{
+visitor.visit(*static_castBase *(this));
+}
bool zero() const { return s.zero(); }
};
@@ -169,7 +185,6 @@
virtual Counter value() const = 0;
virtual Result result() const = 0;
virtual Result total() const = 0;
-void visit(Visit visitor) { visitor.visit(*this); }
};
template class Stat
@@ -191,23 +206,13 @@
std::vectorstd::string subdescs;
public:
+void enable();
+
+ public:
virtual size_type size() const = 0;
virtual const VCounter value() const = 0;
virtual const VResult result() const = 0;
virtual Result total() const = 0;
-
-void
-update()
-{
-if (!subnames.empty()) {
-size_type s = size();
-if (subnames.size() s)
-subnames.resize(s);
-
-if (subdescs.size() s)
-subdescs.resize(s);
-}
-}
};
template class Stat
@@ -237,14 +242,6 @@
}
Result total() const { return this-s.total(); }
-
-void
-visit(Visit visitor)
-{
-this-update();
-this-s.update();
-visitor.visit(*this);
-}
};
struct DistData
@@ -271,13 +268,6 @@
{
public:
DistInfo(Stat stat) : InfoWrapStat, DistInfoBase(stat) {}
-
-void
-visit(Visit visitor)
-{
-this-s.update();
-visitor.visit(*this);
-}
};
class VectorDistInfoBase : public Info
@@ -288,6 +278,7 @@
/** Names and descriptions of
Re: [m5-dev] changeset in m5: stats: remove the template wart left over from ...
Just so everyone knows, this change fixes an old problem with the
template stuff left over from the binning days (for those of you that
remember). The thing that changes for people as a result is that the
name of the stat Classes has slightly changed.
We used to say things like
Stats::Scalar
Stats::Vector
These should now just be:
Stats::Scalar
Stats::Vector
You're simply removing the which was totally useless anyway.
Nate
On Thu, Mar 5, 2009 at 7:11 PM, Nathan Binkert n...@binkert.org wrote:
changeset a4c935e9cf99 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a4c935e9cf99
description:
stats: remove the template wart left over from the ancient binning
stuff
diffstat:
1 file changed, 14 insertions(+), 28 deletions(-)
src/base/statistics.hh | 42 ++
diffs (151 lines):
diff -r 471090ec173e -r a4c935e9cf99 src/base/statistics.hh
--- a/src/base/statistics.hh Thu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hh Thu Mar 05 19:09:53 2009 -0800
@@ -2350,8 +2350,7 @@
* This is a simple scalar statistic, like a counter.
* @sa Stat, ScalarBase, StatStor
*/
-templateint N = 0
-class Scalar : public DataWrapScalarN, ScalarBaseStatStor, ScalarInfo
+class Scalar : public DataWrapScalar, ScalarBaseStatStor, ScalarInfo
{
public:
/** The base implementation. */
@@ -2398,8 +2397,7 @@
* A stat that calculates the per tick average of a value.
* @sa Stat, ScalarBase, AvgStor
*/
-templateint N = 0
-class Average : public DataWrapAverageN, ScalarBaseAvgStor, ScalarInfo
+class Average : public DataWrapAverage, ScalarBaseAvgStor, ScalarInfo
{
public:
/** The base implementation. */
@@ -2427,8 +2425,7 @@
* A vector of scalar stats.
* @sa Stat, VectorBase, StatStor
*/
-templateint N = 0
-class Vector : public DataWrapVecVectorN, VectorBaseStatStor,
VectorInfo
+class Vector : public DataWrapVecVector, VectorBaseStatStor, VectorInfo
{
public:
/** The base implementation. */
@@ -2451,9 +2448,8 @@
* A vector of Average stats.
* @sa Stat, VectorBase, AvgStor
*/
-templateint N = 0
class AverageVector
- : public DataWrapVecAverageVectorN, VectorBaseAvgStor, VectorInfo
+ : public DataWrapVecAverageVector, VectorBaseAvgStor, VectorInfo
{
public:
/**
@@ -2473,9 +2469,8 @@
* A 2-Dimensional vecto of scalar stats.
* @sa Stat, Vector2dBase, StatStor
*/
-templateint N = 0
class Vector2d
- : public DataWrapVec2dVector2dN, Vector2dBaseStatStor, Vector2dInfo
+ : public DataWrapVec2dVector2d, Vector2dBaseStatStor, Vector2dInfo
{
public:
Vector2d
@@ -2490,9 +2485,8 @@
* A simple distribution stat.
* @sa Stat, DistBase, DistStor
*/
-templateint N = 0
class Distribution
- : public DataWrapDistributionN, DistBaseDistStor, DistInfo
+ : public DataWrapDistribution, DistBaseDistStor, DistInfo
{
public:
/** Base implementation. */
@@ -2524,9 +2518,8 @@
* Calculates the mean and variance of all the samples.
* @sa Stat, DistBase, FancyStor
*/
-templateint N = 0
class StandardDeviation
- : public DataWrapStandardDeviationN, DistBaseFancyStor, DistInfo
+ : public DataWrapStandardDeviation, DistBaseFancyStor, DistInfo
{
public:
/** The base implementation */
@@ -2546,9 +2539,8 @@
* Calculates the per tick mean and variance of the samples.
* @sa Stat, DistBase, AvgFancy
*/
-templateint N = 0
class AverageDeviation
- : public DataWrapAverageDeviationN, DistBaseAvgFancy, DistInfo
+ : public DataWrapAverageDeviation, DistBaseAvgFancy, DistInfo
{
public:
/** The base implementation */
@@ -2568,9 +2560,8 @@
* A vector of distributions.
* @sa Stat, VectorDistBase, DistStor
*/
-templateint N = 0
class VectorDistribution
- : public DataWrapVecVectorDistributionN,
+ : public DataWrapVecVectorDistribution,
VectorDistBaseDistStor,
VectorDistInfo
{
@@ -2605,9 +2596,8 @@
* This is a vector of StandardDeviation stats.
* @sa Stat, VectorDistBase, FancyStor
*/
-templateint N = 0
class VectorStandardDeviation
- : public DataWrapVecVectorStandardDeviationN,
+ : public DataWrapVecVectorStandardDeviation,
VectorDistBaseFancyStor,
VectorDistInfo
{
@@ -2633,9 +2623,8 @@
* This is a vector of AverageDeviation stats.
* @sa Stat, VectorDistBase, AvgFancy
*/
-templateint N = 0
class VectorAverageDeviation
- : public DataWrapVecVectorAverageDeviationN,
+ : public DataWrapVecVectorAverageDeviation,
VectorDistBaseAvgFancy,
VectorDistInfo
{
@@ -2828,8 +2817,7 @@
* Create a new ScalarStatNode.
* @param s The ScalarStat to place in a node.
*/
- template int N
- Temp(const ScalarN s)
+ Temp(const Scalar s)
: node(new
Re: [m5-dev] locked memory accesses
Quoting Steve Reinhardt ste...@gmail.com: On Thu, Mar 5, 2009 at 6:33 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: Quoting Steve Reinhardt ste...@gmail.com: On Wed, Mar 4, 2009 at 7:03 AM, Steve Reinhardt ste...@gmail.com wrote: I think there are two possible solutions: 1. Add a retry response code for atomic requests (along the lines of the error codes we alrady have in packet.hh) and then make sure that all the places where we issue atomic requests can deal with them appropriately. Oddly enough it's reminiscent of the LL/SC solution, though this is different since it only applies in atomic mode. 2. Force any cpu or device that wants to do locked accesses in atomic mode to do both the lock and unlock accesses back-to-back within the same event (e.g., in the same call to tick()). Neither of these sound particularly attractive. I like #2 better [...] Another advantage of #2 is that atomic-mode atomicity comes for free without touching the memory system at all. This is nice since it gives you a baseline that will work on any memory system (e.g., Ruby). There's also some possibility that we could avoid implementing timing-mode locking in main memory with this approach, by making the reasonable restriction that if you want to run in timing mode then you have to use caches. That may not hold if we have to deal with locked uncached accesses... I know these exist in real life, but I'm hoping that that's one of the features we can avoid by only running modern 64-bit software. Gabe, do you know off hand if there are locked uncached accesses in any of the code you've run so far? Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev I haven't reached a conclusion on what to do, but I have a few thoughts. First, I don't know if we'd be able to use #2 to get away with not implementing locking in the main memory for timing accesses. It would be impossible to do a read and write of a location in the same event because you'd have to wait around for each to complete. You'd either have to force all other accesses to wait around which might be a big performance hit. Also things might get really sticky with speculative accesses, although I think that may be true in general. Yea, you're right, but that wasn't my point... what I was trying to say was that if you (1) use option #2 to make atomicity just work in atomic mode from the memory system's point of view and (2) require the use of caches in timing mode so that you can rely on the cache coherence protocol to handle atomicity in timing mode (which probably isn't that hard, since you already have mechanisms for deferring invalidations), then the main memory object would never have to worry about implementing atomicity. (In contrast to the current situation, where main memory has its own independent implementation of LL/SC support just to deal with cacheless configs.) I like the idea of having lock and unlock flags, although I think it would be a good idea to not allow intervening operations even from the same source. With that restriction, locks could set up a condition where you'd only allow an access to happen if it was an unlock. If everything obeyed the rule of a lock and then an unlock that would guarantee atomicity and has the nice property that you don't have to keep track of -who- the access was originally from, just where the access was to. It may be next to impossible to actually know who has a lock if you have, for instance, a shared cache intervening. Yes, that's exactly what I was thinking already. All of the accesses I mentioned before and all of the CPU maintained data structure updates can happen with a single load-op-store, although I could believe there's some other ISA that needs something more elaborate. I'm not sure that it matters, as long as the CPU doesn't do any intervening unlocked memory accesses to the same block. As far as how to make atomic mode atomic (which -is- weird), I don't really like either of the options you mentioned either. The first one seems more naturally analogous to timing mode, but then why do we need atomic mode? The second one limits the effects of supporting this sort of instruction/operation, but it would probably really complicate the CPU and I'd bet have a lot of unintended consequences. I've been thinking about this in the background and I haven't been able to come up with a better idea though. I'll keep trying. What if for AtomicSimpleCPU we execute a macroinstruction on each tick instead of a microop? We're not really caring that much about timing anyway, and all of the other CPU models only work in timing mode so they won't be affected. The only place where this gets really ridiculous is for REP prefixes, but if it's not too hard we could only execute one iteration of a REP instead of the whole macroinstruction in just that case.
Re: [m5-dev] locked memory accesses
Here's another option: make the CPU model smart and when it sees a lock access have it keep running until it sees an unlock access. This might not be too bad if keep running could be implemented simply by doing something like a recursive tail call to tick(). Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] locked memory accesses
Here's another option: make the CPU model smart and when it sees a lock access have it keep running until it sees an unlock access. This might not be too bad if keep running could be implemented simply by doing something like a recursive tail call to tick(). There's already a big loop in the tick() function to simulate a cpu width (so we can set a low CPU frequency, but get a high instruction rate for rate matching). I'd rather see something like the for loop being changed into a while loop, and do a i++ or something like that to keep it going. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] locked memory accesses
On Thu, Mar 5, 2009 at 7:40 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: I like that option the best so far. I'll assume that's what we're doing unless I suddenly think of a compelling reason not to or if someone doesn't like it. Great... it should be even easier than I thought if you build off the width loop that's already in there (which I had forgotten about). Generally speaking, I don't consider myself qualified to make the necessary changes to the memory system stuff, especially the caches. Can someone please volunteer? I can start working on the ISA stuff maybe tonight or maybe tomorrow. A shared (queue) repository would probably be a good idea. I could probably do it once I find the time. The beauty of this approach is that you don't have to wait on any memory system changes to test in atomic mode, so I'd hope that it wouldn't hold you up too badly if it took a little while (week or two) before I get around to it. Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
How different are ITBs and DTBs anyway? It seems like for a UTB you'd want a single object that handles both ifetch and data translations using a common translate() method, not something that inherits from two different classes. E.g., why not just derive it from TLB? The two translation functions are different because every ISA does some different things for instructions vs data. Think about something like the executable bit. Philosophically, I agree... let's avoid virtual inheritance if at all possible. It's just not a good idea. Ok, so the question is, which of the other alternatives should we do? Gabe (mister TLB expert)? Korey (since this is mips code)? Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
On Thu, Mar 5, 2009 at 9:09 PM, nathan binkert n...@binkert.org wrote: How different are ITBs and DTBs anyway? It seems like for a UTB you'd want a single object that handles both ifetch and data translations using a common translate() method, not something that inherits from two different classes. E.g., why not just derive it from TLB? The two translation functions are different because every ISA does some different things for instructions vs data. Think about something like the executable bit. Right, but you could have a flag that says ifetch (or an ifetch/read/write enum in place of the read/write flag we have now) to control that behavior. Then the current ITB would panic on a read or write request, and the DTB would panic on an ifetch, but a UTB could handle all of the above. Or more realistically we could just punt on having separate ITB and DTB classes. Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
I believe the reason the UTB thing was done in that way was to try to match the current M5 infrastructure which require ITB and DTB pointers in every CPU model and have a few functions that hardcode (itb-___ or dtb-___). If you dont derive UTB from both ITB and DTB you'll have a problem there with compatibility...hence a big headache because you have to figure out how to create a single object representing the UTB but then get ITB/DTB base pointers to use the UTB version. I wouldn't say delete the UTB because you need that to boot Full System MIPS and doesn't some other ISA use Unified TLB as well? I'm not sure every drop of FS MIPS code made it into the tree, but you definitely need that UTB or it definitely wont work. So what's the solution? Well, it really depends on how willing we are to change how we traditionally use the ITB and DTB in M5 (as has been discussed previously). On Fri, Mar 6, 2009 at 12:17 AM, nathan binkert n...@binkert.org wrote: Right, but you could have a flag that says ifetch (or an ifetch/read/write enum in place of the read/write flag we have now) to control that behavior. Then the current ITB would panic on a read or write request, and the DTB would panic on an ifetch, but a UTB could handle all of the above. That's what I was suggesting with the extra parameter. So, it sounds like this is the right approach. Gabe, can you help me implement it? I'd think that it should be relatively easy, it probably just involves mostly busy work. Or more realistically we could just punt on having separate ITB and DTB classes. I personally think yes. I don't think it buys us very much. Maybe it shortens the rope we give the users when they build a configuration, but there's already way more than enough to allow a user to hang themselves. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- -- Korey L Sewell Graduate Student - PhD Candidate Computer Science Engineering University of Michigan ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
