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Ship it!
Hi Nilay, I see no reason why this would not work with our
, misses) += 1;
Actually, it may just be cleaner to have a function that returns the
index. Then you don't need all of the template mubmo jumbo.
Lisa Hsu wrote:
I did a single pass of trying to pass a reference of a stat to a
function. When it didn't work immediately, I
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- Lisa
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On 2011-04-22 17:16:05, Lisa Hsu wrote
There's more to it than that. I started it yesterday and I'll post a diff
today and you can see what I mean.
So one question to you Nate, is what do you prefer, doing a single #if
FULL_SYSTEM in the C++, or doing a if buildEnv[FULL_SYSTEM] in the python so
that the value passed into the C++ is
Korey, that's awesome. If you've done it already, then by all means, let's
see it on the review board.
And Steve, you are right, Ruby does not do stats per context, though
recently a set of my pushes made it possible to even pass that information
to Ruby. Nothing in the tree takes advantage of
:
AttributeError: 'module' object has no attribute 'outdir'
Lisa
On Wed, Apr 20, 2011 at 10:43 AM, Lisa Hsu h...@eecs.umich.edu wrote:
Korey, that's awesome. If you've done it already, then by all means, let's
see it on the review board.
And Steve, you are right, Ruby does not do stats per context
they need
to be the same length if used in a formula. Total miss latency needs
to have the same vector length as total misses.
Nate
On Mon, Apr 18, 2011 at 2:09 PM, Lisa Hsu h...@eecs.umich.edu
wrote:
I'm not sure I understand what the problem is either. Can different
VectorStats
I think the immediate fix is the pythonic fix from a few msgs ago. I
believe that's quick and easy. I think :).
On Tue, Apr 19, 2011 at 2:27 PM, nathan binkert n...@binkert.org wrote:
I love that you guys want to fix this. Can we agree on the immediate
fix so it's no longer broken and then
Yes, Steve's got it right. In the C++ you replace the instances of the 3
lengths Nate mentions with a single var (that can be more aptly named as
Steve wants) that is pythonically calculated and passed in from the
configuration. I'm making up words here :).
I think I can do this tonight or
I'm not sure I understand what the problem is either. Can different
VectorStats not have different lengths?
Lisa
On Mon, Apr 18, 2011 at 11:43 AM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
My first reaction is let's fix it, but I don't really understand the
problem or the impact of
I don't have anything definitive about Ruby vs. M5 stats, but until there is
anything definitive, I use both depending on what I'm trying to do.
I've added my own M5 stats to the Ruby Caches because I know those stats
much better, but I've also looked at existing Ruby stats when I know they
around it. C++ only gets angry if you have a variable that's never used.
Lisa
On Thu, Mar 31, 2011 at 7:46 PM, Nilay ni...@cs.wisc.edu wrote:
Lisa, should not compiler yell in this case as well?
Nilay
On Thu, March 31, 2011 8:22 pm, Lisa Hsu wrote:
changeset c7302d55d644 in /z/repo/m5
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On 2011-03-17 16:07:17, Lisa Hsu wrote:
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(Updated 2011-03-17 16:07:17
On 2011-03-17 16:07:08, Lisa Hsu wrote:
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(Updated 2011-03-17 16:07:08
On 2011-03-17 16:06:30, Lisa Hsu wrote:
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-03-17 16:06:13, Lisa Hsu wrote:
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(Updated 2011-03-17 16:06:13)
Review
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changeset 99428f716e7b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=99428f716e7b
description:
Ruby: Bug in SLICC forgot semicolon at end of code.
diffstat:
src/mem/slicc/symbols/StateMachine.py | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diffs (12
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(Updated 2011
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(Updated 2011-03-31 14:13:38.794443)
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Review request for Default, Ali Saidi, Gabe
12:20:53, Lisa Hsu wrote:
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(Updated 2011-03-31 12:20:53)
Review request
/#review1069
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On 2011-03-31 12:20:53, Lisa Hsu wrote:
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some. Thanks!
- Lisa
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On 2011-03-31 12:21:07, Lisa Hsu wrote
changeset 20dbef14192d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=20dbef14192d
description:
Ruby: pass Packet-Req-contextId() to Ruby.
It is useful for Ruby to understand from whence request packets came.
This has all request packets going into Ruby
changeset d5ad24eb015f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d5ad24eb015f
description:
Ruby: enable multiple sequencers in one controller.
diffstat:
src/mem/slicc/symbols/StateMachine.py | 21 +
1 files changed, 13 insertions(+), 8
changeset 8c68155aac00 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8c68155aac00
description:
Ruby: have the rubytester pass contextId to Ruby.
diffstat:
src/cpu/testers/rubytest/Check.cc | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diffs (27 lines):
; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Lisa Hsu
changeset be38f7b6ad9e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=be38f7b6ad9e
description:
Ruby: Simplify SLICC and Entry/TBE handling.
Before this changeset, all local variables of type Entry and TBE were
considered
to be pointers, but an
. I
didn't get too creative here.
- Lisa
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On 2011-03-31 12:21:22, Lisa
? Maybe there is a way to set some attribute on the
variable that the compiler can understand. I have no idea if that is
actually possible and if any solution would be portable across compiler
generations. I'm just curious if there was some way to avoid the code
duplication.
Lisa Hsu
changeset c7302d55d644 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c7302d55d644
description:
CacheMemory: add allocateVoid() that is == allocate() but no return
value.
This function duplicates the functionality of allocate() exactly,
except that it does not
I think you forgot the attachments :P.
Sometimes, if ProtocolTrace isn't enough for me to find a problem, I turn on
RubySlicc and RubyGenerated as well. RubySlicc is the DPRINTFs within the
actual protocol *.sm files, and RubyGenerated are inside of the generated
code that you will only see in
Malek,
TimingSimpleCPUs are in-order CPU models and only do one instruction at a
time, so coalescing at the CPU won't make any sense, since there will be
nothing to coalesce. Unless you want to do your coalescing further down the
memory hierarchy where you might have multiple accesses from
Hi Malek,
I think the term blocking is confusing because it's really an overloaded
term. There's a distinction is between blocking CPUs and blocking memory
systems, and they are distinct.
As you say below, a TimingCPU is a blocking CPU and only has one outstanding
instruction going at a time.
Yes, that's bizarre, since I was using the same tip, no patches applied.
Don't know what to tell you Arka...since you and Nilay are both in
Wisconsin maybe you can look at the differences in your setups, because so
far it seems like it's just you :P.
Lisa
On Wed, Mar 23, 2011 at 1:55 PM, Nilay
Hi Arka,
My repo it not the current tip, but the tip is Nilay's push removing
CacheMsg, so it's pretty close. I've been running X86_SE_MESI_CMP_directory
with the random tester for maybe 10 or 15 minutes now, and it hasn't died.
Since yours died immediately, I would assume that I won't be able
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On 2011-03-18 16:06:49, Lisa Hsu wrote
.
- Lisa
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On 2011-03-18 16:06:02, Lisa Hsu wrote
---
On 2011-03-18 16:06:35, Lisa Hsu wrote:
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(Updated 2011-03-18 16:06:35
changeset f596091c854d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f596091c854d
description:
se.py: Modify script to make multiprogramming much easier.
Now, instead of --bench benchname, you can do --bench
bench1-bench2-bench3 and it will
set up a
changeset 5cbb0a68dce1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5cbb0a68dce1
description:
enable x86 workloads on se.py
diffstat:
configs/example/se.py | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diffs (22 lines):
diff -r f596091c854d
changeset 89cd8302abd3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=89cd8302abd3
description:
configs: combine ruby_se.py and se.py to avoid all that code duplication
diffstat:
configs/example/ruby_se.py | 170 -
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What's going on with this patch? I don't believe it's been committed but it
seems like it should. I've also got some patches waiting behind this
because they used to touch CacheMsg and I don't want to mess Nilay up, so
I've been waiting to serialize behind this.
Lisa
On Wed, Feb 9, 2011 at
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Yes, you assume right.
On Thu, Mar 17, 2011 at 4:08 PM, nathan binkert n...@binkert.org wrote:
I assume that when you commit these, you'll put a proper message in and
make the author vince (qref -u can set the username)
Nate
On Thu, Mar 17, 2011 at 4:06 PM, Lisa Hsu h...@eecs.umich.edu
changeset 03f7df749b9d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=03f7df749b9d
description:
Ruby: expose a simple mod function in slicc interface.
diffstat:
src/mem/protocol/RubySlicc_Util.sm | 2 +-
src/mem/ruby/slicc_interface/RubySlicc_Util.hh |
changeset b0ecadb07742 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b0ecadb07742
description:
Ruby: minor bugfix, line did not adhere to some macro usage conventions.
diffstat:
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh | 2 +-
1 files changed, 1
changeset 60051d2262c2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=60051d2262c2
description:
Import changeset
diffstat:
system/alpha/console/Makefile|44 +
system/alpha/console/console.c | 1126 +
Agreed.
On Wed, Jan 19, 2011 at 1:50 PM, Ali Saidi sa...@umich.edu wrote:
I would not complain if the build times went up slightly but I didn't need
8GB of RAM to do a -j 6 build. ;)
Ali
On Wed, 19 Jan 2011 09:02:13 -0800, nathan binkert n...@binkert.org
wrote:
I don't think anyone
I think the purpose of libruby was that back in the day GEMS/Ruby was able
to be hooked up to several other drivers like Bochs, and libruby
encapsulated the APIs to be able to talk to these other guys.
Caveat - this is what I recall hearing Brad say, I can't say for sure. But
since I'm going
I have changed the wiki to say that we recommend using the development
repository (over m5-stable), since in practice that really is better.
Lisa
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one
- if neither one works, ask on m5-users
If people followed this approach, then it wouldn't matter nearly as much
which one they started with.
Steve
On Fri, Jan 21, 2011 at 2:50 PM, Lisa Hsu h...@eecs.umich.edu wrote:
I have changed the wiki to say that we recommend using
I just had this break a few checkpoints myself - and it's not a big deal
really because it's easily fixup-able...but I wonder whether you really want
to serialize the size of the physmem - let's say you run a checkpointing run
with physmem N gigs and then you restore with physmem M gigs...I don't
Hi Nilay,
I've been talking with Brad here at work about some of these things so I
will finally jump into the conversation via email. First, great job on this
- this has clearly been a substantial amount of work. I'm impressed.
I've got some comments below.
On Tue, Jan 11, 2011 at 3:46 PM,
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Ship it!
Obviates the need for a different patch I had in my own queue,
I can affirm that the ConfigParser package is super easy to use, and I've
used it to aggregate both ALPHA and X86 checkpoints together arbitrarily to
make new checkpoints. An updater shouldn't be too hard, I've done a fair
amount of fixup along the way in that regard.
I also want to point out I
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Ship it!
Though I'm with Nate on code cleanliness to just use the hash
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Ship it!
- Lisa
On 2011-01-06 16:10:36, Brad Beckmann wrote:
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I don't know about the interrupt device, the but TLB code is good -
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Suggest using %#x instead of %x, otherwise, good.
- Lisa
On 2011-01-06
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Ship it!
Didn't check your logic/math or anything, but looks good...so,
I don't have them either. Usually my phone bings at midnight with a cron
email, now that I think about it, hasn't happened in a bit, and there's
nothing in inbox or spam.
Lisa
On Mon, Jun 28, 2010 at 11:17 PM, nathan binkert n...@binkert.org wrote:
I haven't seen them either. I actually scan
1) I like the idea of putting the init sequence onto the wiki (but including
the call to regStats, which isn't there now because it's not relevant to
this conversation, but would still be helpful).
2) I like the idea of parameterizing instantiate with a checkpoint or not
and then having init()
changeset f98fe16f50ee in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f98fe16f50ee
description:
flags: add comment to avoid future deletions since code appears
redundant.
diffstat:
src/sim/eventq.cc | 13 ++---
1 files changed, 10 insertions(+), 3
changeset 97c34fea328a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=97c34fea328a
description:
flags: Unserializing old checkpoints before the introduction
of the Initialized flag would break, set Initialized for events upon
unserialization.
diffstat:
changeset 669c1d2df752 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=669c1d2df752
description:
Stats: fix dist stat and enable VectorDistStat
diffstat:
src/base/statistics.hh | 23 ++-
src/base/stats/text.cc | 2 +-
2 files changed, 15
A while back I think I made totalInstructions() a virtual function because
it was impl'ed by all the cpus anyway, don't know if that's basically what
you're looking for, functionality-wise.
Lisa
On Mon, May 24, 2010 at 9:20 PM, nathan binkert n...@binkert.org wrote:
There seem to be a few
Korey,
Use myStat[tid].value()
Lisa
On Fri, Mar 5, 2010 at 9:07 AM, Korey Sewell ksew...@umich.edu wrote:
Is there a way to get the run-time value of a stat?
Particularly, I have a vector stats that I am incrementing:
myStat[tid]++.
But, for debugging purposes, I would like to print out
changeset 7732bca47f60 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7732bca47f60
description:
cache stats: account for writebacks and/or device occupancy in the
cache.
Plus, a minor bugfix that neglects to update blk-contextSrc in certain
cases on a cache
.
+#
+# Authors: Lisa Hsu
+
+# Configure the M5 cache hierarchy config in one place
+#
+
+import m5
+from m5.objects import *
+from Caches import *
+
+def config_cache(options, system):
+if options.l2cache:
+system.l2 = L2Cache(size='2MB')
+system.tol2bus = Bus()
+system.l2.cpu_side
These failures are my fault, I've got to check in reference updates.
Lisa
On Wed, Feb 24, 2010 at 12:18 AM, Cron Daemon r...@zizzer.eecs.umich.eduwrote:
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
passed.
*
, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Lisa Hsu
+ */
+
+
+#include mem/cache/tags/cacheset.hh
+
+CacheBlk*
+CacheSet::findBlk(Addr tag) const
+{
+for (int i = 0
changeset 039202aafc0d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=039202aafc0d
description:
stats: this makes some fixes to AverageStat and AverageVector.
Also, make Formulas work on AverageVector. First, Stat::Average (and
thus
changeset ab05e20dc4a7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ab05e20dc4a7
description:
cache: Make caches sharing aware and add occupancy stats.
On the config end, if a shared L2 is created for the system, it is
parameterized to have n sharers
This is because of the push that I've been talking with Timothy Jones about,
he just pushed a fix to it this morning. The bad changeset caused Alpha O3
boot to hang and go on indefinitely.
It occurred to me last night that the runs would just still be going on
zizzer, so I killed 2 instances this
, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Lisa Hsu
from ConfigParser import ConfigParser
import gzip
Shoot, my bad on the breaking. I was so focused on making sure the script
worked correctly that I didn't pay attention to the code changes.
Basically, the script in this changeset will take separate checkpoints and
make them into a single multiprogrammed checkpoint, tested and used on ALPHA
changeset 2980bd04e6df in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2980bd04e6df
description:
util: do checkpoint aggregation more cleanly, fix last changeset.
1) Move alpha-specific code out of page_table.cc:serialize().
2) Begin serializing M5_pid
Sorry about that, I'll remember next time.
Lisa
On Mon, Jan 18, 2010 at 5:21 PM, nathan binkert n...@binkert.org wrote:
description:
cache: make tags-insertBlock() and tags-accessBlock() context
aware so that the cache can make context-specific decisions within their
various tag
Of Derek Hower
Sent: Wednesday, December 02, 2009 2:48 PM
To: M5 Developer List
Subject: Re: [m5-dev] Sequencer Usage of the AbstractController Pointer
Sorry I've been flying all day.
I of course will second:
Go Devils!!
-Derek
On Dec 2, 2009, at 12:13 PM, Lisa Hsu h...@eecs.umich.edu
I just have to say - sorry Brad, but Go Blue Devils!
Lisa
I know this is spam for most of you, sorry. But this is very important :).
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Nice catch. This bug was introduced 10/9/08, I'm surprised it didn't come
up until now. I am committing it now.
Thanks.
Lisa
On Tue, Sep 29, 2009 at 2:12 PM, soumyaroop roy s...@cse.usf.edu wrote:
There was a tiny typographical bug in the code due to which
max_insts_all_threads wasn't
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