[EMAIL PROTECTED] is fine with me.
lisa
2008/5/20 Steve Reinhardt [EMAIL PROTECTED]:
OK... if it's just a matter of associating an email with my old bk commits,
then [EMAIL PROTECTED] is the one to use.
Steve
On Tue, May 20, 2008 at 10:24 AM, nathan binkert [EMAIL PROTECTED] wrote:
You
changeset ab3067124402 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ab3067124402
description:
This function declaration isn't used anywhere.
HG: user: Lisa Hsu [EMAIL PROTECTED] HG: branch default HG: changed
src/mem/cache/cache.hh
diffstat:
1 file
changeset 8ba6b8d32aca in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8ba6b8d32aca
description:
Automated merge with ssh://daystrom.m5sim.org//z/repo/m5
diffstat:
2 files changed, 1 insertion(+), 1 deletion(-)
src/arch/x86/interrupts.cc |1 -
src/dev/x86/i8259.cc
Is this what you describe, by all means all systems go!
2008/10/24 Lisa Hsu [EMAIL PROTECTED]:
Hi All,
In case you haven't guessed it, I'm hacking on M5 once again. I've
noticed
recently that there is a big hot mess when it comes to identification
mechanisms for CPUs, threads
be tricky to use the
context ID t
index into a vector of thread contexts when the numbering doesn't start
over for
each CPU. Other than that it looks like we're strictly getting closer
to the
right answer at least.
Gabe
Quoting Lisa Hsu [EMAIL PROTECTED]:
yes, that's what i mean
a unique cpuId only within that process.
Lisa
Ali
On Oct 24, 2008, at 6:20 PM, Lisa Hsu wrote:
what do we all like better, cpuID/contextID, or cpuId/contextId?
lisa
On Fri, Oct 24, 2008 at 6:07 PM, nathan binkert [EMAIL PROTECTED]
wrote:
The BIOS identifies all of the CPUs to the OS
changeset 6ed48cba2217 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6ed48cba2217
description:
decouple eviction from insertion in the cache.
diffstat:
4 files changed, 6 insertions(+), 6 deletions(-)
src/mem/cache/tags/fa_lru.hh |2 +-
src/mem/cache/tags/iic.hh
changeset 76abee886def in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=76abee886def
description:
Add in Context IDs to the simulator. From now on, cpuId is almost
never used,
the primary identifier for a hardware context should be contextId().
The
changeset e8c1d4e669a7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e8c1d4e669a7
description:
get rid of all instances of readTid() and getThreadNum(). Unify and
eliminate
redundancies with threadId() as their replacement.
diffstat:
5 files changed, 5
changeset ee56bb539212 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ee56bb539212
description:
Change the findBlock(addr, lat) to accessBlock, which I think has
better connotations for what is really happening and how it should be used.
diffstat:
3 files changed, 11
changeset 993c7952b930 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=993c7952b930
description:
Make it so that all thread contexts are registered with the System,
even in
SE. Process still keeps track of the tc's it owns, but registration
occurs
with
Hey guys,
I'm trying to run a timing CMP with caches using EIO traces, but the EIO
can't seem to be run on multicore platforms, the 2nd cpu inevitably itb
pagefaults continually on a single PC (presumably the first) and then dies.
Is this a bug or a feature? Is there something I don't know
changeset 199d31b47f7b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=199d31b47f7b
description:
make BaseCPU the provider of _cpuId, and cpuId() instead of being
scattered
across the subclasses. generally make it so that member data is _cpuId
and
It happens in AlphaLiveProcess. I had the inclination that EIO is only
Alpha capable, I think I saw it on our wiki. Is that inherent or just the
way it is because we just don't have it for something else? I'm not sure
we'll develop eio for non-alpha anyway. But if people object, let me know,
I
changeset 323cfbfec1a4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=323cfbfec1a4
description:
Right now a single thread cpu 1 could get assigned context Id != 1,
depending
on the order in which it's registered with the system. To make them
match,
changeset 11e6f4fa85c3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=11e6f4fa85c3
description:
new mp eio test
diffstat:
10 files changed, 1243 insertions(+), 1 deletion(-)
tests/SConscript |1
changeset 8d96bbe4cc84 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8d96bbe4cc84
description:
Automated merge with ssh://m5sim.org//repo/m5
diffstat:
0 files changed
diffs (24 lines):
diff -r 11e6f4fa85c3 -r 8d96bbe4cc84 src/arch/sparc/ua2005.cc
---
changeset c36087d4573d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c36087d4573d
description:
Reference updates. Since split cache is gone, a lot of config.ini
changes, and minor changes to stats that are likely due to the decoupling of
insertions/evictions in the
changeset f693fcdd4aa5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f693fcdd4aa5
description:
Automated merge with ssh://daystrom.m5sim.org//repo/m5
diffstat:
140 files changed, 65 insertions(+), 526 deletions(-)
I prefer Nate's way too - members be _member, and accessor be member().
I half did this with my contextId()/cpuId()/threadId() changes just now. my
set functions were still prepended with set though, didn't think of
overloading.
Anyway, point is, I'm down.
Lisa
On Thu, Nov 6, 2008 at 2:16 PM,
i stick to that rule too, and i like it as well. it's not that hard, and
when followed, makes for easier coding, you can be sure that you're
affecting the class var you want, instead of a random local var. i totally
vote to stick with the rule, and *actually following it* :).
lisa
On Sun, Nov
i would imagine you need to do patch -p1, not -p0. what errors do you get
when your patching fails?
lisa
On Sun, Nov 30, 2008 at 4:25 PM, Korey Sewell [EMAIL PROTECTED] wrote:
i'm having a problem with my repository as I was trying to fix a bug
that was stalling Mixie...
basically, i
changeset 9c3edb28db1a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9c3edb28db1a
description:
This patch pulls out the auxiliary vector struct from individual ISA
LiveProcesses to the base LiveProcess definition so anyone can use them.
diffstat:
5 files
changeset 8aad0d60e7ab in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8aad0d60e7ab
description:
Automated merge with ssh://m5sim.org//repo/m5
diffstat:
84 files changed, 149 insertions(+), 396 deletions(-)
src/arch/alpha/process.cc
I always forget to pull before i convert a patch to a changeset, hence the
merge. bah.
On Fri, Dec 5, 2008 at 12:15 PM, Lisa Hsu [EMAIL PROTECTED] wrote:
changeset 8aad0d60e7ab in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8aad0d60e7ab
description:
Automated
by different
names.
- I'd prefer a more M5-ish name like AuxVector... I realize we're
shadowing the canonical auxv_t struct but the current name just looks
very awkward to me.
Steve
On Fri, Dec 5, 2008 at 9:15 AM, Lisa Hsu [EMAIL PROTECTED] wrote:
changeset 9c3edb28db1a in /z/repo/m5
Anyone do this lately? It appears to be broken. Whether restoring directly
into O3 or using the --standard-switch, both die. In the former case it's
because there are no activeThreads, and in the 2nd because it appears the O3
cpu is getting recvAtomic callbacks before the switchover has even
appears to be legit, I'm getting
the same CountedDrain error he is.
Lisa
On Fri, Dec 12, 2008 at 3:35 PM, Lisa Hsu h...@eecs.umich.edu wrote:
Anyone do this lately? It appears to be broken. Whether restoring
directly into O3 or using the --standard-switch, both die. In the former
case it's
to
look.
Ali
On Dec 12, 2008, at 3:59 PM, Lisa Hsu wrote:
The former case is still broken (were were ever supposed to be able
to restore directly to O3? i can't remember).
The latter was my fault, i added a new cache option that was not
caught by all the if not options.caches
Your description that it only occurs when you switch to a timing sim makes
me think of this (not to toot my own horn or anything):
http://www.eecs.umich.edu/~hsul/pubs/mobs05.pdf
Just throwing that out as a possibility. You might want to slow down your
checkpoint dropping run so that it's not
Rick,
1) Just to follow up, did you figure out a good speed for the checkpoint
producing run?
2) Did you ever find why everything was 404'ed?
Lisa
On Wed, Jan 28, 2009 at 9:44 PM, Lisa Hsu h...@eecs.umich.edu wrote:
I couldn't say exactly, so much in M5 has changed since that paper to give
of a problem. I
added a specweb-fileset disk to my sim and my 404's went away. I poked
around our images, old and new, and saw no references at all to a
mod_specweb99.so, so I don't know what that was about.
Lisa
On Wed, Feb 4, 2009 at 5:09 PM, Rick Strong rstr...@cs.ucsd.edu wrote:
Lisa Hsu wrote
changeset 9fe574944f31 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9fe574944f31
description:
sycalls: implement mremap() and add DATA flag for getrlimit(). mremap
has been tested on Alpha, compiles for the rest but not tested. I don't see why
it wouldn't work
hey guys,
i just pushed something and haven't gotten an email notification - has
anyone else?
lisa
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in the spam filter so you might want to check in your
junk folder.
Gabe
Lisa Hsu wrote:
hey guys,
i just pushed something and haven't gotten an email notification - has
anyone else?
lisa
at 4:23 PM, Ali Saidi sa...@umich.edu wrote:
Maybe one of the pool nodes is broken? All the nodes are busy right
now, so I couldn't really try...
Ali
On Apr 13, 2009, at 2:22 PM, Lisa Hsu wrote:
Anyone have a clue why this might be?
Yesterday's message indicated:
Error: can't find
present is
enough though...
On Fri, Apr 17, 2009 at 9:32 AM, Lisa Hsu h...@eecs.umich.edu wrote:
m5.opt --trace-help
that will list all available trace flags, including composite ones.
m5.opt
-h will give a big usage blurb too, so that you can see if you want is
available.
Lisa
On Fri
want a per-configuration relevant trace flag listing so
nothing slips under the cracks when I'm trying to debug something.
Maybe that's specific to how I want to use M5 so I could see why
people think the *All Flags are sufficient.
On Fri, Apr 17, 2009 at 11:50 AM, Lisa Hsu h...@eecs.umich.edu
Oh, definitely not a commit of KoreysO3, that would obviously have to stay
in one's patch tree...but a reasonable commit with a reasonable name that is
usedul - I think wouldn't be so bad.
Lisa
On Fri, Apr 17, 2009 at 1:35 PM, nathan binkert n...@binkert.org wrote:
I'm not sure what you mean.
No, we don't support that. O3 is too complicated, has too much state to
checkpoint, so we only checkpoint and restore AtomicCPU, then move into the
desired CPU model post-checkpoint.
On Fri, Apr 17, 2009 at 7:26 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Quoting Steve Reinhardt
Ah, now I get what you are saying, you want automatic context-specific flags
to be turned on with a single catch-all flag. It's hard to say, on the one
hand yes, that could be totally useful, but on the other, it's likely to be
so noisy that it sifting through the noise eliminates its utility.
I also like this idea. It makes sense to put our types in one place, I
remember trying to fine the actual definition of various typedefs for things
like Tick and Counter in the old days.
Lisa
On Sat, May 16, 2009 at 1:14 AM, Steve Reinhardt ste...@gmail.com wrote:
This all sounds great to me.
anyone get this?
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Just an FYI, I don't believe 3dNow! is supported anymore; at least, Rev 3.14
of the 1st volume says:
AMD no longer recommends the use of 3DNow! insts, which have been
superceded by their more efficient 128-bit media counterparts.
So I wouldn't do anything special to support them.
Lisa
On Sat,
Sorry, but I absolutely do not... Have to mail my thesis to Rackham on
Wed! It's very exciting.
Lisa
On Fri, Sep 11, 2009 at 11:24 AM, nathan binkert n...@binkert.org wrote:
Those are still broken on zizzer, by the way. We should really fix those
soon so we don't discover a big mess
Nice catch. This bug was introduced 10/9/08, I'm surprised it didn't come
up until now. I am committing it now.
Thanks.
Lisa
On Tue, Sep 29, 2009 at 2:12 PM, soumyaroop roy s...@cse.usf.edu wrote:
There was a tiny typographical bug in the code due to which
max_insts_all_threads wasn't
changeset 81e6aa93bc6a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=81e6aa93bc6a
description:
commit Soumyaroop's bug catch about max_insts_all_threads
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/cpu/base.cc |2 +-
diffs (12 lines):
diff -r
this. In the future, when committing a change
submitted by someone else, please make them the author. Commit has a
-u option, e.g.
hg commit -u Soymyaroop Roy s...@cse.usf.edu
incidentally, qnew and qref also support -u
Thanks,
Nate
On Tue, Sep 29, 2009 at 3:01 PM, Lisa Hsu h...@eecs.umich.edu wrote
I just have to say - sorry Brad, but Go Blue Devils!
Lisa
I know this is spam for most of you, sorry. But this is very important :).
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Of Derek Hower
Sent: Wednesday, December 02, 2009 2:48 PM
To: M5 Developer List
Subject: Re: [m5-dev] Sequencer Usage of the AbstractController Pointer
Sorry I've been flying all day.
I of course will second:
Go Devils!!
-Derek
On Dec 2, 2009, at 12:13 PM, Lisa Hsu h...@eecs.umich.edu
Sorry about that, I'll remember next time.
Lisa
On Mon, Jan 18, 2010 at 5:21 PM, nathan binkert n...@binkert.org wrote:
description:
cache: make tags-insertBlock() and tags-accessBlock() context
aware so that the cache can make context-specific decisions within their
various tag
Shoot, my bad on the breaking. I was so focused on making sure the script
worked correctly that I didn't pay attention to the code changes.
Basically, the script in this changeset will take separate checkpoints and
make them into a single multiprogrammed checkpoint, tested and used on ALPHA
changeset 2980bd04e6df in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2980bd04e6df
description:
util: do checkpoint aggregation more cleanly, fix last changeset.
1) Move alpha-specific code out of page_table.cc:serialize().
2) Begin serializing M5_pid
, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Lisa Hsu
from ConfigParser import ConfigParser
import gzip
This is because of the push that I've been talking with Timothy Jones about,
he just pushed a fix to it this morning. The bad changeset caused Alpha O3
boot to hang and go on indefinitely.
It occurred to me last night that the runs would just still be going on
zizzer, so I killed 2 instances this
, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Lisa Hsu
+ */
+
+
+#include mem/cache/tags/cacheset.hh
+
+CacheBlk*
+CacheSet::findBlk(Addr tag) const
+{
+for (int i = 0
changeset 039202aafc0d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=039202aafc0d
description:
stats: this makes some fixes to AverageStat and AverageVector.
Also, make Formulas work on AverageVector. First, Stat::Average (and
thus
changeset ab05e20dc4a7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ab05e20dc4a7
description:
cache: Make caches sharing aware and add occupancy stats.
On the config end, if a shared L2 is created for the system, it is
parameterized to have n sharers
These failures are my fault, I've got to check in reference updates.
Lisa
On Wed, Feb 24, 2010 at 12:18 AM, Cron Daemon r...@zizzer.eecs.umich.eduwrote:
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
passed.
*
changeset 7732bca47f60 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7732bca47f60
description:
cache stats: account for writebacks and/or device occupancy in the
cache.
Plus, a minor bugfix that neglects to update blk-contextSrc in certain
cases on a cache
.
+#
+# Authors: Lisa Hsu
+
+# Configure the M5 cache hierarchy config in one place
+#
+
+import m5
+from m5.objects import *
+from Caches import *
+
+def config_cache(options, system):
+if options.l2cache:
+system.l2 = L2Cache(size='2MB')
+system.tol2bus = Bus()
+system.l2.cpu_side
Korey,
Use myStat[tid].value()
Lisa
On Fri, Mar 5, 2010 at 9:07 AM, Korey Sewell ksew...@umich.edu wrote:
Is there a way to get the run-time value of a stat?
Particularly, I have a vector stats that I am incrementing:
myStat[tid]++.
But, for debugging purposes, I would like to print out
A while back I think I made totalInstructions() a virtual function because
it was impl'ed by all the cpus anyway, don't know if that's basically what
you're looking for, functionality-wise.
Lisa
On Mon, May 24, 2010 at 9:20 PM, nathan binkert n...@binkert.org wrote:
There seem to be a few
changeset 669c1d2df752 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=669c1d2df752
description:
Stats: fix dist stat and enable VectorDistStat
diffstat:
src/base/statistics.hh | 23 ++-
src/base/stats/text.cc | 2 +-
2 files changed, 15
changeset 97c34fea328a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=97c34fea328a
description:
flags: Unserializing old checkpoints before the introduction
of the Initialized flag would break, set Initialized for events upon
unserialization.
diffstat:
changeset f98fe16f50ee in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f98fe16f50ee
description:
flags: add comment to avoid future deletions since code appears
redundant.
diffstat:
src/sim/eventq.cc | 13 ++---
1 files changed, 10 insertions(+), 3
1) I like the idea of putting the init sequence onto the wiki (but including
the call to regStats, which isn't there now because it's not relevant to
this conversation, but would still be helpful).
2) I like the idea of parameterizing instantiate with a checkpoint or not
and then having init()
I don't have them either. Usually my phone bings at midnight with a cron
email, now that I think about it, hasn't happened in a bit, and there's
nothing in inbox or spam.
Lisa
On Mon, Jun 28, 2010 at 11:17 PM, nathan binkert n...@binkert.org wrote:
I haven't seen them either. I actually scan
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Ship it!
Didn't check your logic/math or anything, but looks good...so,
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Ship it!
Though I'm with Nate on code cleanliness to just use the hash
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Ship it!
- Lisa
On 2011-01-06 16:10:36, Brad Beckmann wrote:
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I don't know about the interrupt device, the but TLB code is good -
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Suggest using %#x instead of %x, otherwise, good.
- Lisa
On 2011-01-06
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Ship it!
Obviates the need for a different patch I had in my own queue,
I can affirm that the ConfigParser package is super easy to use, and I've
used it to aggregate both ALPHA and X86 checkpoints together arbitrarily to
make new checkpoints. An updater shouldn't be too hard, I've done a fair
amount of fixup along the way in that regard.
I also want to point out I
I just had this break a few checkpoints myself - and it's not a big deal
really because it's easily fixup-able...but I wonder whether you really want
to serialize the size of the physmem - let's say you run a checkpointing run
with physmem N gigs and then you restore with physmem M gigs...I don't
Hi Nilay,
I've been talking with Brad here at work about some of these things so I
will finally jump into the conversation via email. First, great job on this
- this has clearly been a substantial amount of work. I'm impressed.
I've got some comments below.
On Tue, Jan 11, 2011 at 3:46 PM,
Agreed.
On Wed, Jan 19, 2011 at 1:50 PM, Ali Saidi sa...@umich.edu wrote:
I would not complain if the build times went up slightly but I didn't need
8GB of RAM to do a -j 6 build. ;)
Ali
On Wed, 19 Jan 2011 09:02:13 -0800, nathan binkert n...@binkert.org
wrote:
I don't think anyone
I think the purpose of libruby was that back in the day GEMS/Ruby was able
to be hooked up to several other drivers like Bochs, and libruby
encapsulated the APIs to be able to talk to these other guys.
Caveat - this is what I recall hearing Brad say, I can't say for sure. But
since I'm going
I have changed the wiki to say that we recommend using the development
repository (over m5-stable), since in practice that really is better.
Lisa
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one
- if neither one works, ask on m5-users
If people followed this approach, then it wouldn't matter nearly as much
which one they started with.
Steve
On Fri, Jan 21, 2011 at 2:50 PM, Lisa Hsu h...@eecs.umich.edu wrote:
I have changed the wiki to say that we recommend using
changeset 60051d2262c2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=60051d2262c2
description:
Import changeset
diffstat:
system/alpha/console/Makefile|44 +
system/alpha/console/console.c | 1126 +
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Yes, you assume right.
On Thu, Mar 17, 2011 at 4:08 PM, nathan binkert n...@binkert.org wrote:
I assume that when you commit these, you'll put a proper message in and
make the author vince (qref -u can set the username)
Nate
On Thu, Mar 17, 2011 at 4:06 PM, Lisa Hsu h...@eecs.umich.edu
changeset 03f7df749b9d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=03f7df749b9d
description:
Ruby: expose a simple mod function in slicc interface.
diffstat:
src/mem/protocol/RubySlicc_Util.sm | 2 +-
src/mem/ruby/slicc_interface/RubySlicc_Util.hh |
changeset b0ecadb07742 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b0ecadb07742
description:
Ruby: minor bugfix, line did not adhere to some macro usage conventions.
diffstat:
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh | 2 +-
1 files changed, 1
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This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/598/
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
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This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/599/
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
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http://reviews.m5sim.org/r/600/
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
What's going on with this patch? I don't believe it's been committed but it
seems like it should. I've also got some patches waiting behind this
because they used to touch CacheMsg and I don't want to mess Nilay up, so
I've been waiting to serialize behind this.
Lisa
On Wed, Feb 9, 2011 at
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On 2011-03-18 16:06:49, Lisa Hsu wrote
.
- Lisa
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On 2011-03-18 16:06:02, Lisa Hsu wrote
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On 2011-03-18 16:06:35, Lisa Hsu wrote:
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(Updated 2011-03-18 16:06:35
changeset f596091c854d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f596091c854d
description:
se.py: Modify script to make multiprogramming much easier.
Now, instead of --bench benchname, you can do --bench
bench1-bench2-bench3 and it will
set up a
changeset 5cbb0a68dce1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5cbb0a68dce1
description:
enable x86 workloads on se.py
diffstat:
configs/example/se.py | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diffs (22 lines):
diff -r f596091c854d
1 - 100 of 147 matches
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