I did some investigation on the CH32V series. It seems that they have their own
custom protocol completely unrelated to ARM SWD. I have seen it referred to as
RVSWD. To complicate things even further, their CH32V003 uses a different
single transport protocol.
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**[tickets:#378] SWD support
> I have came across custom SOCs where there is a single ARM Coresight DAP and
> a riscv processor connected on APB bus on a particular APB port.
> Example SOC: https://www.nordicsemi.com/Products/nRF54H20 - This is with
> combination of ARM and RISCV core on an SOC.
Ashi, does the first statem
Example SOC: https://www.nordicsemi.com/Products/nRF54H20 - This is with
combination of ARM and RISCV core on an SOC.
CH32V seems to be a RISCV based SOC only.
For SOC having combination of ARM and RISCV or any other peripheral connected
on APB bus, ARM being a primary debug chip is accessible
> I have came across custom SOCs where there is a single ARM Coresight DAP and
> a riscv processor connected on APB bus on a particular APB port.
Do you happen to mean the WCH CH32VXXX MCUs by any chance? If so then maybe
this is of relevance?
* https://github.com/fxsheep/openocd_wchlink-rv/iss
Though this is a off-topic. I have got some queries hence posting
I have came across custom SOCs where there is a single ARM Coresight DAP and a
riscv processor connected on APB bus on a particular APB port.
ARM debug can be achieved using openocd, any idea on how riscv debug can be
achieved he
Interesting development.
I was looking at the pin out on the tweet to see whether it use JTAG or SWD.
All I can find is USB, so no guidance there. Either signals can be routed
through USB I believe. I know JTAG can, but my limited knowledge means I am not
sure about SWD.
From: Antonio Borneo
HI Antonio,
With reference to your second point,
"[A] single JTAG/SWD TAP based on ARM CoreSight DAP. One of the AP (access
ports) could be a JTAG-AP where the debug of the RISC-V core gets accessible.
(today OpenOCD does not support JTAG-AP yet)"
This is an interesting idea, and certainly pos
ickets] Re: #378 SWD support for RISCV artchitecture
FWIW, Some Microchip FPGAs/SoC FPGAs can support hard and/or soft IP Cortex-M
and RISC-V CPUs. But my recollection (from working for Microchip in the past)
is that neither supported SWD. Certainly there is no SWD debug access to t
ickets] Re: #378 SWD support for RISCV artchitecture
FWIW, Some Microchip FPGAs/SoC FPGAs can support hard and/or soft IP Cortex-M
and RISC-V CPUs. But my recollection (from working for Microchip in the past)
is that neither supported SWD. Certainly there is no SWD debug access to t
FWIW, Some Microchip FPGAs/SoC FPGAs can support hard and/or soft IP Cortex-M
and RISC-V CPUs. But my recollection (from working for Microchip in the past)
is that neither supported SWD. Certainly there is no SWD debug access to the
RISC-V.
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** [tickets:#378] SWD support for RISCV artchite
That seems to be about using ESP32 as an SWD debug interface.
Not about debugging ESP32 using SWD.
And nothing there is obviously about the RISC-V based ESP32-C3.
As such, I don't see its relevance in this thread?
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** [tickets:#378] SWD support for RISCV artchitecture**
**Status:** new
**Mil
You mean ESP32-C3?
I don't think so.
As far as I can see it only has JTAG.
https://www.espressif.com/en/products/socs/esp32-c3
---
** [tickets:#378] SWD support for RISCV artchitecture**
**Status:** new
**Milestone:** 0.10.0
**Labels:** openocd
**Created:** Wed Dec 28, 2022 07:00 AM UTC by As
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