Greetings Folks,
I would like to thank Ted for his kind offer. I think that there are
more like me who would rather take cover from the bad vibes
echoing in the PEDA at present. Maybe we remind ourselves what
is the purpose of this group.
Thanking all for the information that I have got out
I find the personal remarks rather amusing. It helps me get thru the day.
It becomes my daily dose of Dilbert office polictics.
Mike Reagan
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Can anyone tell me how to change the default text height, line-width, etc.,
that the autoplacer uses when loading components to the PCB from the Load
Nets option? It doesn't seem to use the same values stored for the
component primitives. The primitives definitions seem to work fine for
For validation, on the PCB side, I used to place a 'scanned version' in
a translucent state, of the part over the footprint. I've been able to find
and correct many footprint problems in advance using this technique. If
such an ability was built into Protel a copy of the scan was kept with
That is a good question. I haven't been able to figure it out either. I've
resorted to just using the heck out of the global change feature.
Brad
Tim Hutcheson wrote:
Can anyone tell me how to change the default text height, line-width, etc.,
that the autoplacer uses when loading components
ensure that the xtal and its associated decoupling caps are as close as
possible to the processor clock pins.
Put ground planes around it on top /bottom layers and locally stitch top /
bottom planes with as many vias as you can fit in (I tend to use 1mm via /
0.5mm hole for this)
You may also
What I do is lay a ground (polygon plane) plane directly underneath the crystal and
surrounding components. This plane is additional to the ground plane on the internal
layer. So the polygon is on the same layer as the component. Also, very close
placement to the processor on the same side,
Make sure that the ground side of the decoupling caps for the crystal go straight
to the GND of the processor with as thick a
trace as possible. Preferably a polygon fill throughout the processor crystal area.
If you are using just a normal trace here,
believe it or not, you may have
On 08:35 AM 7/26/2001 -0400, Mike Reagan wrote:
Does anyone know if 99SE has some upper limit to the size file it can
export to dsn?
I don't personally, but...
At a guess, Ian Wilson, Geoff Harland, or Protel CSC are the parties who can best
answer your question. I forwarded the query to
That's it, I will now make a ClientBasic program which will create perfect footprints
based on the measurements which are actually
in the data sheets. It will create dual quad flat packs.
I need to know who's IC package data sheets would be best to work with as reference.
Does ClientBasic
What does your operating environment look like when you encounter the
problem?
Thanks AJ,
Good point.
I somehow suspected that the dsn file might be trying to use MS notepad or
write and that may be what is clobbering the dsn file. Both which have size
limitations
Mike Reagan
EDSI
Frederick
i would agree with steve's comments here
sometime i have spent longer looking for a footprint than it would take
to make one (simple ones only that is)
also it is true that they can and sometimes should be slanted to the
project at hand
sch parts, however, don't strike me as being hard at all
Hello Protel Debaters (just kidding),
Does anyone know how to setup MS Word as the text editor and MS Excel for
.cvs files? Is it worth it or should I just export the files and then open
them in Word and Excel.
I like the print preview, etc. of Word and I like Excel for BOMs (easier to
sort,
At 03:06 PM 7/26/01 -0400, chris mackensen wrote:
because
cadence's files are all OPEN and TEXT based and NOT ENCAPSULATED in a
DATABASE (and NOT BINARY), it was a matter of my perl script just parsing
Excel sheets of pin data (automatically saved as text files over the web)
and generating the
WOW! What a melee!
I am Pentium of Borg. Division is futile. You will be approximated.
(origin unknown)
Is this approximating a constructive process? If so, it's off by several
orders of magnitude.
Seriously, I cast my vote (if I have one) for the following:
1) website-hosted
It should be noted that the Protel ASCII format is not only text based,
but
it is self-documenting. All the records and fields are named wherever they
occur. The library format is binary only, but one could import parts to a
PCB file and then create a library from the PCB file.
True, but I
I believe CDs only have a finite life also. Does anyone know how long?
PS: Ivan, what was the sci fi book :-)?
Colin Weber
Varian Australia P/L
At 05:14 PM 26/07/2001 -0400, you wrote:
It should be noted that the Protel ASCII format is not only text based,
but
it is self-documenting. All
Jon has many good points on Greg's problem. After the fact, what one
presumes as square waves is not often the case since edges are never
perfectly square. I have seen so called linear RF amps produce -30 dBc and
-10 dBc second and third order products in my time.
EMI is a real problem when
I believe CDs only have a finite life also. Does anyone know how long?
The number I have heard mentioned is 10-20 years for writable optical media,
and 50-100 years for stamped optical media. Of course, no one knows for
sure because these technologies aren't that old yet.
But for magnetic
Try Anam Amkor, a company which sources a lot of package types to manufacturers.
http://www.amkor.com/products/ProductFamilies.cfm
___
Clive Broome
IDT Sydney Design CentrePh: +61 2 9763 3513
8 Bayswater Dr,
I looked at their data sheets. They do not include mechanical drawings.
I'm thinking I'll works with the mechanical data sheets from Altera, Micron, Sharp,
National.
The goal is to make a script, or wizard which will take the few important
measurements from the data sheets mechanical section,
I've also noticed that after building relatively complex footprints, such as
ball escapes for BGA devices with the escape track routing added and
modified over time, when I drag these parts around I notice little bits of
copper from tracks that no longer seem to be part of the library part!!! So
I've also noticed that after building relatively complex footprints, such
as
ball escapes for BGA devices with the escape track routing added and
modified over time, when I drag these parts around I notice little bits of
copper from tracks that no longer seem to be part of the library part!!!
Check that the template you're using doesn't contain references
to bitmaps that are on a slow network!
I ran into this problem when I was last in the USA - I had a local
copy of my design database, however the template included a bitmap
of the company logo which was referenced directly back to
I agree, especially with point 2
Brad
Brad Shea
Senior PCB Designer
PowerSearch Ltd
121 Ewing St
Welshpool WA 6106
Australia
email:[EMAIL PROTECTED]
Phone: (08) 9358 3633
Fax: (08) 9358 3644
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