Module Name:src
Committed By: jmcneill
Date: Tue Aug 10 17:12:31 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: files.cortex gic.c gicv3.c
Log Message:
Make gic_splfuncs optional and disable it by default until it has had
more testing.
To generate a diff of this
Module Name:src
Committed By: jmcneill
Date: Tue Aug 10 15:33:09 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: files.cortex gic.c gicv3.c
Added Files:
src/sys/arch/arm/cortex: gic_splfuncs.c gic_splfuncs.h
Log Message:
Use custom spl funcs for GIC and avoid
Module Name:src
Committed By: jmcneill
Date: Sun Mar 28 11:13:24 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Disable 1ofN distribution of SPIs by default. This is a workaround for an
issue in the USB stack -- signaling transfer complete on
Module Name:src
Committed By: skrll
Date: Sun Mar 28 09:11:38 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Only target the boot cpu for real with SPI interrupts. I tried to do
this back in 2014, but somehow I missed a spot.
This is a
Module Name:src
Committed By: skrll
Date: Sun Mar 14 08:09:20 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c
Log Message:
Remove an unnecessary if statement in gic_v2m_msi_alloc when finding a
'count' that fits the available.
To generate a diff of this
Module Name:src
Committed By: jmcneill
Date: Tue Feb 23 10:03:05 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c gicv3.c
Log Message:
If we are committing a deferred splhigh() to hardware, no need to continue.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: jmcneill
Date: Sun Feb 21 15:45:30 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Apply PMR optimizations from gicv3
To generate a diff of this commit:
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/cortex/gic.c
Please
Module Name:src
Committed By: ryo
Date: Tue Feb 9 17:44:01 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
fix build without MULTIPROCESSOR
To generate a diff of this commit:
cvs rdiff -u -r1.40 -r1.41 src/sys/arch/arm/cortex/gicv3.c
Please note
Module Name:src
Committed By: jakllsch
Date: Tue Feb 9 14:24:14 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Avoid an extra daif read when dispatching interrupts by using
ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid()
Module Name:src
Committed By: jmcneill
Date: Sun Feb 7 21:24:50 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Optimize hardware priority updates.
In gicv3_set_priority, read the current priority mask and only update it
if we are lowering the
Module Name:src
Committed By: jmcneill
Date: Mon Jan 18 23:43:35 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Fix a comment
To generate a diff of this commit:
cvs rdiff -u -r1.42 -r1.43 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are
Module Name:src
Committed By: jmcneill
Date: Sat Jan 16 21:05:15 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h gicv3_its.c gicv3_its.h
Log Message:
Remove MAXCPUS dependency.
To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39
Module Name:src
Committed By: jmcneill
Date: Thu Dec 24 14:44:49 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/arm/cortex/gicv3_its.c
Please note
Module Name:src
Committed By: jmcneill
Date: Tue Dec 22 10:46:51 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
When lpiconf flushing is required, make sure to flush to PoC and not PoU.
Spotted by nick.
To generate a diff of this commit:
cvs
Module Name:src
Committed By: jmcneill
Date: Fri Dec 11 22:42:31 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Simplify gits_command by getting rid of the _BYTE_ORDER test and just
always use the loop + htole64 path.
To generate a diff of
Module Name:src
Committed By: jmcneill
Date: Fri Dec 11 21:40:50 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c gicv3_its.c
Log Message:
Preserve ST Lower and Upper fields when clearing Mask bit in the MSI-X
vector control register.
To generate a diff of
Module Name:src
Committed By: jmcneill
Date: Fri Dec 11 21:22:37 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Fix spelling in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/arm/cortex/gicv3.c
Please note
Module Name:src
Committed By: jmcneill
Date: Fri Dec 4 21:39:26 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h
Log Message:
gicv3: Only use 1 of N SPI distribution when the feature is available.
A GICv3+ implementation is not guaranteed to support 1
Module Name:src
Committed By: skrll
Date: Sat Nov 28 14:29:02 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: armperiph.c
Log Message:
Fix build
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/cortex/armperiph.c
Please note that diffs
Module Name:src
Committed By: jmcneill
Date: Sun Nov 22 20:17:39 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Fix interrupt priorities on N1 SDP.
The GICv3 architecture specification is not clear on the NS view of
priority registers, and there
Module Name:src
Committed By: jmcneill
Date: Sun Nov 22 19:53:48 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gic_reg.h
Log Message:
Add GICD_CTRL_EnableGrp1S definition.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12
Module Name:src
Committed By: jmcneill
Date: Sun Nov 1 14:30:12 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
sc_enabled_sgippi can be updated from any CPU, so use atomic_or/atomic_and
To generate a diff of this commit:
cvs rdiff -u -r1.31
Module Name:src
Committed By: jmcneill
Date: Sun Nov 1 14:19:42 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Remove unused __HAVE_PIC_FAST_SOFTINTS block. It never would have worked
if enabled..
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: jmcneill
Date: Sun Nov 1 12:13:21 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Add an isb() barrier after ICC_SGI1R_EL1 write to prevent reordering with
subsequent wfi/wfe instructions. Haven't seen this in practice
Module Name:src
Committed By: jmcneill
Date: Sun Nov 1 11:17:20 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
gicv3_set_priority: ICC_PMR_EL1 is self-synchronizing so no need for isb()
here.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: jmcneill
Date: Sun Nov 1 11:04:55 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
gicv3_irq_handler: No need to call gicv3_set_priority if we are already at
the desired ipl.
To generate a diff of this commit:
cvs
Module Name:src
Committed By: jmcneill
Date: Sun Nov 1 11:03:44 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
gicv3_ipi_send: simplify logic in kcp != NULL case given that we know that
the kcpuset will only ever contain one cpu.
To generate a
Module Name:src
Committed By: ryo
Date: Thu Sep 24 08:50:09 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
need to swap on big endian machines.
"The ITS command queue uses a little endian memory order model." (GIC
Architecture Specification)
Module Name:src
Committed By: jmcneill
Date: Mon Jul 27 18:36:23 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Remove CPU ID test in armgic_match. Perfectly normal to have GIC in
non-Cortex cores.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: skrll
Date: Sun Jul 12 13:33:44 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Avoid undefined behaviour. Detected by KUBSAN.
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gic.c
Module Name:src
Committed By: jmcneill
Date: Thu May 7 16:20:40 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c gic_v2m.h
Log Message:
Do not store a pointer to the passed in struct pci_attach_args
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9
Module Name:src
Committed By: jmcneill
Date: Mon Apr 13 12:14:56 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Apply similar fix from gic.c that fixed "left shift of 255 by 24 places
cannot be represented in type 'int'" warnings from UBSan.
To
Module Name:src
Committed By: jmcneill
Date: Mon Apr 13 12:14:04 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Fix "left shift of 255 by 24 places cannot be represented in type 'int'"
warning from UBSan.
To generate a diff of this commit:
cvs
Module Name:src
Committed By: jmcneill
Date: Thu Feb 13 02:12:07 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3_its.c
Log Message:
Make intr affinity work with MSIs again
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24
Module Name:src
Committed By: jmcneill
Date: Thu Feb 13 00:42:59 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h gicv3_its.c
Log Message:
Since all ITS instances share a common LPI configuration table, used a
shared vmem arena to allocate pic irqs. Idea
Module Name:src
Committed By: jmcneill
Date: Sat Feb 1 15:33:48 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Use kmem_zalloc for its state, fixes possible crash if a driver tries to
set affinity before a CPU is online.
To generate a diff
Module Name:src
Committed By: jmcneill
Date: Fri Jan 17 13:54:47 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Set msi_id to its_id
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/arm/cortex/gicv3_its.c
Please
Module Name:src
Committed By: skrll
Date: Tue Dec 24 09:13:23 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Traiing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/arm/cortex/gicv3_its.c
Please note
Module Name:src
Committed By: skrll
Date: Tue Dec 24 09:12:56 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Traiing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs
Module Name:src
Committed By: jmcneill
Date: Thu May 2 23:07:40 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gic_reg.h
Log Message:
Fix definition of GICD_IROUTER; the input to this macro is the INTID,
which can be a value between 32 and 1019.
To generate a diff
Module Name:src
Committed By: jmcneill
Date: Wed Jan 30 02:01:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Fix bitmask in A64 errata workaround and write cval instead of tval on A64
To generate a diff of this commit:
cvs rdiff -u -r1.38
Module Name:src
Committed By: jmcneill
Date: Sat Jan 19 20:52:26 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: pl310.c
Log Message:
Remove hard requirement for "offset" property on Cortex-A5. This is not
required w/ FDT.
To generate a diff of this commit:
cvs rdiff
Module Name:src
Committed By: jakllsch
Date: Fri Dec 7 17:56:42 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c
Log Message:
fix a paste-o in a panic message
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/cortex/gic_v2m.c
Module Name:src
Committed By: jmcneill
Date: Wed Nov 28 22:54:11 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h
Log Message:
Allow non-power of 2 counts, and support alloc/release/alloc patterns for a
device as long as the ITT size is
Module Name:src
Committed By: jakllsch
Date: Sat Nov 24 22:08:54 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.h
Log Message:
include dev/pci/pcivar.h, we use pci_attach_args directly
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3
Module Name:src
Committed By: skrll
Date: Sat Nov 24 15:40:57 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic_reg.h gicv3_its.c
Log Message:
Handle ThunderX errata
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gic_reg.h
cvs
Module Name:src
Committed By: jmcneill
Date: Fri Nov 23 16:01:27 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Only allocate what we need for ITT tables
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7
Module Name:src
Committed By: jmcneill
Date: Fri Nov 23 11:49:04 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Fix LPI pending table size, use correct LPI conf offset in
gicv3_lpi_block_irqs, and set bit[7]=1 for G1NS interrupts when writing to
Module Name:src
Committed By: jmcneill
Date: Fri Nov 23 11:48:12 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Fix ITT size, only need to MAPD once per device.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6
Module Name:src
Committed By: jakllsch
Date: Thu Nov 22 20:47:38 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
use correct interrupt index
fixes intrctl list
from jmcneill@
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5
Module Name:src
Committed By: jmcneill
Date: Wed Nov 21 11:44:26 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3_its.c
Log Message:
kcpuset_ffs returns the cpu number plus one, so make sure to subtract it
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: jmcneill
Date: Sat Nov 17 00:17:54 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Use intr_establish_xname
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/cortex/gicv3.c
Please note
Module Name:src
Committed By: jmcneill
Date: Fri Nov 16 23:25:09 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Use intr_establish_xname
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/arm/cortex/gic.c
Please note that
Module Name:src
Committed By: jmcneill
Date: Thu Nov 15 17:15:52 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
A64 timer errata can cause the timer to fire too soon, so skip KASSERT here too.
To generate a diff of this commit:
cvs rdiff -u -r1.37
Module Name:src
Committed By: jmcneill
Date: Thu Nov 15 00:01:38 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Instead of disabling preemption, set the binary point field to the minimum
supported value
To generate a diff of this commit:
cvs
Module Name:src
Committed By: jmcneill
Date: Tue Nov 13 22:25:29 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic_reg.h gicv3.c
Log Message:
Update GICD_CTLR reg bit definitions to reflect the layout of the register
when either in non-secure state or for a system
Module Name:src
Committed By: jmcneill
Date: Tue Nov 13 10:33:03 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Save a few pages by only allocating LPI pending tables for "ncpu" instead of
"MAXCPU" CPUs.
To generate a diff of this commit:
cvs
Module Name:src
Committed By: jmcneill
Date: Sat Nov 10 11:46:31 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h gicv3_its.c gicv3_its.h
Log Message:
Implement pic_get_affinity/pic_set_affinity for LPIs via ITS
To generate a diff of this commit:
cvs
Module Name:src
Committed By: jmcneill
Date: Sat Nov 10 01:56:28 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h
Log Message:
Implement pic_get_affinity/pic_set_affinity for SPIs
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6
Module Name:src
Committed By: jmcneill
Date: Fri Nov 9 23:36:24 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: files.cortex gic_reg.h gicv3.c gicv3.h
Added Files:
src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h
Log Message:
Add support for GICv3
Module Name:src
Committed By: jmcneill
Date: Mon Nov 5 11:50:15 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
ICC_PMR_EL1 has different encoding than IPRIORITYR. Not 100% sure that this is
correct yet, but it works with both RK3399 and QEMU.
Module Name:src
Committed By: jmcneill
Date: Wed Oct 31 15:43:19 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c
Log Message:
Add MSI-X support.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/gic_v2m.c
Please note that
Module Name:src
Committed By: jmcneill
Date: Tue Oct 30 23:59:47 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c
Log Message:
Fail gracefully when an attempt to allocate MSI vectors is made on a device
without MSI capabilities.
To generate a diff of this
Module Name:src
Committed By: jmcneill
Date: Tue Oct 30 10:38:11 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Disable diagnostic assertions around timer jitter on Allwinner A64. It
seems the instability of CNTVCT can cause issues with the compare
Module Name:src
Committed By: aymeric
Date: Sun Oct 28 21:08:13 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: a9tmr.c
Log Message:
Enable the global timer at attach time, it ensures that delay() works.
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18
Module Name:src
Committed By: aymeric
Date: Sun Oct 14 19:01:00 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: a9tmr.c
Log Message:
Remove comment that the peripherals clock should be half of the cpu clock.
NFC
To generate a diff of this commit:
cvs rdiff -u -r1.16
Module Name:src
Committed By: jmcneill
Date: Sun Sep 30 13:53:26 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Set NS access bit when writing ICC_PMR_EL1
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/gicv3.c
Module Name:src
Committed By: skrll
Date: Sun Sep 30 10:34:38 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
If we're going to allow pl0 to access virtual and physical counters then
we should allow it from all CPUs.
kern/53630 (openssl fallout on
Module Name:src
Committed By: skrll
Date: Tue Sep 25 20:55:34 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: armperiph.c
Log Message:
Cortex A5 also uses PPI 27 for timer.
ODROID-C1 boots again.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15
Module Name:src
Committed By: jmcneill
Date: Mon Sep 10 19:43:58 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
armgic_ipi_send: use GIC interface number, not CPU index, when setting
the target(s) for an IPI.
To generate a diff of this commit:
cvs
Module Name:src
Committed By: skrll
Date: Mon Sep 10 10:55:03 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Typo in comment from Joerg's gtmr diff
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/arm/cortex/gtmr.c
Module Name:src
Committed By: jmcneill
Date: Mon Sep 10 09:48:57 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Update sc_mptargets atomically, as PEs will be started up in parallel w/o
locking here
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: tnn
Date: Sat Sep 1 20:54:32 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
fix non-DIAGNOSTIC build
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/arm/cortex/gtmr.c
Please note that
Module Name:src
Committed By: jmcneill
Date: Sat Aug 11 00:32:17 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
IPI and priority fixes. My RK3399 board boots multiuser now.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2
Module Name:src
Committed By: jmcneill
Date: Wed Aug 8 19:02:28 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: files.cortex
Added Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h
Log Message:
Add GICv3 support.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: jmcneill
Date: Wed Aug 8 19:01:55 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic_reg.h
Log Message:
Update for GICv3
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/gic_reg.h
Please note that
Module Name:src
Committed By: jmcneill
Date: Sun Jul 15 16:04:07 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Support pic_set_affinity and pic_get_affinity
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35
Module Name:src
Committed By: jmcneill
Date: Sat Jun 30 17:30:37 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
ARM ARM refers to this as "ARM Generic Timer", so adjust printf at attach
to match.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: ryo
Date: Wed Jun 27 11:05:50 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: a9_mpsubr.S
Log Message:
keep stack pointer even if chainging CPU mode.
To generate a diff of this commit:
cvs rdiff -u -r1.55 -r1.56
Module Name:src
Committed By: ryo
Date: Sun Jun 24 19:04:30 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
fixed a case of gtmr_cntvct_stable_read() is returning the same value as before.
To generate a diff of this commit:
cvs rdiff -u -r1.30
Module Name:src
Committed By: hkenken
Date: Wed Jun 20 05:01:40 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: a9tmr.c a9tmr_var.h
Log Message:
Use mpcaa_off1 parameter for mapping subregion.
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16
Module Name:src
Committed By: jmcneill
Date: Sun Jun 17 22:42:41 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Simplify gtmr_delay and don't mix and match usage of the physical and
virtual timers (always use the virtual timer).
To generate a diff
Module Name:src
Committed By: jakllsch
Date: Sat Jun 9 01:17:35 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Avoid unnecessarily touching CNTP_CTL.
We may not have the privilege of accessing CNTP_CTL if running as a
virtualized guest, and we're
Module Name:src
Committed By: jmcneill
Date: Mon May 21 10:28:13 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Replace stable_read/write debug printfs with event counters
To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28
Module Name:src
Committed By: joerg
Date: Mon May 14 17:11:38 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Remove a number of debug #if 0s.
To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/arm/cortex/gtmr.c
Please note
Module Name:src
Committed By: joerg
Date: Mon May 14 17:09:41 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c gtmr_var.h
Log Message:
Remove unused gtmr_bootdelay.
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/cortex/gtmr.c
cvs
Module Name:src
Committed By: jakllsch
Date: Sat Apr 28 18:26:53 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Cover all pic_maxsources lines for armgic_cpu_init_priorities() and
armgic_cpu_update_priorities().
Previously only the first 32 lines
Module Name:src
Committed By: jmcneill
Date: Wed Feb 7 20:42:17 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC
The priority level is changed by writing to GICC_PMR with
Module Name:src
Committed By: skrll
Date: Thu Jan 18 12:49:09 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: a9_mpsubr.S
Log Message:
Use r0 in the tlbiall instruction to avoid confusion.
>From Ramakrishna Rao Desetti
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: skrll
Date: Fri Dec 29 11:07:03 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: a9wdt.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/a9wdt.c
Please note that diffs
Module Name:src
Committed By: skrll
Date: Fri Dec 29 11:06:27 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: a9wdt.c armperiph.c
Log Message:
Set attached to true when attach completes.
Reported by Ramakrishna Rao Desetti on port-arm
To generate a diff of this
Module Name:src
Committed By: matt
Date: Fri Nov 10 22:54:20 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: a9_mpsubr.S
Log Message:
Add #define CPU_CORTEDVIRT to reduce copied complex ifdef.
Shrink HYP test
To generate a diff of this commit:
cvs rdiff -u -r1.52
Module Name:src
Committed By: skrll
Date: Thu Nov 9 21:38:25 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: gtmr_var.h
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/gtmr_var.h
Please note that
Module Name:src
Committed By: skrll
Date: Sat Nov 4 17:09:55 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: a9_mpsubr.S
Log Message:
Ensure CNTVOFF is 0 before dropping out of Hyp mode
CVS --
To
Module Name:src
Committed By: skrll
Date: Wed Oct 25 16:09:46 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Improve delay to be better than 1.3 innaccurate by default and handle the
unlikely wrap
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: skrll
Date: Wed Oct 25 16:08:09 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs
Module Name:src
Committed By: skrll
Date: Fri Sep 22 06:31:02 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: a9_mpsubr.S
Log Message:
Typo
To generate a diff of this commit:
cvs rdiff -u -r1.50 -r1.51 src/sys/arch/arm/cortex/a9_mpsubr.S
Please note that diffs are
Module Name:src
Committed By: jmcneill
Date: Sat Sep 9 13:14:30 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
gtmr_intr: If the ISTATUS bit is 0, timer condition is not met. In this
case, just return 0.
To generate a diff of this commit:
cvs
Module Name:src
Committed By: jmcneill
Date: Wed Sep 6 18:08:35 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: a9_mpsubr.S
Log Message:
Clear TEX Remap Enable in SCTLR. U-Boot with CONFIG_ARMV8_SWITCH_TO_EL1
sets it since it is RES1 when TTBCR.EAE=1, but we are still
Module Name:src
Committed By: skrll
Date: Fri Jul 14 06:33:26 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public
1 - 100 of 218 matches
Mail list logo
