CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Tue Aug 10 17:12:31 UTC 2021 Modified Files: src/sys/arch/arm/cortex: files.cortex gic.c gicv3.c Log Message: Make gic_splfuncs optional and disable it by default until it has had more testing. To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/files.cortex cvs rdiff -u -r1.48 -r1.49 src/sys/arch/arm/cortex/gic.c cvs rdiff -u -r1.45 -r1.46 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/files.cortex diff -u src/sys/arch/arm/cortex/files.cortex:1.15 src/sys/arch/arm/cortex/files.cortex:1.16 --- src/sys/arch/arm/cortex/files.cortex:1.15 Tue Aug 10 15:33:09 2021 +++ src/sys/arch/arm/cortex/files.cortex Tue Aug 10 17:12:31 2021 @@ -1,4 +1,4 @@ -# $NetBSD: files.cortex,v 1.15 2021/08/10 15:33:09 jmcneill Exp $ +# $NetBSD: files.cortex,v 1.16 2021/08/10 17:12:31 jmcneill Exp $ defflag opt_cpu_in_cksum.h NEON_IN_CKSUM @@ -11,16 +11,16 @@ device armperiph: mpcorebus attach armperiph at mainbus file arch/arm/cortex/armperiph.c armperiph -define gic_splfuncs +defflag opt_gic.hGIC_SPLFUNCS file arch/arm/cortex/gic_splfuncs.c gic_splfuncs # ARM Generic Interrupt Controller (initially on Cortex-A9) -device armgic: pic, pic_splfuncs, gic_splfuncs +device armgic: pic, pic_splfuncs attach armgic at mpcorebus file arch/arm/cortex/gic.c armgic # ARM Generic Interrupt Controller v3+ -device gicvthree: pic, pic_splfuncs, gic_splfuncs +device gicvthree: pic, pic_splfuncs file arch/arm/cortex/gicv3.c gicvthree file arch/arm/cortex/gicv3_its.c gicvthree & pci & __have_pci_msi_msix Index: src/sys/arch/arm/cortex/gic.c diff -u src/sys/arch/arm/cortex/gic.c:1.48 src/sys/arch/arm/cortex/gic.c:1.49 --- src/sys/arch/arm/cortex/gic.c:1.48 Tue Aug 10 15:33:09 2021 +++ src/sys/arch/arm/cortex/gic.c Tue Aug 10 17:12:31 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: gic.c,v 1.48 2021/08/10 15:33:09 jmcneill Exp $ */ +/* $NetBSD: gic.c,v 1.49 2021/08/10 17:12:31 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -30,11 +30,12 @@ #include "opt_ddb.h" #include "opt_multiprocessor.h" +#include "opt_gic.h" #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.48 2021/08/10 15:33:09 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.49 2021/08/10 17:12:31 jmcneill Exp $"); #include #include @@ -50,9 +51,12 @@ __KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.48 #include #include -#include #include +#ifdef GIC_SPLFUNCS +#include +#endif + void armgic_irq_handler(void *); #define ARMGIC_SGI_IPIBASE 0 @@ -730,7 +734,9 @@ armgic_attach(device_t parent, device_t "%u SGIs\n", priorities, sc->sc_gic_lines - ppis - sgis, ppis, sgis); +#ifdef GIC_SPLFUNCS gic_spl_init(); +#endif } CFATTACH_DECL_NEW(armgic, 0, Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.45 src/sys/arch/arm/cortex/gicv3.c:1.46 --- src/sys/arch/arm/cortex/gicv3.c:1.45 Tue Aug 10 15:33:09 2021 +++ src/sys/arch/arm/cortex/gicv3.c Tue Aug 10 17:12:31 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.45 2021/08/10 15:33:09 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.46 2021/08/10 17:12:31 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -27,11 +27,12 @@ */ #include "opt_multiprocessor.h" +#include "opt_gic.h" #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.45 2021/08/10 15:33:09 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.46 2021/08/10 17:12:31 jmcneill Exp $"); #include #include @@ -51,7 +52,10 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1. #include #include + +#ifdef GIC_SPLFUNCS #include +#endif #define PICTOSOFTC(pic) \ ((void *)((uintptr_t)(pic) - offsetof(struct gicv3_softc, sc_pic))) @@ -952,7 +956,9 @@ gicv3_init(struct gicv3_softc *sc) #endif #endif +#ifdef GIC_SPLFUNCS gic_spl_init(); +#endif return 0; }
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Tue Aug 10 15:33:09 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: files.cortex gic.c gicv3.c
Added Files:
src/sys/arch/arm/cortex: gic_splfuncs.c gic_splfuncs.h
Log Message:
Use custom spl funcs for GIC and avoid unnecessary pmr register accesses
in splx.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/files.cortex
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/arm/cortex/gic.c
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/cortex/gic_splfuncs.c \
src/sys/arch/arm/cortex/gic_splfuncs.h
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/files.cortex
diff -u src/sys/arch/arm/cortex/files.cortex:1.14 src/sys/arch/arm/cortex/files.cortex:1.15
--- src/sys/arch/arm/cortex/files.cortex:1.14 Tue Sep 29 19:58:50 2020
+++ src/sys/arch/arm/cortex/files.cortex Tue Aug 10 15:33:09 2021
@@ -1,4 +1,4 @@
-# $NetBSD: files.cortex,v 1.14 2020/09/29 19:58:50 jmcneill Exp $
+# $NetBSD: files.cortex,v 1.15 2021/08/10 15:33:09 jmcneill Exp $
defflag opt_cpu_in_cksum.h NEON_IN_CKSUM
@@ -11,13 +11,16 @@ device armperiph: mpcorebus
attach armperiph at mainbus
file arch/arm/cortex/armperiph.c armperiph
+define gic_splfuncs
+file arch/arm/cortex/gic_splfuncs.c gic_splfuncs
+
# ARM Generic Interrupt Controller (initially on Cortex-A9)
-device armgic: pic, pic_splfuncs
+device armgic: pic, pic_splfuncs, gic_splfuncs
attach armgic at mpcorebus
file arch/arm/cortex/gic.c armgic
# ARM Generic Interrupt Controller v3+
-device gicvthree: pic, pic_splfuncs
+device gicvthree: pic, pic_splfuncs, gic_splfuncs
file arch/arm/cortex/gicv3.c gicvthree
file arch/arm/cortex/gicv3_its.c gicvthree & pci & __have_pci_msi_msix
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.47 src/sys/arch/arm/cortex/gic.c:1.48
--- src/sys/arch/arm/cortex/gic.c:1.47 Sun Mar 28 09:11:38 2021
+++ src/sys/arch/arm/cortex/gic.c Tue Aug 10 15:33:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.47 2021/03/28 09:11:38 skrll Exp $ */
+/* $NetBSD: gic.c,v 1.48 2021/08/10 15:33:09 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.47 2021/03/28 09:11:38 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.48 2021/08/10 15:33:09 jmcneill Exp $");
#include
#include
@@ -50,6 +50,7 @@ __KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.47
#include
#include
+#include
#include
void armgic_irq_handler(void *);
@@ -224,11 +225,10 @@ armgic_set_priority(struct pic_softc *pi
struct armgic_softc * const sc = PICTOSOFTC(pic);
struct cpu_info * const ci = curcpu();
- const uint32_t priority = armgic_ipl_to_priority(ipl);
- if (priority > ci->ci_hwpl) {
+ if (ipl < ci->ci_hwpl) {
/* Lowering priority mask */
- ci->ci_hwpl = priority;
- gicc_write(sc, GICC_PMR, priority);
+ ci->ci_hwpl = ipl;
+ gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl));
}
}
@@ -327,10 +327,9 @@ armgic_irq_handler(void *tf)
ci->ci_data.cpu_nintr++;
- const uint32_t priority = armgic_ipl_to_priority(old_ipl);
- if (ci->ci_hwpl != priority) {
- ci->ci_hwpl = priority;
- gicc_write(sc, GICC_PMR, priority);
+ if (ci->ci_hwpl != old_ipl) {
+ ci->ci_hwpl = old_ipl;
+ gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(old_ipl));
if (old_ipl == IPL_HIGH) {
return;
}
@@ -545,7 +544,7 @@ armgic_cpu_init(struct pic_softc *pic, s
sc->sc_enabled_local);
}
}
- ci->ci_hwpl = armgic_ipl_to_priority(ci->ci_cpl);
+ ci->ci_hwpl = ci->ci_cpl;
gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl)); // set PMR
gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt
ENABLE_INTERRUPT();// allow IRQ exceptions
@@ -730,6 +729,8 @@ armgic_attach(device_t parent, device_t
aprint_normal_dev(sc->sc_dev, "%u Priorities, %zu SPIs, %u PPIs, "
"%u SGIs\n", priorities, sc->sc_gic_lines - ppis - sgis, ppis,
sgis);
+
+ gic_spl_init();
}
CFATTACH_DECL_NEW(armgic, 0,
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.44 src/sys/arch/arm/cortex/gicv3.c:1.45
--- src/sys/arch/arm/cortex/gicv3.c:1.44 Sun Mar 28 11:13:24 2021
+++ src/sys/arch/arm/cortex/gicv3.c Tue Aug 10 15:33:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.44 2021/03/28 11:13:24 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.45 2021/08/10 15:33:09 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.44 2021/03/28 11:13:24 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.45 2021/08/10 15:33:09 jmcneill Exp $");
#include
#include
@@ -51,6 +51,7 @@ __KERNEL_RCSID(0, "$NetBSD:
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Mar 28 11:13:24 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Disable 1ofN distribution of SPIs by default. This is a workaround for an
issue in the USB stack -- signaling transfer complete on multiple PEs can
cause transfer completions to be processed out of order.
To generate a diff of this commit:
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.43 src/sys/arch/arm/cortex/gicv3.c:1.44
--- src/sys/arch/arm/cortex/gicv3.c:1.43 Tue Feb 23 10:03:04 2021
+++ src/sys/arch/arm/cortex/gicv3.c Sun Mar 28 11:13:24 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.43 2021/02/23 10:03:04 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.44 2021/03/28 11:13:24 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.43 2021/02/23 10:03:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.44 2021/03/28 11:13:24 jmcneill Exp $");
#include
#include
@@ -65,6 +65,13 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#define GIC_PRIO_SHIFT_NS 4
#define GIC_PRIO_SHIFT_S 3
+/*
+ * Set to true if you want to use 1 of N interrupt distribution for SPIs
+ * when available. Disabled by default because it causes issues with the
+ * USB stack.
+ */
+bool gicv3_use_1ofn = false;
+
static struct gicv3_softc *gicv3_softc;
static inline uint32_t
@@ -195,7 +202,7 @@ gicv3_establish_irq(struct pic_softc *pi
* If 1 of N SPI routing is supported, route MP-safe interrupts to all
* participating PEs. Otherwise, just route to the primary PE.
*/
- if (is->is_mpsafe && GIC_SUPPORTS_1OFN(sc)) {
+ if (is->is_mpsafe && GIC_SUPPORTS_1OFN(sc) && gicv3_use_1ofn) {
irouter = GICD_IROUTER_Interrupt_Routing_mode;
} else {
irouter = sc->sc_irouter[0];
@@ -498,7 +505,7 @@ gicv3_set_affinity(struct pic_softc *pic
const int set = kcpuset_countset(affinity);
if (set == 1) {
irouter = sc->sc_irouter[kcpuset_ffs(affinity) - 1];
- } else if (set == ncpu && GIC_SUPPORTS_1OFN(sc)) {
+ } else if (set == ncpu && GIC_SUPPORTS_1OFN(sc) && gicv3_use_1ofn) {
irouter = GICD_IROUTER_Interrupt_Routing_mode;
} else {
return EINVAL;
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Sun Mar 28 09:11:38 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Only target the boot cpu for real with SPI interrupts. I tried to do
this back in 2014, but somehow I missed a spot.
This is a quick-and-dirty fix for the USB stack which expects transfer
completions to be in-order. If interrupts happen across the CPUs then
this isn't guaranteed (yet).
kern/55243 panic at usb_transfer_complete() on raspberry pi 4
To generate a diff of this commit:
cvs rdiff -u -r1.46 -r1.47 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.46 src/sys/arch/arm/cortex/gic.c:1.47
--- src/sys/arch/arm/cortex/gic.c:1.46 Tue Feb 23 10:03:04 2021
+++ src/sys/arch/arm/cortex/gic.c Sun Mar 28 09:11:38 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.46 2021/02/23 10:03:04 jmcneill Exp $ */
+/* $NetBSD: gic.c,v 1.47 2021/03/28 09:11:38 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.46 2021/02/23 10:03:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.47 2021/03/28 09:11:38 skrll Exp $");
#include
#include
@@ -517,7 +517,11 @@ armgic_cpu_init_targets(struct armgic_so
if (is != NULL && is->is_mpsafe) {
const u_int byte_shift = 8 * (irq & 3);
uint32_t targets = gicd_read(sc, targets_reg);
+#if 0
targets |= sc->sc_mptargets << byte_shift;
+#else
+ targets |= sc->sc_bptargets << byte_shift;
+#endif
gicd_write(sc, targets_reg, targets);
}
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Sun Mar 14 08:09:20 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c
Log Message:
Remove an unnecessary if statement in gic_v2m_msi_alloc when finding a
'count' that fits the available.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/cortex/gic_v2m.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_v2m.c
diff -u src/sys/arch/arm/cortex/gic_v2m.c:1.10 src/sys/arch/arm/cortex/gic_v2m.c:1.11
--- src/sys/arch/arm/cortex/gic_v2m.c:1.10 Fri Dec 11 21:40:50 2020
+++ src/sys/arch/arm/cortex/gic_v2m.c Sun Mar 14 08:09:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.c,v 1.10 2020/12/11 21:40:50 jmcneill Exp $ */
+/* $NetBSD: gic_v2m.c,v 1.11 2021/03/14 08:09:20 skrll Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.10 2020/12/11 21:40:50 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.11 2021/03/14 08:09:20 skrll Exp $");
#include
#include
@@ -240,10 +240,9 @@ gic_v2m_msi_alloc(struct arm_pci_msi *ms
if (exact && *count > avail)
return NULL;
- while (*count > avail) {
- if (avail < *count)
- (*count) >>= 1;
- }
+ while (*count > avail)
+ (*count) >>= 1;
+
if (*count == 0)
return NULL;
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Tue Feb 23 10:03:05 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c gicv3.c
Log Message:
If we are committing a deferred splhigh() to hardware, no need to continue.
To generate a diff of this commit:
cvs rdiff -u -r1.45 -r1.46 src/sys/arch/arm/cortex/gic.c
cvs rdiff -u -r1.42 -r1.43 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.45 src/sys/arch/arm/cortex/gic.c:1.46
--- src/sys/arch/arm/cortex/gic.c:1.45 Sun Feb 21 15:45:30 2021
+++ src/sys/arch/arm/cortex/gic.c Tue Feb 23 10:03:04 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.45 2021/02/21 15:45:30 jmcneill Exp $ */
+/* $NetBSD: gic.c,v 1.46 2021/02/23 10:03:04 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.45 2021/02/21 15:45:30 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.46 2021/02/23 10:03:04 jmcneill Exp $");
#include
#include
@@ -331,6 +331,9 @@ armgic_irq_handler(void *tf)
if (ci->ci_hwpl != priority) {
ci->ci_hwpl = priority;
gicc_write(sc, GICC_PMR, priority);
+ if (old_ipl == IPL_HIGH) {
+ return;
+ }
}
for (;;) {
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.42 src/sys/arch/arm/cortex/gicv3.c:1.43
--- src/sys/arch/arm/cortex/gicv3.c:1.42 Sun Feb 21 15:00:05 2021
+++ src/sys/arch/arm/cortex/gicv3.c Tue Feb 23 10:03:04 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.42 2021/02/21 15:00:05 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.43 2021/02/23 10:03:04 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.42 2021/02/21 15:00:05 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.43 2021/02/23 10:03:04 jmcneill Exp $");
#include
#include
@@ -738,6 +738,9 @@ gicv3_irq_handler(void *frame)
if (ci->ci_hwpl != pmr) {
ci->ci_hwpl = pmr;
icc_pmr_write(pmr);
+ if (oldipl == IPL_HIGH) {
+ return;
+ }
}
for (;;) {
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Feb 21 15:45:30 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Apply PMR optimizations from gicv3
To generate a diff of this commit:
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.44 src/sys/arch/arm/cortex/gic.c:1.45
--- src/sys/arch/arm/cortex/gic.c:1.44 Tue Feb 9 14:24:14 2021
+++ src/sys/arch/arm/cortex/gic.c Sun Feb 21 15:45:30 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.44 2021/02/09 14:24:14 jakllsch Exp $ */
+/* $NetBSD: gic.c,v 1.45 2021/02/21 15:45:30 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.44 2021/02/09 14:24:14 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.45 2021/02/21 15:45:30 jmcneill Exp $");
#include
#include
@@ -222,9 +222,14 @@ static void
armgic_set_priority(struct pic_softc *pic, int ipl)
{
struct armgic_softc * const sc = PICTOSOFTC(pic);
+ struct cpu_info * const ci = curcpu();
const uint32_t priority = armgic_ipl_to_priority(ipl);
- gicc_write(sc, GICC_PMR, priority);
+ if (priority > ci->ci_hwpl) {
+ /* Lowering priority mask */
+ ci->ci_hwpl = priority;
+ gicc_write(sc, GICC_PMR, priority);
+ }
}
#ifdef MULTIPROCESSOR
@@ -322,6 +327,12 @@ armgic_irq_handler(void *tf)
ci->ci_data.cpu_nintr++;
+ const uint32_t priority = armgic_ipl_to_priority(old_ipl);
+ if (ci->ci_hwpl != priority) {
+ ci->ci_hwpl = priority;
+ gicc_write(sc, GICC_PMR, priority);
+ }
+
for (;;) {
uint32_t iar = gicc_read(sc, GICC_IAR);
uint32_t irq = __SHIFTOUT(iar, GICC_IAR_IRQ);
@@ -365,7 +376,7 @@ armgic_irq_handler(void *tf)
ipl, ci->ci_cpl,
gicc_read(sc, GICC_PMR));
gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl));
- ci->ci_cpl = ipl;
+ ci->ci_hwpl = ci->ci_cpl = ipl;
}
ENABLE_INTERRUPT();
pic_dispatch(is, tf);
@@ -527,6 +538,7 @@ armgic_cpu_init(struct pic_softc *pic, s
sc->sc_enabled_local);
}
}
+ ci->ci_hwpl = armgic_ipl_to_priority(ci->ci_cpl);
gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl)); // set PMR
gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt
ENABLE_INTERRUPT();// allow IRQ exceptions
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: ryo
Date: Tue Feb 9 17:44:01 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
fix build without MULTIPROCESSOR
To generate a diff of this commit:
cvs rdiff -u -r1.40 -r1.41 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.40 src/sys/arch/arm/cortex/gicv3.c:1.41
--- src/sys/arch/arm/cortex/gicv3.c:1.40 Sun Feb 7 21:24:50 2021
+++ src/sys/arch/arm/cortex/gicv3.c Tue Feb 9 17:44:01 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.40 2021/02/07 21:24:50 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.41 2021/02/09 17:44:01 ryo Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.40 2021/02/07 21:24:50 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.41 2021/02/09 17:44:01 ryo Exp $");
#include
#include
@@ -79,11 +79,13 @@ gicd_write_4(struct gicv3_softc *sc, bus
bus_space_write_4(sc->sc_bst, sc->sc_bsh_d, reg, val);
}
+#ifdef MULTIPROCESSOR
static inline uint64_t
gicd_read_8(struct gicv3_softc *sc, bus_size_t reg)
{
return bus_space_read_8(sc->sc_bst, sc->sc_bsh_d, reg);
}
+#endif
static inline void
gicd_write_8(struct gicv3_softc *sc, bus_size_t reg, uint64_t val)
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jakllsch Date: Tue Feb 9 14:24:14 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: Avoid an extra daif read when dispatching interrupts by using ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros. To generate a diff of this commit: cvs rdiff -u -r1.43 -r1.44 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic.c diff -u src/sys/arch/arm/cortex/gic.c:1.43 src/sys/arch/arm/cortex/gic.c:1.44 --- src/sys/arch/arm/cortex/gic.c:1.43 Thu Dec 3 07:45:52 2020 +++ src/sys/arch/arm/cortex/gic.c Tue Feb 9 14:24:14 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: gic.c,v 1.43 2020/12/03 07:45:52 skrll Exp $ */ +/* $NetBSD: gic.c,v 1.44 2021/02/09 14:24:14 jakllsch Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -34,7 +34,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.43 2020/12/03 07:45:52 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.44 2021/02/09 14:24:14 jakllsch Exp $"); #include #include @@ -367,9 +367,9 @@ armgic_irq_handler(void *tf) gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl)); ci->ci_cpl = ipl; } - cpsie(I32_bit); + ENABLE_INTERRUPT(); pic_dispatch(is, tf); - cpsid(I32_bit); + DISABLE_INTERRUPT(); gicc_write(sc, GICC_EOIR, iar); #ifdef DEBUG n++; @@ -529,7 +529,7 @@ armgic_cpu_init(struct pic_softc *pic, s } gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl)); // set PMR gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt - cpsie(I32_bit); // allow IRQ exceptions + ENABLE_INTERRUPT();// allow IRQ exceptions } void @@ -656,7 +656,7 @@ armgic_attach(device_t parent, device_t armgic_set_priority(>sc_pic, ci->ci_cpl); // set PMR gicd_write(sc, GICD_CTRL, GICD_CTRL_Enable); // enable Distributer gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable CPU interrupts - cpsie(I32_bit); // allow interrupt exceptions + ENABLE_INTERRUPT();// allow interrupt exceptions /* * For each line that isn't valid, we set the intrsource for it to
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Feb 7 21:24:50 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Optimize hardware priority updates.
In gicv3_set_priority, read the current priority mask and only update it
if we are lowering the priority. The hardware priority filter is raised
only after taking an interrupt. This makes splfoo/splx without an interrupt
in between considerably cheaper as PMR writes are relatively expensive
compared to reads.
While here, avoid an extra daif read when dispatching interrupts by using
ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.39 src/sys/arch/arm/cortex/gicv3.c:1.40
--- src/sys/arch/arm/cortex/gicv3.c:1.39 Sat Jan 16 21:05:15 2021
+++ src/sys/arch/arm/cortex/gicv3.c Sun Feb 7 21:24:50 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.39 2021/01/16 21:05:15 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.40 2021/02/07 21:24:50 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.39 2021/01/16 21:05:15 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.40 2021/02/07 21:24:50 jmcneill Exp $");
#include
#include
@@ -220,8 +220,13 @@ static void
gicv3_set_priority(struct pic_softc *pic, int ipl)
{
struct gicv3_softc * const sc = PICTOSOFTC(pic);
+ const uint8_t curpmr = icc_pmr_read();
+ const uint8_t newpmr = IPL_TO_PMR(sc, ipl);
- icc_pmr_write(IPL_TO_PMR(sc, ipl));
+ if (newpmr > curpmr) {
+ /* Lowering priority mask */
+ icc_pmr_write(newpmr);
+ }
}
static void
@@ -407,7 +412,7 @@ gicv3_cpu_init(struct pic_softc *pic, st
;
/* Set initial priority mask */
- gicv3_set_priority(pic, IPL_HIGH);
+ icc_pmr_write(IPL_TO_PMR(sc, IPL_HIGH));
/* Set the binary point field to the minimum value */
icc_bpr1_write(0);
@@ -424,7 +429,7 @@ gicv3_cpu_init(struct pic_softc *pic, st
gicv3_redist_enable(sc, ci);
/* Allow IRQ exceptions */
- cpsie(I32_bit);
+ ENABLE_INTERRUPT();
}
#ifdef MULTIPROCESSOR
@@ -722,9 +727,14 @@ gicv3_irq_handler(void *frame)
struct gicv3_softc * const sc = gicv3_softc;
struct pic_softc *pic;
const int oldipl = ci->ci_cpl;
+ const uint8_t pmr = IPL_TO_PMR(sc, oldipl);
ci->ci_data.cpu_nintr++;
+ if (icc_pmr_read() != pmr) {
+ icc_pmr_write(pmr);
+ }
+
for (;;) {
const uint32_t iar = icc_iar1_read();
dsb(sy);
@@ -745,7 +755,7 @@ gicv3_irq_handler(void *frame)
if (__predict_false(ipl < ci->ci_cpl)) {
pic_do_pending_ints(I32_bit, ipl, frame);
} else if (ci->ci_cpl != ipl) {
- gicv3_set_priority(pic, ipl);
+ icc_pmr_write(IPL_TO_PMR(sc, ipl));
ci->ci_cpl = ipl;
}
@@ -756,9 +766,9 @@ gicv3_irq_handler(void *frame)
const int64_t nintr = ci->ci_data.cpu_nintr;
- cpsie(I32_bit);
+ ENABLE_INTERRUPT();
pic_dispatch(is, frame);
- cpsid(I32_bit);
+ DISABLE_INTERRUPT();
if (nintr != ci->ci_data.cpu_nintr)
ci->ci_intr_preempt.ev_count++;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Mon Jan 18 23:43:35 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: Fix a comment To generate a diff of this commit: cvs rdiff -u -r1.42 -r1.43 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gtmr.c diff -u src/sys/arch/arm/cortex/gtmr.c:1.42 src/sys/arch/arm/cortex/gtmr.c:1.43 --- src/sys/arch/arm/cortex/gtmr.c:1.42 Fri Oct 30 18:54:36 2020 +++ src/sys/arch/arm/cortex/gtmr.c Mon Jan 18 23:43:34 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: gtmr.c,v 1.42 2020/10/30 18:54:36 skrll Exp $ */ +/* $NetBSD: gtmr.c,v 1.43 2021/01/18 23:43:34 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.42 2020/10/30 18:54:36 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.43 2021/01/18 23:43:34 jmcneill Exp $"); #include #include @@ -178,7 +178,7 @@ gtmr_read_cntct(struct gtmr_softc *sc) /* * The Allwinner A64 SoC has an unstable architectural timer. * To workaround this problem, ignore reads where the lower - * 11 bits are all 0s or 1s. + * 10 bits are all 0s or 1s. */ uint64_t val; u_int bits;
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Jan 16 21:05:15 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h gicv3_its.c gicv3_its.h
Log Message:
Remove MAXCPUS dependency.
To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/cortex/gicv3.h
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/cortex/gicv3_its.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/gicv3_its.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.38 src/sys/arch/arm/cortex/gicv3.c:1.39
--- src/sys/arch/arm/cortex/gicv3.c:1.38 Tue Dec 22 10:46:51 2020
+++ src/sys/arch/arm/cortex/gicv3.c Sat Jan 16 21:05:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.38 2020/12/22 10:46:51 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.39 2021/01/16 21:05:15 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.38 2020/12/22 10:46:51 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.39 2021/01/16 21:05:15 jmcneill Exp $");
#include
#include
@@ -41,6 +41,7 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#include
#include
#include
+#include
#include
#include
@@ -838,7 +839,8 @@ gicv3_init(struct gicv3_softc *sc)
LIST_INIT(>sc_lpi_callbacks);
- for (n = 0; n < MAXCPUS; n++)
+ sc->sc_irouter = kmem_zalloc(sizeof(*sc->sc_irouter) * ncpu, KM_SLEEP);
+ for (n = 0; n < ncpu; n++)
sc->sc_irouter[n] = UINT64_MAX;
sc->sc_gicd_typer = gicd_read_4(sc, GICD_TYPER);
@@ -876,6 +878,9 @@ gicv3_init(struct gicv3_softc *sc)
pic_add(>sc_pic, 0);
if ((sc->sc_gicd_typer & GICD_TYPER_LPIS) != 0) {
+ sc->sc_lpipend = kmem_zalloc(sizeof(*sc->sc_lpipend) * ncpu, KM_SLEEP);
+ sc->sc_processor_id = kmem_zalloc(sizeof(*sc->sc_processor_id) * ncpu, KM_SLEEP);
+
sc->sc_lpi.pic_ops = _lpiops;
sc->sc_lpi.pic_maxsources = 8192; /* Min. required by GICv3 spec */
snprintf(sc->sc_lpi.pic_name, sizeof(sc->sc_lpi.pic_name), "gicv3-lpi");
Index: src/sys/arch/arm/cortex/gicv3.h
diff -u src/sys/arch/arm/cortex/gicv3.h:1.10 src/sys/arch/arm/cortex/gicv3.h:1.11
--- src/sys/arch/arm/cortex/gicv3.h:1.10 Fri Dec 4 21:39:26 2020
+++ src/sys/arch/arm/cortex/gicv3.h Sat Jan 16 21:05:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.h,v 1.10 2020/12/04 21:39:26 jmcneill Exp $ */
+/* $NetBSD: gicv3.h,v 1.11 2021/01/16 21:05:15 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -70,20 +70,20 @@ struct gicv3_softc {
u_int sc_pmr_shift;
uint32_t sc_enabled_sgippi;
- uint64_t sc_irouter[MAXCPUS];
+ uint64_t *sc_irouter;
/* LPI configuration table */
struct gicv3_dma sc_lpiconf;
bool sc_lpiconf_flush;
/* LPI pending tables */
- struct gicv3_dma sc_lpipend[MAXCPUS];
+ struct gicv3_dma *sc_lpipend;
/* LPI IDs */
vmem_t *sc_lpi_pool;
/* Unique identifier for PEs */
- u_int sc_processor_id[MAXCPUS];
+ u_int *sc_processor_id;
/* Callbacks */
LIST_HEAD(, gicv3_lpi_callback) sc_lpi_callbacks;
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.31 src/sys/arch/arm/cortex/gicv3_its.c:1.32
--- src/sys/arch/arm/cortex/gicv3_its.c:1.31 Thu Dec 24 14:44:49 2020
+++ src/sys/arch/arm/cortex/gicv3_its.c Sat Jan 16 21:05:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.31 2020/12/24 14:44:49 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.32 2021/01/16 21:05:15 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.31 2020/12/24 14:44:49 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.32 2021/01/16 21:05:15 jmcneill Exp $");
#include
#include
@@ -712,7 +712,7 @@ gicv3_its_table_init(struct gicv3_softc
/*
* Allocate space for one interrupt collection per CPU.
*/
- table_size = roundup(entry_size * MAXCPUS, page_size);
+ table_size = roundup(entry_size * ncpu, page_size);
table_type = "Collections";
break;
default:
@@ -866,6 +866,8 @@ gicv3_its_init(struct gicv3_softc *sc, b
its->its_pa = kmem_zalloc(sizeof(struct pci_attach_args *) * its->its_pic->pic_maxsources, KM_SLEEP);
its->its_targets = kmem_zalloc(sizeof(struct cpu_info *) * its->its_pic->pic_maxsources, KM_SLEEP);
its->its_gic = sc;
+ its->its_rdbase = kmem_zalloc(sizeof(*its->its_rdbase) * ncpu, KM_SLEEP);
+ its->its_cpuonline = kmem_zalloc(sizeof(*its->its_cpuonline) * ncpu, KM_SLEEP);
its->its_cb.cpu_init = gicv3_its_cpu_init;
its->its_cb.get_affinity = gicv3_its_get_affinity;
its->its_cb.set_affinity = gicv3_its_set_affinity;
Index: src/sys/arch/arm/cortex/gicv3_its.h
diff -u src/sys/arch/arm/cortex/gicv3_its.h:1.6
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Thu Dec 24 14:44:49 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.30 src/sys/arch/arm/cortex/gicv3_its.c:1.31 --- src/sys/arch/arm/cortex/gicv3_its.c:1.30 Fri Dec 11 22:42:31 2020 +++ src/sys/arch/arm/cortex/gicv3_its.c Thu Dec 24 14:44:49 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.30 2020/12/11 22:42:31 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.31 2020/12/24 14:44:49 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.30 2020/12/11 22:42:31 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.31 2020/12/24 14:44:49 jmcneill Exp $"); #include #include @@ -292,7 +292,7 @@ gicv3_its_msi_alloc_lpi(struct gicv3_its if (vmem_alloc(its->its_gic->sc_lpi_pool, 1, VM_INSTANTFIT|VM_SLEEP, ) != 0) return -1; - + KASSERT(its->its_pa[n] == NULL); new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP); @@ -437,7 +437,7 @@ gicv3_its_msix_enable(struct gicv3_its * bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32)); bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, lpi - its->its_pic->pic_irqbase); val = bus_space_read_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL); - val &= ~PCI_MSIX_VECTCTL_MASK; + val &= ~PCI_MSIX_VECTCTL_MASK; bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, val); ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Tue Dec 22 10:46:51 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
When lpiconf flushing is required, make sure to flush to PoC and not PoU.
Spotted by nick.
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.37 src/sys/arch/arm/cortex/gicv3.c:1.38
--- src/sys/arch/arm/cortex/gicv3.c:1.37 Fri Dec 11 21:22:36 2020
+++ src/sys/arch/arm/cortex/gicv3.c Tue Dec 22 10:46:51 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.37 2020/12/11 21:22:36 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.38 2020/12/22 10:46:51 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.37 2020/12/11 21:22:36 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.38 2020/12/22 10:46:51 jmcneill Exp $");
#include
#include
@@ -514,6 +514,13 @@ static const struct pic_ops gicv3_picops
};
static void
+gicv3_dcache_wb_range(vaddr_t va, vsize_t len)
+{
+ cpu_dcache_wb_range(va, len);
+ dsb(sy);
+}
+
+static void
gicv3_lpi_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask)
{
struct gicv3_softc * const sc = LPITOSOFTC(pic);
@@ -522,7 +529,7 @@ gicv3_lpi_unblock_irqs(struct pic_softc
while ((bit = ffs(mask)) != 0) {
sc->sc_lpiconf.base[irqbase + bit - 1] |= GIC_LPICONF_Enable;
if (sc->sc_lpiconf_flush)
- cpu_dcache_wb_range((vaddr_t)>sc_lpiconf.base[irqbase + bit - 1], 1);
+ gicv3_dcache_wb_range((vaddr_t)>sc_lpiconf.base[irqbase + bit - 1], 1);
mask &= ~__BIT(bit - 1);
}
@@ -539,7 +546,7 @@ gicv3_lpi_block_irqs(struct pic_softc *p
while ((bit = ffs(mask)) != 0) {
sc->sc_lpiconf.base[irqbase + bit - 1] &= ~GIC_LPICONF_Enable;
if (sc->sc_lpiconf_flush)
- cpu_dcache_wb_range((vaddr_t)>sc_lpiconf.base[irqbase + bit - 1], 1);
+ gicv3_dcache_wb_range((vaddr_t)>sc_lpiconf.base[irqbase + bit - 1], 1);
mask &= ~__BIT(bit - 1);
}
@@ -555,7 +562,7 @@ gicv3_lpi_establish_irq(struct pic_softc
sc->sc_lpiconf.base[is->is_irq] = IPL_TO_PRIORITY(sc, is->is_ipl) | GIC_LPICONF_Res1;
if (sc->sc_lpiconf_flush)
- cpu_dcache_wb_range((vaddr_t)>sc_lpiconf.base[is->is_irq], 1);
+ gicv3_dcache_wb_range((vaddr_t)>sc_lpiconf.base[is->is_irq], 1);
else
dsb(ishst);
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Fri Dec 11 22:42:31 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Simplify gits_command by getting rid of the _BYTE_ORDER test and just always use the loop + htole64 path. To generate a diff of this commit: cvs rdiff -u -r1.29 -r1.30 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.29 src/sys/arch/arm/cortex/gicv3_its.c:1.30 --- src/sys/arch/arm/cortex/gicv3_its.c:1.29 Fri Dec 11 21:40:50 2020 +++ src/sys/arch/arm/cortex/gicv3_its.c Fri Dec 11 22:42:31 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.29 2020/12/11 21:40:50 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.30 2020/12/11 22:42:31 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.29 2020/12/11 21:40:50 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.30 2020/12/11 22:42:31 jmcneill Exp $"); #include #include @@ -118,13 +118,9 @@ gits_command(struct gicv3_its *its, cons cwriter = gits_read_8(its, GITS_CWRITER); woff = cwriter & GITS_CWRITER_Offset; -#if _BYTE_ORDER == _BIG_ENDIAN uint64_t *dw = (uint64_t *)(its->its_cmd.base + woff); for (int i = 0; i < __arraycount(cmd->dw); i++) dw[i] = htole64(cmd->dw[i]); -#else - memcpy(its->its_cmd.base + woff, cmd->dw, sizeof(cmd->dw)); -#endif bus_dmamap_sync(its->its_dmat, its->its_cmd.map, woff, sizeof(cmd->dw), BUS_DMASYNC_PREWRITE); woff += sizeof(cmd->dw);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Fri Dec 11 21:40:50 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gic_v2m.c gicv3_its.c Log Message: Preserve ST Lower and Upper fields when clearing Mask bit in the MSI-X vector control register. To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gic_v2m.c cvs rdiff -u -r1.28 -r1.29 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic_v2m.c diff -u src/sys/arch/arm/cortex/gic_v2m.c:1.9 src/sys/arch/arm/cortex/gic_v2m.c:1.10 --- src/sys/arch/arm/cortex/gic_v2m.c:1.9 Thu May 7 16:20:40 2020 +++ src/sys/arch/arm/cortex/gic_v2m.c Fri Dec 11 21:40:50 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gic_v2m.c,v 1.9 2020/05/07 16:20:40 jmcneill Exp $ */ +/* $NetBSD: gic_v2m.c,v 1.10 2020/12/11 21:40:50 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.9 2020/05/07 16:20:40 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.10 2020/12/11 21:40:50 jmcneill Exp $"); #include #include @@ -183,6 +183,7 @@ gic_v2m_msix_enable(struct gic_v2m_frame pci_chipset_tag_t pc = pa->pa_pc; pcitag_t tag = pa->pa_tag; pcireg_t ctl; + uint32_t val; int off; if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, , NULL)) @@ -198,7 +199,9 @@ gic_v2m_msix_enable(struct gic_v2m_frame bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr); bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32)); bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, data); - bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0); + val = bus_space_read_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL); + val &= ~PCI_MSIX_VECTCTL_MASK; + bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, val); ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); ctl |= PCI_MSIX_CTL_ENABLE; Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.28 src/sys/arch/arm/cortex/gicv3_its.c:1.29 --- src/sys/arch/arm/cortex/gicv3_its.c:1.28 Thu Sep 24 08:50:09 2020 +++ src/sys/arch/arm/cortex/gicv3_its.c Fri Dec 11 21:40:50 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.28 2020/09/24 08:50:09 ryo Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.29 2020/12/11 21:40:50 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.28 2020/09/24 08:50:09 ryo Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.29 2020/12/11 21:40:50 jmcneill Exp $"); #include #include @@ -429,6 +429,7 @@ gicv3_its_msix_enable(struct gicv3_its * pci_chipset_tag_t pc = pa->pa_pc; pcitag_t tag = pa->pa_tag; pcireg_t ctl; + uint32_t val; int off; if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, , NULL)) @@ -439,7 +440,9 @@ gicv3_its_msix_enable(struct gicv3_its * bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr); bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32)); bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, lpi - its->its_pic->pic_irqbase); - bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0); + val = bus_space_read_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL); + val &= ~PCI_MSIX_VECTCTL_MASK; + bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, val); ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); ctl |= PCI_MSIX_CTL_ENABLE;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Fri Dec 11 21:22:37 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Fix spelling in comment. To generate a diff of this commit: cvs rdiff -u -r1.36 -r1.37 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.36 src/sys/arch/arm/cortex/gicv3.c:1.37 --- src/sys/arch/arm/cortex/gicv3.c:1.36 Fri Dec 4 21:39:26 2020 +++ src/sys/arch/arm/cortex/gicv3.c Fri Dec 11 21:22:36 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.36 2020/12/04 21:39:26 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.37 2020/12/11 21:22:36 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -31,7 +31,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.36 2020/12/04 21:39:26 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.37 2020/12/11 21:22:36 jmcneill Exp $"); #include #include @@ -837,7 +837,7 @@ gicv3_init(struct gicv3_softc *sc) sc->sc_gicd_typer = gicd_read_4(sc, GICD_TYPER); /* - * We don't alwayst have a consistent view of priorities between the + * We don't always have a consistent view of priorities between the * CPU interface (ICC_PMR_EL1) and the GICD/GICR registers. Detect * if we are making secure or non-secure accesses to each, and adjust * the values that we write to each accordingly.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Fri Dec 4 21:39:26 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h
Log Message:
gicv3: Only use 1 of N SPI distribution when the feature is available.
A GICv3+ implementation is not guaranteed to support 1 of N SPI
distribution. Support for this feature is indicated in GICD_TYPER.No1N.
When No1N=1, route all interrupts to the primary PE by default and only
allow a single CPU target when updating affinity.
To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gicv3.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.35 src/sys/arch/arm/cortex/gicv3.c:1.36
--- src/sys/arch/arm/cortex/gicv3.c:1.35 Tue Nov 24 23:31:56 2020
+++ src/sys/arch/arm/cortex/gicv3.c Fri Dec 4 21:39:26 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.35 2020/11/24 23:31:56 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.36 2020/12/04 21:39:26 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.35 2020/11/24 23:31:56 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.36 2020/12/04 21:39:26 jmcneill Exp $");
#include
#include
@@ -59,6 +59,8 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#define IPL_TO_PRIORITY(sc, ipl) (((0xff - (ipl)) << (sc)->sc_priority_shift) & 0xff)
#define IPL_TO_PMR(sc, ipl) (((0xff - (ipl)) << (sc)->sc_pmr_shift) & 0xff)
+#define GIC_SUPPORTS_1OFN(sc) (((sc)->sc_gicd_typer & GICD_TYPER_No1N) == 0)
+
#define GIC_PRIO_SHIFT_NS 4
#define GIC_PRIO_SHIFT_S 3
@@ -186,11 +188,13 @@ gicv3_establish_irq(struct pic_softc *pi
gicr_write_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4), ipriority);
}
} else {
- if (is->is_mpsafe) {
- /* Route MP-safe interrupts to all participating PEs */
+ /*
+ * If 1 of N SPI routing is supported, route MP-safe interrupts to all
+ * participating PEs. Otherwise, just route to the primary PE.
+ */
+ if (is->is_mpsafe && GIC_SUPPORTS_1OFN(sc)) {
irouter = GICD_IROUTER_Interrupt_Routing_mode;
} else {
- /* Route non-MP-safe interrupts to the primary PE only */
irouter = sc->sc_irouter[0];
}
gicd_write_8(sc, GICD_IROUTER(is->is_irq), irouter);
@@ -482,12 +486,13 @@ gicv3_set_affinity(struct pic_softc *pic
return EINVAL;
const int set = kcpuset_countset(affinity);
- if (set == ncpu)
- irouter = GICD_IROUTER_Interrupt_Routing_mode;
- else if (set == 1)
+ if (set == 1) {
irouter = sc->sc_irouter[kcpuset_ffs(affinity) - 1];
- else
+ } else if (set == ncpu && GIC_SUPPORTS_1OFN(sc)) {
+ irouter = GICD_IROUTER_Interrupt_Routing_mode;
+ } else {
return EINVAL;
+ }
gicd_write_8(sc, GICD_IROUTER(irq), irouter);
@@ -820,7 +825,6 @@ gicv3_quirk_rockchip_rk3399(struct gicv3
int
gicv3_init(struct gicv3_softc *sc)
{
- const uint32_t gicd_typer = gicd_read_4(sc, GICD_TYPER);
int n;
KASSERT(CPU_IS_PRIMARY(curcpu()));
@@ -830,6 +834,8 @@ gicv3_init(struct gicv3_softc *sc)
for (n = 0; n < MAXCPUS; n++)
sc->sc_irouter[n] = UINT64_MAX;
+ sc->sc_gicd_typer = gicd_read_4(sc, GICD_TYPER);
+
/*
* We don't alwayst have a consistent view of priorities between the
* CPU interface (ICC_PMR_EL1) and the GICD/GICR registers. Detect
@@ -855,14 +861,14 @@ gicv3_init(struct gicv3_softc *sc)
sc->sc_quirks);
sc->sc_pic.pic_ops = _picops;
- sc->sc_pic.pic_maxsources = GICD_TYPER_LINES(gicd_typer);
+ sc->sc_pic.pic_maxsources = GICD_TYPER_LINES(sc->sc_gicd_typer);
snprintf(sc->sc_pic.pic_name, sizeof(sc->sc_pic.pic_name), "gicv3");
#ifdef MULTIPROCESSOR
sc->sc_pic.pic_cpus = kcpuset_running;
#endif
pic_add(>sc_pic, 0);
- if ((gicd_typer & GICD_TYPER_LPIS) != 0) {
+ if ((sc->sc_gicd_typer & GICD_TYPER_LPIS) != 0) {
sc->sc_lpi.pic_ops = _lpiops;
sc->sc_lpi.pic_maxsources = 8192; /* Min. required by GICv3 spec */
snprintf(sc->sc_lpi.pic_name, sizeof(sc->sc_lpi.pic_name), "gicv3-lpi");
@@ -893,7 +899,7 @@ gicv3_init(struct gicv3_softc *sc)
gicv3_dist_enable(sc);
gicv3_cpu_init(>sc_pic, curcpu());
- if ((gicd_typer & GICD_TYPER_LPIS) != 0)
+ if ((sc->sc_gicd_typer & GICD_TYPER_LPIS) != 0)
gicv3_lpi_cpu_init(>sc_lpi, curcpu());
#ifdef MULTIPROCESSOR
Index: src/sys/arch/arm/cortex/gicv3.h
diff -u src/sys/arch/arm/cortex/gicv3.h:1.9 src/sys/arch/arm/cortex/gicv3.h:1.10
--- src/sys/arch/arm/cortex/gicv3.h:1.9 Tue Nov 24 23:31:56 2020
+++ src/sys/arch/arm/cortex/gicv3.h Fri Dec 4 21:39:26 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.h,v 1.9 2020/11/24 23:31:56 jmcneill Exp $ */
+/* $NetBSD: gicv3.h,v 1.10 2020/12/04 21:39:26 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -64,6 +64,8 @@ struct gicv3_softc {
u_int sc_quirks;
#define
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sat Nov 28 14:29:02 UTC 2020 Modified Files: src/sys/arch/arm/cortex: armperiph.c Log Message: Fix build To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/cortex/armperiph.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/armperiph.c diff -u src/sys/arch/arm/cortex/armperiph.c:1.16 src/sys/arch/arm/cortex/armperiph.c:1.17 --- src/sys/arch/arm/cortex/armperiph.c:1.16 Tue Sep 29 19:58:50 2020 +++ src/sys/arch/arm/cortex/armperiph.c Sat Nov 28 14:29:02 2020 @@ -32,7 +32,7 @@ #include -__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.16 2020/09/29 19:58:50 jmcneill Exp $"); +__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.17 2020/11/28 14:29:02 skrll Exp $"); #include #include @@ -43,6 +43,7 @@ __KERNEL_RCSID(1, "$NetBSD: armperiph.c, #include #include #include +#include static int armperiph_match(device_t, cfdata_t, void *); static void armperiph_attach(device_t, device_t, void *);
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Nov 22 20:17:39 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Fix interrupt priorities on N1 SDP.
The GICv3 architecture specification is not clear on the NS view of
priority registers, and there doesn't seem to be any consistency in how
these are implemented in both real and emulated environments.
The previous fix for this issue was meant to detect what we thought at the
time was a bug on the Rockchip RK3399. At that time the theory was somehow
EL1 has a secure view of the hardware, and this is causing us to have the
wrong view of IPRIORITYRn based on IHI0069F section 4.8.6 "Software
accesses of interrupt priority". But it turns out that this is not the
full picture. While I was able to confirm that yes, we do have secure
access to the GIC on RK3399 from EL1, the view of IPRIORITYRn differs
depending on whether you are using the Rockchip TF-A as included with
https://github.com/ayufan-rock64/linux-u-boot (shifted view), or mainline
TF-A from pkgsrc (unshifted view).
So to detect this quirk, we need three things: A method to detect if we
have S access to GIC registers, a method to see how many PMR bits are
implemented, and a method to see how many IPRIORITYRn bits are implemented.
To detect S access, we can try to toggle GICD_CTRL.EnableGrp1S. This bit
is either RES0 (security extensions not implemented), RAZ/WI (non-secure
access in two security state systems) or RW (secure access in two security
state systems).
To read the number of PMR and IPRIORITYRn bits supported, we can write all
1s to the register fields and read them back.
For the RK3399 (Rockchip TF-A) quirk, we assume a shifted view of
IPRIORITYRn if we have detected S accesses, and the PMR and IPRIORITYRn
values differ. The S access test is required because some real hardware
implementations (Ampere eMAG) were observed to report different PMR and
IPRIORITYRn masks, but present an unshifted view of IPRIORITYRn.
During testing, I also discovered that QEMU 5.1 requires this shifted view
workaround as well -- as far as I can tell, this is a QEMU bug. We can't
detect it the same way as RK3399 because security is disabled in the
emulated GIC, and the PMR and IPRIORITYRn tests both return 0xff! So now
if the GICv3 driver sees this configuration, it assumes that the shifted
view is required.
Honestly, this feature is so poorly documented that maybe it is better to
give up on HW priorities and preemption and use a single flat model like
Linux and FreeBSD does.
Tested on Arm N1 SDP, ROCKpro64 (RK3399) with Rockchip and pkgsrc TF-A,
Pinebook Pro (RK3399), Lenovo HR330A (Ampere eMAG), QEMU 5.1 (gic-version=3),
AWS EC2 a1.medium (Graviton).
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.33 src/sys/arch/arm/cortex/gicv3.c:1.34
--- src/sys/arch/arm/cortex/gicv3.c:1.33 Sat Nov 21 11:44:00 2020
+++ src/sys/arch/arm/cortex/gicv3.c Sun Nov 22 20:17:39 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.33 2020/11/21 11:44:00 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.34 2020/11/22 20:17:39 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.33 2020/11/21 11:44:00 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.34 2020/11/22 20:17:39 jmcneill Exp $");
#include
#include
@@ -755,26 +755,37 @@ gicv3_irq_handler(void *frame)
pic_do_pending_ints(I32_bit, oldipl, frame);
}
-static int
-gicv3_detect_pmr_bits(struct gicv3_softc *sc)
+static bool
+gicv3_access_is_secure(struct gicv3_softc *sc)
+{
+ const uint32_t octlr = gicd_read_4(sc, GICD_CTRL);
+ gicd_write_4(sc, GICD_CTRL, octlr ^ GICD_CTRL_EnableGrp1S);
+ const uint32_t nctlr = gicd_read_4(sc, GICD_CTRL);
+ gicd_write_4(sc, GICD_CTRL, octlr);
+
+ return nctlr != octlr;
+}
+
+static uint8_t
+gicv3_get_pmr_bits(struct gicv3_softc *sc)
{
const uint32_t opmr = icc_pmr_read();
- icc_pmr_write(0xbf);
+ icc_pmr_write(0xff);
const uint32_t npmr = icc_pmr_read();
icc_pmr_write(opmr);
- return NBBY - (ffs(npmr) - 1);
+ return npmr;
}
-static int
-gicv3_detect_ipriority_bits(struct gicv3_softc *sc)
+static uint8_t
+gicv3_get_ipriority_bits(struct gicv3_softc *sc)
{
const uint32_t oipriorityr = gicd_read_4(sc, GICD_IPRIORITYRn(8));
gicd_write_4(sc, GICD_IPRIORITYRn(8), oipriorityr | 0xff);
const uint32_t nipriorityr = gicd_read_4(sc, GICD_IPRIORITYRn(8));
gicd_write_4(sc, GICD_IPRIORITYRn(8), oipriorityr);
- return NBBY - (ffs(nipriorityr & 0xff) - 1);
+ return nipriorityr & 0xff;
}
int
@@ -782,6 +793,7 @@ gicv3_init(struct gicv3_softc *sc)
{
const uint32_t gicd_typer = gicd_read_4(sc, GICD_TYPER);
const uint32_t
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 22 19:53:48 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gic_reg.h Log Message: Add GICD_CTRL_EnableGrp1S definition. To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/cortex/gic_reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic_reg.h diff -u src/sys/arch/arm/cortex/gic_reg.h:1.11 src/sys/arch/arm/cortex/gic_reg.h:1.12 --- src/sys/arch/arm/cortex/gic_reg.h:1.11 Thu May 2 23:07:40 2019 +++ src/sys/arch/arm/cortex/gic_reg.h Sun Nov 22 19:53:47 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gic_reg.h,v 1.11 2019/05/02 23:07:40 jmcneill Exp $ */ +/* $NetBSD: gic_reg.h,v 1.12 2020/11/22 19:53:47 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -144,6 +144,7 @@ #define GICD_CTRL_E1NWF __BIT(7) // GICv3 #define GICD_CTRL_DS __BIT(6) // GICv3 #define GICD_CTRL_ARE_NS __BIT(4) // GICv3 +#define GICD_CTRL_EnableGrp1S __BIT(2) // Secure only #define GICD_CTRL_EnableGrp1A __BIT(1) // GICv3 #define GICD_CTRL_Enable __BIT(0)
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Nov 1 14:30:12 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
sc_enabled_sgippi can be updated from any CPU, so use atomic_or/atomic_and
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.31 src/sys/arch/arm/cortex/gicv3.c:1.32
--- src/sys/arch/arm/cortex/gicv3.c:1.31 Sun Nov 1 14:19:42 2020
+++ src/sys/arch/arm/cortex/gicv3.c Sun Nov 1 14:30:12 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.31 2020/11/01 14:19:42 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.32 2020/11/01 14:30:12 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.31 2020/11/01 14:19:42 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.32 2020/11/01 14:30:12 jmcneill Exp $");
#include
#include
@@ -41,6 +41,7 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#include
#include
#include
+#include
#include
@@ -121,7 +122,7 @@ gicv3_unblock_irqs(struct pic_softc *pic
const u_int group = irqbase / 32;
if (group == 0) {
- sc->sc_enabled_sgippi |= mask;
+ atomic_or_32(>sc_enabled_sgippi, mask);
gicr_write_4(sc, ci->ci_gic_redist, GICR_ISENABLER0, mask);
while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTLR) & GICR_CTLR_RWP)
;
@@ -140,7 +141,7 @@ gicv3_block_irqs(struct pic_softc *pic,
const u_int group = irqbase / 32;
if (group == 0) {
- sc->sc_enabled_sgippi &= ~mask;
+ atomic_and_32(>sc_enabled_sgippi, ~mask);
gicr_write_4(sc, ci->ci_gic_redist, GICR_ICENABLER0, mask);
while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTLR) & GICR_CTLR_RWP)
;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 1 14:19:42 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Remove unused __HAVE_PIC_FAST_SOFTINTS block. It never would have worked if enabled.. To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.30 src/sys/arch/arm/cortex/gicv3.c:1.31 --- src/sys/arch/arm/cortex/gicv3.c:1.30 Sun Nov 1 12:13:21 2020 +++ src/sys/arch/arm/cortex/gicv3.c Sun Nov 1 14:19:42 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.30 2020/11/01 12:13:21 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.31 2020/11/01 14:19:42 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -31,7 +31,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.30 2020/11/01 12:13:21 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.31 2020/11/01 14:19:42 jmcneill Exp $"); #include #include @@ -843,13 +843,6 @@ gicv3_init(struct gicv3_softc *sc) if ((gicd_typer & GICD_TYPER_LPIS) != 0) gicv3_lpi_cpu_init(>sc_lpi, curcpu()); -#ifdef __HAVE_PIC_FAST_SOFTINTS - intr_establish_xname(SOFTINT_BIO, IPL_SOFTBIO, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_BIO, "softint bio"); - intr_establish_xname(SOFTINT_CLOCK, IPL_SOFTCLOCK, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_CLOCK, "softint clock"); - intr_establish_xname(SOFTINT_NET, IPL_SOFTNET, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_NET, "softint net"); - intr_establish_xname(SOFTINT_SERIAL, IPL_SOFTSERIAL, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_SERIAL, "softint serial"); -#endif - #ifdef MULTIPROCESSOR intr_establish_xname(IPI_AST, IPL_VM, IST_MPSAFE | IST_EDGE, pic_ipi_ast, (void *)-1, "IPI ast"); intr_establish_xname(IPI_XCALL, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_xcall, (void *)-1, "IPI xcall");
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 1 12:13:21 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Add an isb() barrier after ICC_SGI1R_EL1 write to prevent reordering with subsequent wfi/wfe instructions. Haven't seen this in practice but I would rather be safe here. To generate a diff of this commit: cvs rdiff -u -r1.29 -r1.30 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.29 src/sys/arch/arm/cortex/gicv3.c:1.30 --- src/sys/arch/arm/cortex/gicv3.c:1.29 Sun Nov 1 11:17:20 2020 +++ src/sys/arch/arm/cortex/gicv3.c Sun Nov 1 12:13:21 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.29 2020/11/01 11:17:20 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.30 2020/11/01 12:13:21 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -31,7 +31,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.29 2020/11/01 11:17:20 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.30 2020/11/01 12:13:21 jmcneill Exp $"); #include #include @@ -435,6 +435,7 @@ gicv3_ipi_send(struct pic_softc *pic, co sgir |= ci->ci_gic_sgir; } icc_sgi1r_write(sgir); + isb(); } static void
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 1 11:17:20 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: gicv3_set_priority: ICC_PMR_EL1 is self-synchronizing so no need for isb() here. To generate a diff of this commit: cvs rdiff -u -r1.28 -r1.29 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.28 src/sys/arch/arm/cortex/gicv3.c:1.29 --- src/sys/arch/arm/cortex/gicv3.c:1.28 Sun Nov 1 11:04:55 2020 +++ src/sys/arch/arm/cortex/gicv3.c Sun Nov 1 11:17:20 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.28 2020/11/01 11:04:55 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.29 2020/11/01 11:17:20 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -31,7 +31,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.28 2020/11/01 11:04:55 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.29 2020/11/01 11:17:20 jmcneill Exp $"); #include #include @@ -214,7 +214,6 @@ gicv3_set_priority(struct pic_softc *pic struct gicv3_softc * const sc = PICTOSOFTC(pic); icc_pmr_write(IPL_TO_PMR(sc, ipl)); - isb(); } static void
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Nov 1 11:04:55 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
gicv3_irq_handler: No need to call gicv3_set_priority if we are already at
the desired ipl.
To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.27 src/sys/arch/arm/cortex/gicv3.c:1.28
--- src/sys/arch/arm/cortex/gicv3.c:1.27 Sun Nov 1 11:03:44 2020
+++ src/sys/arch/arm/cortex/gicv3.c Sun Nov 1 11:04:55 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.27 2020/11/01 11:03:44 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.28 2020/11/01 11:04:55 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.27 2020/11/01 11:03:44 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.28 2020/11/01 11:04:55 jmcneill Exp $");
#include
#include
@@ -723,7 +723,7 @@ gicv3_irq_handler(void *frame)
const int ipl = is->is_ipl;
if (__predict_false(ipl < ci->ci_cpl)) {
pic_do_pending_ints(I32_bit, ipl, frame);
- } else {
+ } else if (ci->ci_cpl != ipl) {
gicv3_set_priority(pic, ipl);
ci->ci_cpl = ipl;
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Nov 1 11:03:44 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
gicv3_ipi_send: simplify logic in kcp != NULL case given that we know that
the kcpuset will only ever contain one cpu.
To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.26 src/sys/arch/arm/cortex/gicv3.c:1.27
--- src/sys/arch/arm/cortex/gicv3.c:1.26 Fri Oct 30 18:54:36 2020
+++ src/sys/arch/arm/cortex/gicv3.c Sun Nov 1 11:03:44 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.26 2020/10/30 18:54:36 skrll Exp $ */
+/* $NetBSD: gicv3.c,v 1.27 2020/11/01 11:03:44 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.26 2020/10/30 18:54:36 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.27 2020/11/01 11:03:44 jmcneill Exp $");
#include
#include
@@ -419,38 +419,23 @@ gicv3_cpu_init(struct pic_softc *pic, st
static void
gicv3_ipi_send(struct pic_softc *pic, const kcpuset_t *kcp, u_long ipi)
{
- CPU_INFO_ITERATOR cii;
struct cpu_info *ci;
- uint64_t intid, aff, targets;
+ uint64_t sgir;
- intid = __SHIFTIN(ipi, ICC_SGIR_EL1_INTID);
+ sgir = __SHIFTIN(ipi, ICC_SGIR_EL1_INTID);
if (kcp == NULL) {
/* Interrupts routed to all PEs, excluding "self" */
if (ncpu == 1)
return;
- icc_sgi1r_write(intid | ICC_SGIR_EL1_IRM);
+ sgir |= ICC_SGIR_EL1_IRM;
} else {
- /* Interrupts routed to specific PEs */
- aff = 0;
- targets = 0;
- for (CPU_INFO_FOREACH(cii, ci)) {
- if (!kcpuset_isset(kcp, cpu_index(ci)))
-continue;
- if ((ci->ci_gic_sgir & ICC_SGIR_EL1_Aff) != aff) {
-if (targets != 0) {
- icc_sgi1r_write(intid | aff | targets);
- isb();
- targets = 0;
-}
-aff = (ci->ci_gic_sgir & ICC_SGIR_EL1_Aff);
- }
- targets |= (ci->ci_gic_sgir & ICC_SGIR_EL1_TargetList);
- }
- if (targets != 0) {
- icc_sgi1r_write(intid | aff | targets);
- isb();
- }
+ /* Interrupt to exactly one PE */
+ ci = cpu_lookup(kcpuset_ffs(kcp) - 1);
+ if (ci == curcpu())
+ return;
+ sgir |= ci->ci_gic_sgir;
}
+ icc_sgi1r_write(sgir);
}
static void
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: ryo Date: Thu Sep 24 08:50:09 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: need to swap on big endian machines. "The ITS command queue uses a little endian memory order model." (GIC Architecture Specification) To generate a diff of this commit: cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.27 src/sys/arch/arm/cortex/gicv3_its.c:1.28 --- src/sys/arch/arm/cortex/gicv3_its.c:1.27 Thu Feb 13 02:12:06 2020 +++ src/sys/arch/arm/cortex/gicv3_its.c Thu Sep 24 08:50:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.27 2020/02/13 02:12:06 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.28 2020/09/24 08:50:09 ryo Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.27 2020/02/13 02:12:06 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.28 2020/09/24 08:50:09 ryo Exp $"); #include #include @@ -118,7 +118,13 @@ gits_command(struct gicv3_its *its, cons cwriter = gits_read_8(its, GITS_CWRITER); woff = cwriter & GITS_CWRITER_Offset; +#if _BYTE_ORDER == _BIG_ENDIAN + uint64_t *dw = (uint64_t *)(its->its_cmd.base + woff); + for (int i = 0; i < __arraycount(cmd->dw); i++) + dw[i] = htole64(cmd->dw[i]); +#else memcpy(its->its_cmd.base + woff, cmd->dw, sizeof(cmd->dw)); +#endif bus_dmamap_sync(its->its_dmat, its->its_cmd.map, woff, sizeof(cmd->dw), BUS_DMASYNC_PREWRITE); woff += sizeof(cmd->dw);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Mon Jul 27 18:36:23 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: Remove CPU ID test in armgic_match. Perfectly normal to have GIC in non-Cortex cores. To generate a diff of this commit: cvs rdiff -u -r1.40 -r1.41 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic.c diff -u src/sys/arch/arm/cortex/gic.c:1.40 src/sys/arch/arm/cortex/gic.c:1.41 --- src/sys/arch/arm/cortex/gic.c:1.40 Sun Jul 12 13:33:44 2020 +++ src/sys/arch/arm/cortex/gic.c Mon Jul 27 18:36:23 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gic.c,v 1.40 2020/07/12 13:33:44 skrll Exp $ */ +/* $NetBSD: gic.c,v 1.41 2020/07/27 18:36:23 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -34,7 +34,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.40 2020/07/12 13:33:44 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.41 2020/07/27 18:36:23 jmcneill Exp $"); #include #include @@ -571,8 +571,6 @@ armgic_match(device_t parent, cfdata_t c if (strcmp(cf->cf_name, mpcaa->mpcaa_name) != 0) return 0; - if (!CPU_ID_CORTEX_P(cputype) || CPU_ID_CORTEX_A8_P(cputype)) - return 0; return 1; }
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Sun Jul 12 13:33:44 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Avoid undefined behaviour. Detected by KUBSAN.
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.39 src/sys/arch/arm/cortex/gic.c:1.40
--- src/sys/arch/arm/cortex/gic.c:1.39 Mon Apr 13 12:14:04 2020
+++ src/sys/arch/arm/cortex/gic.c Sun Jul 12 13:33:44 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.39 2020/04/13 12:14:04 jmcneill Exp $ */
+/* $NetBSD: gic.c,v 1.40 2020/07/12 13:33:44 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.39 2020/04/13 12:14:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.40 2020/07/12 13:33:44 skrll Exp $");
#include
#include
@@ -430,11 +430,11 @@ armgic_establish_irq(struct pic_softc *p
* There are 16 irqs per CFG register. 10=EDGE 00=LEVEL
*/
uint32_t new_cfg = cfg;
- uint32_t old_cfg = (cfg >> twopair_shift) & 3;
- if (is->is_type == IST_LEVEL && (old_cfg & 2) != 0) {
- new_cfg &= ~(3 << twopair_shift);
+ uint32_t old_cfg = (cfg >> twopair_shift) & __BITS(1, 0);
+ if (is->is_type == IST_LEVEL && (old_cfg & __BIT(1)) != 0) {
+ new_cfg &= ~(__BITS(1, 0) << twopair_shift);
} else if (is->is_type == IST_EDGE && (old_cfg & 2) == 0) {
- new_cfg |= 2 << twopair_shift;
+ new_cfg |= __BIT(1) << twopair_shift;
}
if (new_cfg != cfg) {
gicd_write(sc, cfg_reg, new_cfg);
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Thu May 7 16:20:40 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c gic_v2m.h
Log Message:
Do not store a pointer to the passed in struct pci_attach_args
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/cortex/gic_v2m.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/gic_v2m.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_v2m.c
diff -u src/sys/arch/arm/cortex/gic_v2m.c:1.8 src/sys/arch/arm/cortex/gic_v2m.c:1.9
--- src/sys/arch/arm/cortex/gic_v2m.c:1.8 Mon Dec 2 03:06:51 2019
+++ src/sys/arch/arm/cortex/gic_v2m.c Thu May 7 16:20:40 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.c,v 1.8 2019/12/02 03:06:51 msaitoh Exp $ */
+/* $NetBSD: gic_v2m.c,v 1.9 2020/05/07 16:20:40 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.8 2019/12/02 03:06:51 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.9 2020/05/07 16:20:40 jmcneill Exp $");
#include
#include
@@ -66,6 +66,7 @@ static int
gic_v2m_msi_alloc_spi(struct gic_v2m_frame *frame, int count,
const struct pci_attach_args *pa)
{
+ struct pci_attach_args *new_pa;
int spi, n;
for (spi = frame->frame_base;
@@ -75,8 +76,11 @@ gic_v2m_msi_alloc_spi(struct gic_v2m_fra
if (frame->frame_pa[spi + n] != NULL)
goto next_spi;
- for (n = 0; n < count; n++)
-frame->frame_pa[spi + n] = pa;
+ for (n = 0; n < count; n++) {
+new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP);
+memcpy(new_pa, pa, sizeof(*new_pa));
+frame->frame_pa[spi + n] = new_pa;
+ }
return spi;
}
@@ -90,7 +94,13 @@ next_spi:
static void
gic_v2m_msi_free_spi(struct gic_v2m_frame *frame, int spi)
{
+ struct pci_attach_args *pa;
+
+ pa = frame->frame_pa[spi];
frame->frame_pa[spi] = NULL;
+
+ if (pa != NULL)
+ kmem_free(pa, sizeof(*pa));
}
static int
Index: src/sys/arch/arm/cortex/gic_v2m.h
diff -u src/sys/arch/arm/cortex/gic_v2m.h:1.2 src/sys/arch/arm/cortex/gic_v2m.h:1.3
--- src/sys/arch/arm/cortex/gic_v2m.h:1.2 Mon Oct 14 11:00:13 2019
+++ src/sys/arch/arm/cortex/gic_v2m.h Thu May 7 16:20:40 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.h,v 1.2 2019/10/14 11:00:13 jmcneill Exp $ */
+/* $NetBSD: gic_v2m.h,v 1.3 2020/05/07 16:20:40 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -43,7 +43,7 @@ struct gic_v2m_frame {
uint32_t frame_flags;
#define GIC_V2M_FLAG_GRAVITON 0x01 /* Amazon Graviton quirk */
- const struct pci_attach_args *frame_pa[GICC_IAR_IRQ];
+ struct pci_attach_args *frame_pa[GICC_IAR_IRQ];
struct arm_pci_msi frame_msi;
};
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Mon Apr 13 12:14:56 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Apply similar fix from gic.c that fixed "left shift of 255 by 24 places
cannot be represented in type 'int'" warnings from UBSan.
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.24 src/sys/arch/arm/cortex/gicv3.c:1.25
--- src/sys/arch/arm/cortex/gicv3.c:1.24 Thu Feb 13 02:12:06 2020
+++ src/sys/arch/arm/cortex/gicv3.c Mon Apr 13 12:14:55 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.24 2020/02/13 02:12:06 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.25 2020/04/13 12:14:55 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.24 2020/02/13 02:12:06 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.25 2020/04/13 12:14:55 jmcneill Exp $");
#include
#include
@@ -178,7 +178,7 @@ gicv3_establish_irq(struct pic_softc *pi
gicr_write_4(sc, n, GICR_ICFGRn(is->is_irq / 16), icfg);
ipriority = gicr_read_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4));
- ipriority &= ~(0xff << ipriority_shift);
+ ipriority &= ~(0xffU << ipriority_shift);
ipriority |= (ipriority_val << ipriority_shift);
gicr_write_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4), ipriority);
}
@@ -202,7 +202,7 @@ gicv3_establish_irq(struct pic_softc *pi
/* Update interrupt priority */
ipriority = gicd_read_4(sc, GICD_IPRIORITYRn(is->is_irq / 4));
- ipriority &= ~(0xff << ipriority_shift);
+ ipriority &= ~(0xffU << ipriority_shift);
ipriority |= (ipriority_val << ipriority_shift);
gicd_write_4(sc, GICD_IPRIORITYRn(is->is_irq / 4), ipriority);
}
@@ -277,7 +277,7 @@ gicv3_redist_enable(struct gicv3_softc *
for (o = 0; o < 4; o++, byte_shift += 8) {
struct intrsource * const is = sc->sc_pic.pic_sources[n + o];
if (is == NULL)
-priority |= 0xff << byte_shift;
+priority |= (0xffU << byte_shift);
else {
const u_int ipriority_val = IPL_TO_PRIORITY(sc, is->is_ipl);
priority |= ipriority_val << byte_shift;
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Mon Apr 13 12:14:04 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Fix "left shift of 255 by 24 places cannot be represented in type 'int'"
warning from UBSan.
To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.38 src/sys/arch/arm/cortex/gic.c:1.39
--- src/sys/arch/arm/cortex/gic.c:1.38 Fri Nov 16 23:25:09 2018
+++ src/sys/arch/arm/cortex/gic.c Mon Apr 13 12:14:04 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.38 2018/11/16 23:25:09 jmcneill Exp $ */
+/* $NetBSD: gic.c,v 1.39 2020/04/13 12:14:04 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.38 2018/11/16 23:25:09 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.39 2020/04/13 12:14:04 jmcneill Exp $");
#include
#include
@@ -415,7 +415,7 @@ armgic_establish_irq(struct pic_softc *p
* There are 4 irqs per TARGETS register. For now bind
* to the primary cpu.
*/
- targets &= ~(0xff << byte_shift);
+ targets &= ~(0xffU << byte_shift);
#if 0
#ifdef MULTIPROCESSOR
if (is->is_mpsafe) {
@@ -455,7 +455,7 @@ armgic_establish_irq(struct pic_softc *p
*/
const bus_size_t priority_reg = GICD_IPRIORITYRn(is->is_irq / 4);
uint32_t priority = gicd_read(sc, priority_reg);
- priority &= ~(0xff << byte_shift);
+ priority &= ~(0xffU << byte_shift);
priority |= armgic_ipl_to_priority(is->is_ipl) << byte_shift;
gicd_write(sc, priority_reg, priority);
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Thu Feb 13 02:12:07 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3_its.c
Log Message:
Make intr affinity work with MSIs again
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.23 src/sys/arch/arm/cortex/gicv3.c:1.24
--- src/sys/arch/arm/cortex/gicv3.c:1.23 Thu Feb 13 00:42:59 2020
+++ src/sys/arch/arm/cortex/gicv3.c Thu Feb 13 02:12:06 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.23 2020/02/13 00:42:59 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.24 2020/02/13 02:12:06 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.23 2020/02/13 00:42:59 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.24 2020/02/13 02:12:06 jmcneill Exp $");
#include
#include
@@ -634,6 +634,7 @@ gicv3_lpi_get_affinity(struct pic_softc
struct gicv3_softc * const sc = LPITOSOFTC(pic);
struct gicv3_lpi_callback *cb;
+ kcpuset_zero(affinity);
LIST_FOREACH(cb, >sc_lpi_callbacks, list)
cb->get_affinity(cb->priv, irq, affinity);
}
@@ -647,11 +648,11 @@ gicv3_lpi_set_affinity(struct pic_softc
LIST_FOREACH(cb, >sc_lpi_callbacks, list) {
error = cb->set_affinity(cb->priv, irq, affinity);
- if (error)
+ if (error != EPASSTHROUGH)
return error;
}
- return error;
+ return EINVAL;
}
#endif
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.26 src/sys/arch/arm/cortex/gicv3_its.c:1.27
--- src/sys/arch/arm/cortex/gicv3_its.c:1.26 Thu Feb 13 00:42:59 2020
+++ src/sys/arch/arm/cortex/gicv3_its.c Thu Feb 13 02:12:06 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.26 2020/02/13 00:42:59 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.27 2020/02/13 02:12:06 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.26 2020/02/13 00:42:59 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.27 2020/02/13 02:12:06 jmcneill Exp $");
#include
#include
@@ -806,7 +806,6 @@ gicv3_its_get_affinity(void *priv, size_
struct gicv3_its * const its = priv;
struct cpu_info *ci;
- kcpuset_zero(affinity);
ci = its->its_targets[irq];
if (ci)
kcpuset_set(affinity, cpu_index(ci));
@@ -825,7 +824,7 @@ gicv3_its_set_affinity(void *priv, size_
pa = its->its_pa[irq];
if (pa == NULL)
- return EINVAL;
+ return EPASSTHROUGH;
ci = cpu_lookup(kcpuset_ffs(affinity) - 1);
its->its_targets[irq] = ci;
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Thu Feb 13 00:42:59 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h gicv3_its.c
Log Message:
Since all ITS instances share a common LPI configuration table, used a
shared vmem arena to allocate pic irqs. Idea from FreeBSD.
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/gicv3.h
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.22 src/sys/arch/arm/cortex/gicv3.c:1.23
--- src/sys/arch/arm/cortex/gicv3.c:1.22 Tue Dec 24 09:12:56 2019
+++ src/sys/arch/arm/cortex/gicv3.c Thu Feb 13 00:42:59 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.22 2019/12/24 09:12:56 skrll Exp $ */
+/* $NetBSD: gicv3.c,v 1.23 2020/02/13 00:42:59 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.22 2019/12/24 09:12:56 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.23 2020/02/13 00:42:59 jmcneill Exp $");
#include
#include
@@ -40,6 +40,7 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#include
#include
#include
+#include
#include
@@ -828,6 +829,11 @@ gicv3_init(struct gicv3_softc *sc)
snprintf(sc->sc_lpi.pic_name, sizeof(sc->sc_lpi.pic_name), "gicv3-lpi");
pic_add(>sc_lpi, GIC_LPI_BASE);
+ sc->sc_lpi_pool = vmem_create("gicv3-lpi", 0, sc->sc_lpi.pic_maxsources,
+ 1, NULL, NULL, NULL, 0, VM_SLEEP, IPL_HIGH);
+ if (sc->sc_lpi_pool == NULL)
+ panic("failed to create gicv3 lpi pool\n");
+
gicv3_lpi_init(sc);
}
Index: src/sys/arch/arm/cortex/gicv3.h
diff -u src/sys/arch/arm/cortex/gicv3.h:1.7 src/sys/arch/arm/cortex/gicv3.h:1.8
--- src/sys/arch/arm/cortex/gicv3.h:1.7 Sun Jun 30 11:11:38 2019
+++ src/sys/arch/arm/cortex/gicv3.h Thu Feb 13 00:42:59 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.h,v 1.7 2019/06/30 11:11:38 jmcneill Exp $ */
+/* $NetBSD: gicv3.h,v 1.8 2020/02/13 00:42:59 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -30,6 +30,7 @@
#define _ARM_CORTEX_GICV3_H
#include
+#include
struct gicv3_dma {
bus_dma_segment_t segs[1];
@@ -73,6 +74,9 @@ struct gicv3_softc {
/* LPI pending tables */
struct gicv3_dma sc_lpipend[MAXCPUS];
+ /* LPI IDs */
+ vmem_t *sc_lpi_pool;
+
/* Unique identifier for PEs */
u_int sc_processor_id[MAXCPUS];
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.25 src/sys/arch/arm/cortex/gicv3_its.c:1.26
--- src/sys/arch/arm/cortex/gicv3_its.c:1.25 Sat Feb 1 15:33:48 2020
+++ src/sys/arch/arm/cortex/gicv3_its.c Thu Feb 13 00:42:59 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.25 2020/02/01 15:33:48 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.26 2020/02/13 00:42:59 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.25 2020/02/01 15:33:48 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.26 2020/02/13 00:42:59 jmcneill Exp $");
#include
#include
@@ -284,18 +284,19 @@ gicv3_its_msi_alloc_lpi(struct gicv3_its
const struct pci_attach_args *pa)
{
struct pci_attach_args *new_pa;
- int n;
+ vmem_addr_t n;
- for (n = 0; n < its->its_pic->pic_maxsources; n++) {
- if (its->its_pa[n] == NULL) {
- new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP);
- memcpy(new_pa, pa, sizeof(*new_pa));
- its->its_pa[n] = new_pa;
- return n + its->its_pic->pic_irqbase;
- }
- }
+ KASSERT(its->its_gic->sc_lpi_pool != NULL);
-return -1;
+ if (vmem_alloc(its->its_gic->sc_lpi_pool, 1, VM_INSTANTFIT|VM_SLEEP, ) != 0)
+ return -1;
+
+ KASSERT(its->its_pa[n] == NULL);
+
+ new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP);
+ memcpy(new_pa, pa, sizeof(*new_pa));
+ its->its_pa[n] = new_pa;
+ return n + its->its_pic->pic_irqbase;
}
static void
@@ -303,11 +304,14 @@ gicv3_its_msi_free_lpi(struct gicv3_its
{
struct pci_attach_args *pa;
+ KASSERT(its->its_gic->sc_lpi_pool != NULL);
KASSERT(lpi >= its->its_pic->pic_irqbase);
pa = its->its_pa[lpi - its->its_pic->pic_irqbase];
its->its_pa[lpi - its->its_pic->pic_irqbase] = NULL;
kmem_free(pa, sizeof(*pa));
+
+ vmem_free(its->its_gic->sc_lpi_pool, lpi - its->its_pic->pic_irqbase, 1);
}
static uint32_t
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sat Feb 1 15:33:48 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Use kmem_zalloc for its state, fixes possible crash if a driver tries to set affinity before a CPU is online. To generate a diff of this commit: cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.24 src/sys/arch/arm/cortex/gicv3_its.c:1.25 --- src/sys/arch/arm/cortex/gicv3_its.c:1.24 Fri Jan 17 13:54:47 2020 +++ src/sys/arch/arm/cortex/gicv3_its.c Sat Feb 1 15:33:48 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.24 2020/01/17 13:54:47 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.25 2020/02/01 15:33:48 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.24 2020/01/17 13:54:47 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.25 2020/02/01 15:33:48 jmcneill Exp $"); #include #include @@ -846,7 +846,7 @@ gicv3_its_init(struct gicv3_softc *sc, b if ((typer & GITS_TYPER_Physical) == 0) return ENXIO; - its = kmem_alloc(sizeof(*its), KM_SLEEP); + its = kmem_zalloc(sizeof(*its), KM_SLEEP); its->its_id = its_id; its->its_bst = sc->sc_bst; its->its_bsh = bsh;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Fri Jan 17 13:54:47 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Set msi_id to its_id To generate a diff of this commit: cvs rdiff -u -r1.23 -r1.24 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.23 src/sys/arch/arm/cortex/gicv3_its.c:1.24 --- src/sys/arch/arm/cortex/gicv3_its.c:1.23 Tue Dec 24 09:13:22 2019 +++ src/sys/arch/arm/cortex/gicv3_its.c Fri Jan 17 13:54:47 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.23 2019/12/24 09:13:22 skrll Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.24 2020/01/17 13:54:47 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.23 2019/12/24 09:13:22 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.24 2020/01/17 13:54:47 jmcneill Exp $"); #include #include @@ -873,6 +873,7 @@ gicv3_its_init(struct gicv3_softc *sc, b gicv3_its_cpu_init(its, curcpu()); msi = >its_msi; + msi->msi_id = its_id; msi->msi_dev = sc->sc_dev; msi->msi_priv = its; msi->msi_alloc = gicv3_its_msi_alloc;
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Tue Dec 24 09:13:23 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Traiing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.22 src/sys/arch/arm/cortex/gicv3_its.c:1.23
--- src/sys/arch/arm/cortex/gicv3_its.c:1.22 Mon Dec 2 03:06:51 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c Tue Dec 24 09:13:22 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.22 2019/12/02 03:06:51 msaitoh Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.23 2019/12/24 09:13:22 skrll Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.22 2019/12/02 03:06:51 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.23 2019/12/24 09:13:22 skrll Exp $");
#include
#include
@@ -297,7 +297,7 @@ gicv3_its_msi_alloc_lpi(struct gicv3_its
return -1;
}
-
+
static void
gicv3_its_msi_free_lpi(struct gicv3_its *its, int lpi)
{
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Tue Dec 24 09:12:56 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Traiing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.21 src/sys/arch/arm/cortex/gicv3.c:1.22
--- src/sys/arch/arm/cortex/gicv3.c:1.21 Thu Sep 5 13:33:11 2019
+++ src/sys/arch/arm/cortex/gicv3.c Tue Dec 24 09:12:56 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.21 2019/09/05 13:33:11 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.22 2019/12/24 09:12:56 skrll Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.21 2019/09/05 13:33:11 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.22 2019/12/24 09:12:56 skrll Exp $");
#include
#include
@@ -348,7 +348,7 @@ gicv3_find_redist(struct gicv3_softc *sc
static uint64_t
gicv3_sgir(struct gicv3_softc *sc)
{
- const uint64_t cpu_identity = gicv3_cpu_identity();
+ const uint64_t cpu_identity = gicv3_cpu_identity();
const u_int aff0 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff0);
const u_int aff1 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff1);
@@ -358,7 +358,7 @@ gicv3_sgir(struct gicv3_softc *sc)
return __SHIFTIN(__BIT(aff0), ICC_SGIR_EL1_TargetList) |
__SHIFTIN(aff1, ICC_SGIR_EL1_Aff1) |
__SHIFTIN(aff2, ICC_SGIR_EL1_Aff2) |
- __SHIFTIN(aff3, ICC_SGIR_EL1_Aff3);
+ __SHIFTIN(aff3, ICC_SGIR_EL1_Aff3);
}
static void
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Thu May 2 23:07:40 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gic_reg.h Log Message: Fix definition of GICD_IROUTER; the input to this macro is the INTID, which can be a value between 32 and 1019. To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/cortex/gic_reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic_reg.h diff -u src/sys/arch/arm/cortex/gic_reg.h:1.10 src/sys/arch/arm/cortex/gic_reg.h:1.11 --- src/sys/arch/arm/cortex/gic_reg.h:1.10 Sat Nov 24 15:40:57 2018 +++ src/sys/arch/arm/cortex/gic_reg.h Thu May 2 23:07:40 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: gic_reg.h,v 1.10 2018/11/24 15:40:57 skrll Exp $ */ +/* $NetBSD: gic_reg.h,v 1.11 2019/05/02 23:07:40 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -138,7 +138,7 @@ #define GICD_SGIR 0xF00 // Software Generated Interrupt Register #define GICD_CPENDSGIR(n) (0xF10+4*(n)) // SGI Clear-Pending Registers #define GICD_SPENDSGIR(n) (0xF20+4*(n)) // SGI Set-Pending Registers -#define GICD_IROUTER(n) (0x6100+8*(n)) // Interrupt Routing Registers +#define GICD_IROUTER(n) (0x6000+8*(n)) // Interrupt Routing Registers #define GICD_CTRL_RWP __BIT(31) // GICv3 #define GICD_CTRL_E1NWF __BIT(7) // GICv3
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Wed Jan 30 02:01:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Fix bitmask in A64 errata workaround and write cval instead of tval on A64
To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.38 src/sys/arch/arm/cortex/gtmr.c:1.39
--- src/sys/arch/arm/cortex/gtmr.c:1.38 Thu Nov 15 17:15:52 2018
+++ src/sys/arch/arm/cortex/gtmr.c Wed Jan 30 02:01:58 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.38 2018/11/15 17:15:52 jmcneill Exp $ */
+/* $NetBSD: gtmr.c,v 1.39 2019/01/30 02:01:58 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.38 2018/11/15 17:15:52 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.39 2019/01/30 02:01:58 jmcneill Exp $");
#include
#include
@@ -171,8 +171,8 @@ gtmr_read_cntvct(struct gtmr_softc *sc)
u_int bits;
do {
val = gtmr_cntvct_read();
- bits = val & __BITS(10,0);
- } while (bits == 0 || bits == __BITS(10,0));
+ bits = val & __BITS(9,0);
+ } while (bits == 0 || bits == __BITS(9,0));
return val;
}
@@ -298,7 +298,12 @@ gtmr_intr(void *arg)
} else {
delta = 0;
}
- gtmr_cntv_tval_write(sc->sc_autoinc - delta);
+
+ if (ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) {
+ gtmr_cntv_cval_write(now + sc->sc_autoinc - delta);
+ } else {
+ gtmr_cntv_tval_write(sc->sc_autoinc - delta);
+ }
ci->ci_lastintr = now;
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Jan 19 20:52:26 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: pl310.c
Log Message:
Remove hard requirement for "offset" property on Cortex-A5. This is not
required w/ FDT.
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/cortex/pl310.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/pl310.c
diff -u src/sys/arch/arm/cortex/pl310.c:1.18 src/sys/arch/arm/cortex/pl310.c:1.19
--- src/sys/arch/arm/cortex/pl310.c:1.18 Wed Jun 20 08:03:55 2018
+++ src/sys/arch/arm/cortex/pl310.c Sat Jan 19 20:52:26 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pl310.c,v 1.18 2018/06/20 08:03:55 hkenken Exp $ */
+/* $NetBSD: pl310.c,v 1.19 2019/01/19 20:52:26 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.18 2018/06/20 08:03:55 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.19 2019/01/19 20:52:26 jmcneill Exp $");
#include
#include
@@ -140,17 +140,8 @@ arml2cc_attach(device_t parent, device_t
aprint_naive("\n");
- if (!prop_dictionary_get_uint32(dict, "offset", )) {
- if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) {
- /*
- * PL310 on Cortex-A5 is external to PERIPHBASE, so
- * "offset" property is required.
- */
- aprint_normal(": not configured\n");
- return;
- }
+ if (!prop_dictionary_get_uint32(dict, "offset", ))
off = mpcaa->mpcaa_off1;
- }
arml2cc_sc = sc;
sc->sc_dev = self;
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jakllsch
Date: Fri Dec 7 17:56:42 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c
Log Message:
fix a paste-o in a panic message
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/cortex/gic_v2m.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_v2m.c
diff -u src/sys/arch/arm/cortex/gic_v2m.c:1.4 src/sys/arch/arm/cortex/gic_v2m.c:1.5
--- src/sys/arch/arm/cortex/gic_v2m.c:1.4 Fri Nov 16 15:06:21 2018
+++ src/sys/arch/arm/cortex/gic_v2m.c Fri Dec 7 17:56:41 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.c,v 1.4 2018/11/16 15:06:21 jmcneill Exp $ */
+/* $NetBSD: gic_v2m.c,v 1.5 2018/12/07 17:56:41 jakllsch Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.4 2018/11/16 15:06:21 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.5 2018/12/07 17:56:41 jakllsch Exp $");
#include
#include
@@ -128,7 +128,7 @@ gic_v2m_msi_disable(struct gic_v2m_frame
int off;
if (!pci_get_capability(pc, tag, PCI_CAP_MSI, , NULL))
- panic("gic_v2m_msi_enable: device is not MSI-capable");
+ panic("gic_v2m_msi_disable: device is not MSI-capable");
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Wed Nov 28 22:54:11 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h
Log Message:
Allow non-power of 2 counts, and support alloc/release/alloc patterns for a
device as long as the ITT size is sufficient
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/cortex/gicv3_its.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/gicv3_its.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.8 src/sys/arch/arm/cortex/gicv3_its.c:1.9
--- src/sys/arch/arm/cortex/gicv3_its.c:1.8 Sat Nov 24 15:40:57 2018
+++ src/sys/arch/arm/cortex/gicv3_its.c Wed Nov 28 22:54:11 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.8 2018/11/24 15:40:57 skrll Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.9 2018/11/28 22:54:11 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.8 2018/11/24 15:40:57 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.9 2018/11/28 22:54:11 jmcneill Exp $");
#include
#include
@@ -293,22 +293,25 @@ static int
gicv3_its_device_map(struct gicv3_its *its, uint32_t devid, u_int count)
{
struct gicv3_its_device *dev;
+ u_int vectors;
- LIST_FOREACH(dev, >its_devices, dev_list)
- if (dev->dev_id == devid)
- return EEXIST;
-
- const u_int vectors = MAX(2, count);
- if (!powerof2(vectors))
- return EINVAL;
+ vectors = MAX(2, count);
+ while (!powerof2(vectors))
+ vectors++;
const uint64_t typer = gits_read_8(its, GITS_TYPER);
const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1;
const u_int itt_entry_size = __SHIFTOUT(typer, GITS_TYPER_ITT_entry_size) + 1;
const u_int itt_size = roundup(vectors * itt_entry_size, GITS_ITT_ALIGN);
+ LIST_FOREACH(dev, >its_devices, dev_list)
+ if (dev->dev_id == devid) {
+ return itt_size <= dev->dev_size ? 0 : EEXIST;
+ }
+
dev = kmem_alloc(sizeof(*dev), KM_SLEEP);
dev->dev_id = devid;
+ dev->dev_size = itt_size;
gicv3_dma_alloc(its->its_gic, >dev_itt, itt_size, GITS_ITT_ALIGN);
LIST_INSERT_HEAD(>its_devices, dev, dev_list);
Index: src/sys/arch/arm/cortex/gicv3_its.h
diff -u src/sys/arch/arm/cortex/gicv3_its.h:1.3 src/sys/arch/arm/cortex/gicv3_its.h:1.4
--- src/sys/arch/arm/cortex/gicv3_its.h:1.3 Sat Nov 24 22:08:53 2018
+++ src/sys/arch/arm/cortex/gicv3_its.h Wed Nov 28 22:54:11 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.h,v 1.3 2018/11/24 22:08:53 jakllsch Exp $ */
+/* $NetBSD: gicv3_its.h,v 1.4 2018/11/28 22:54:11 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -40,6 +40,7 @@
struct gicv3_its_device {
uint32_t dev_id;
+ u_int dev_size;
struct gicv3_dma dev_itt;
LIST_ENTRY(gicv3_its_device) dev_list;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jakllsch Date: Sat Nov 24 22:08:54 UTC 2018 Modified Files: src/sys/arch/arm/cortex: gicv3_its.h Log Message: include dev/pci/pcivar.h, we use pci_attach_args directly To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/gicv3_its.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.h diff -u src/sys/arch/arm/cortex/gicv3_its.h:1.2 src/sys/arch/arm/cortex/gicv3_its.h:1.3 --- src/sys/arch/arm/cortex/gicv3_its.h:1.2 Sat Nov 10 11:46:31 2018 +++ src/sys/arch/arm/cortex/gicv3_its.h Sat Nov 24 22:08:53 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.h,v 1.2 2018/11/10 11:46:31 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.h,v 1.3 2018/11/24 22:08:53 jakllsch Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,6 +32,8 @@ #ifndef _ARM_CORTEX_GICV3_ITS_H #define _ARM_CORTEX_GICV3_ITS_H +#include + #include #include #include
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Sat Nov 24 15:40:57 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic_reg.h gicv3_its.c
Log Message:
Handle ThunderX errata
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gic_reg.h
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_reg.h
diff -u src/sys/arch/arm/cortex/gic_reg.h:1.9 src/sys/arch/arm/cortex/gic_reg.h:1.10
--- src/sys/arch/arm/cortex/gic_reg.h:1.9 Tue Nov 13 22:25:28 2018
+++ src/sys/arch/arm/cortex/gic_reg.h Sat Nov 24 15:40:57 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_reg.h,v 1.9 2018/11/13 22:25:28 jmcneill Exp $ */
+/* $NetBSD: gic_reg.h,v 1.10 2018/11/24 15:40:57 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -335,6 +335,11 @@
#define GITS_CTLR_ImDe __BIT(1)
#define GITS_CTLR_Enabled __BIT(0)
+#define GITS_IIDR_ProductID __BITS(31,24)
+#define GITS_IIDR_Variant __BITS(19,16)
+#define GITS_IIDR_Revision __BITS(15,12)
+#define GITS_IIDR_Implementor __BITS(11,0)
+
#define GITS_TYPER_VMOVP __BIT(37)
#define GITS_TYPER_CIL __BIT(36)
#define GITS_TYPER_CIDbits __BITS(35,32)
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.7 src/sys/arch/arm/cortex/gicv3_its.c:1.8
--- src/sys/arch/arm/cortex/gicv3_its.c:1.7 Fri Nov 23 16:01:27 2018
+++ src/sys/arch/arm/cortex/gicv3_its.c Sat Nov 24 15:40:57 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.7 2018/11/23 16:01:27 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.8 2018/11/24 15:40:57 skrll Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.7 2018/11/23 16:01:27 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.8 2018/11/24 15:40:57 skrll Exp $");
#include
#include
@@ -56,6 +56,13 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,
#define GITS_ITT_ALIGN 0x100
+/*
+ * IIDR values used for errata
+ */
+#define GITS_IIDR_PID_CAVIUM_THUNDERX 0xa1
+#define GITS_IIDR_IMP_CAVIUM 0x34c
+
+
static inline uint32_t
gits_read_4(struct gicv3_its *its, bus_size_t reg)
{
@@ -594,7 +601,26 @@ gicv3_its_table_init(struct gicv3_softc
int tab;
const uint64_t typer = gits_read_8(its, GITS_TYPER);
- const u_int devbits = __SHIFTOUT(typer, GITS_TYPER_Devbits) + 1;
+
+ /* devbits and innercache defaults */
+ u_int devbits = __SHIFTOUT(typer, GITS_TYPER_Devbits) + 1;
+ u_int innercache = GITS_Cache_NORMAL_NC;
+
+ uint32_t iidr = gits_read_4(its, GITS_IIDR);
+ const uint32_t ctx =
+ __SHIFTIN(GITS_IIDR_IMP_CAVIUM, GITS_IIDR_Implementor) |
+ __SHIFTIN(GITS_IIDR_PID_CAVIUM_THUNDERX, GITS_IIDR_ProductID) |
+ __SHIFTIN(0, GITS_IIDR_Variant);
+ const uint32_t mask =
+ GITS_IIDR_Implementor |
+ GITS_IIDR_ProductID |
+ GITS_IIDR_Variant;
+
+ if ((iidr & mask) == ctx) {
+ devbits = 20; /* 8Mb */
+ innercache = GITS_Cache_DEVICE_nGnRnE;
+ aprint_normal_dev(sc->sc_dev, "Cavium ThunderX errata detected\n");
+ }
for (tab = 0; tab < 8; tab++) {
baser = gits_read_8(its, GITS_BASERn(tab));
@@ -646,11 +672,11 @@ gicv3_its_table_init(struct gicv3_softc
baser &= ~GITS_BASER_Physical_Address;
baser |= its->its_tab[tab].segs[0].ds_addr;
baser &= ~GITS_BASER_InnerCache;
- baser |= __SHIFTIN(GITS_Cache_NORMAL_NC, GITS_BASER_InnerCache);
+ baser |= __SHIFTIN(innercache, GITS_BASER_InnerCache);
baser &= ~GITS_BASER_Shareability;
baser |= __SHIFTIN(GITS_Shareability_NS, GITS_BASER_Shareability);
baser |= GITS_BASER_Valid;
-
+
gits_write_8(its, GITS_BASERn(tab), baser);
}
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Fri Nov 23 16:01:27 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Only allocate what we need for ITT tables
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.6 src/sys/arch/arm/cortex/gicv3_its.c:1.7
--- src/sys/arch/arm/cortex/gicv3_its.c:1.6 Fri Nov 23 11:48:12 2018
+++ src/sys/arch/arm/cortex/gicv3_its.c Fri Nov 23 16:01:27 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.6 2018/11/23 11:48:12 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.7 2018/11/23 16:01:27 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,12 +32,13 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.6 2018/11/23 11:48:12 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.7 2018/11/23 16:01:27 jmcneill Exp $");
#include
#include
#include
#include
+#include
#include
@@ -281,19 +282,23 @@ gicv3_its_devid(pci_chipset_tag_t pc, pc
return (b << 8) | (d << 3) | f;
}
-static void
-gicv3_its_device_map(struct gicv3_its *its, uint32_t devid)
+static int
+gicv3_its_device_map(struct gicv3_its *its, uint32_t devid, u_int count)
{
struct gicv3_its_device *dev;
LIST_FOREACH(dev, >its_devices, dev_list)
if (dev->dev_id == devid)
- return;
+ return EEXIST;
+
+ const u_int vectors = MAX(2, count);
+ if (!powerof2(vectors))
+ return EINVAL;
const uint64_t typer = gits_read_8(its, GITS_TYPER);
const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1;
const u_int itt_entry_size = __SHIFTOUT(typer, GITS_TYPER_ITT_entry_size) + 1;
- const u_int itt_size = roundup2((itt_entry_size * (1 << id_bits)) / NBBY, GITS_ITT_ALIGN);
+ const u_int itt_size = roundup(vectors * itt_entry_size, GITS_ITT_ALIGN);
dev = kmem_alloc(sizeof(*dev), KM_SLEEP);
dev->dev_id = devid;
@@ -305,6 +310,8 @@ gicv3_its_device_map(struct gicv3_its *i
*/
gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, id_bits - 1, true);
gits_wait(its);
+
+ return 0;
}
static void
@@ -414,7 +421,8 @@ gicv3_its_msi_alloc(struct arm_pci_msi *
const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
- gicv3_its_device_map(its, devid);
+ if (gicv3_its_device_map(its, devid, *count) != 0)
+ return NULL;
vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP);
for (n = 0; n < *count; n++) {
@@ -479,7 +487,10 @@ gicv3_its_msix_alloc(struct arm_pci_msi
const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
- gicv3_its_device_map(its, devid);
+ if (gicv3_its_device_map(its, devid, *count) != 0) {
+ bus_space_unmap(bst, bsh, bsz);
+ return NULL;
+ }
vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP);
for (n = 0; n < *count; n++) {
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Fri Nov 23 11:49:04 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Fix LPI pending table size, use correct LPI conf offset in
gicv3_lpi_block_irqs, and set bit[7]=1 for G1NS interrupts when writing to the
LPI configuration table.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.12 src/sys/arch/arm/cortex/gicv3.c:1.13
--- src/sys/arch/arm/cortex/gicv3.c:1.12 Wed Nov 21 11:44:26 2018
+++ src/sys/arch/arm/cortex/gicv3.c Fri Nov 23 11:49:04 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.12 2018/11/21 11:44:26 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.13 2018/11/23 11:49:04 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.12 2018/11/21 11:44:26 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.13 2018/11/23 11:49:04 jmcneill Exp $");
#include
#include
@@ -530,15 +530,14 @@ static void
gicv3_lpi_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask)
{
struct gicv3_softc * const sc = LPITOSOFTC(pic);
- const u_int off = irqbase - pic->pic_irqbase;
int bit;
while ((bit = ffs(mask)) != 0) {
- sc->sc_lpiconf.base[off + bit - 1] &= ~GIC_LPICONF_Enable;
+ sc->sc_lpiconf.base[irqbase + bit - 1] &= ~GIC_LPICONF_Enable;
mask &= ~__BIT(bit - 1);
}
- bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, off, 32, BUS_DMASYNC_PREWRITE);
+ bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, irqbase, 32, BUS_DMASYNC_PREWRITE);
}
static void
@@ -546,7 +545,7 @@ gicv3_lpi_establish_irq(struct pic_softc
{
struct gicv3_softc * const sc = LPITOSOFTC(pic);
- sc->sc_lpiconf.base[is->is_irq] = IPL_TO_PRIORITY(is->is_ipl) | GIC_LPICONF_Res1;
+ sc->sc_lpiconf.base[is->is_irq] = 0x80 | IPL_TO_PRIORITY(is->is_ipl) | GIC_LPICONF_Res1;
bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, is->is_irq, 1, BUS_DMASYNC_PREWRITE);
}
@@ -671,7 +670,7 @@ gicv3_lpi_init(struct gicv3_softc *sc)
/*
* Allocate LPI pending tables
*/
- const bus_size_t lpipend_sz = (sc->sc_lpi.pic_maxsources + sc->sc_lpi.pic_irqbase) / NBBY;
+ const bus_size_t lpipend_sz = sc->sc_lpi.pic_maxsources / NBBY;
for (int cpuindex = 0; cpuindex < ncpu; cpuindex++) {
gicv3_dma_alloc(sc, >sc_lpipend[cpuindex], lpipend_sz, 0x1);
KASSERT((sc->sc_lpipend[cpuindex].segs[0].ds_addr & ~GICR_PENDBASER_Physical_Address) == 0);
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Fri Nov 23 11:48:12 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Fix ITT size, only need to MAPD once per device.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.5 src/sys/arch/arm/cortex/gicv3_its.c:1.6
--- src/sys/arch/arm/cortex/gicv3_its.c:1.5 Thu Nov 22 20:47:37 2018
+++ src/sys/arch/arm/cortex/gicv3_its.c Fri Nov 23 11:48:12 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.5 2018/11/22 20:47:37 jakllsch Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.6 2018/11/23 11:48:12 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.5 2018/11/22 20:47:37 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.6 2018/11/23 11:48:12 jmcneill Exp $");
#include
#include
@@ -281,26 +281,30 @@ gicv3_its_devid(pci_chipset_tag_t pc, pc
return (b << 8) | (d << 3) | f;
}
-static struct gicv3_its_device *
-gicv3_its_device_lookup(struct gicv3_its *its, uint32_t devid)
+static void
+gicv3_its_device_map(struct gicv3_its *its, uint32_t devid)
{
struct gicv3_its_device *dev;
LIST_FOREACH(dev, >its_devices, dev_list)
if (dev->dev_id == devid)
- return dev;
+ return;
const uint64_t typer = gits_read_8(its, GITS_TYPER);
const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1;
const u_int itt_entry_size = __SHIFTOUT(typer, GITS_TYPER_ITT_entry_size) + 1;
- const u_int itt_size = roundup2(itt_entry_size * (1 << id_bits), GITS_ITT_ALIGN);
+ const u_int itt_size = roundup2((itt_entry_size * (1 << id_bits)) / NBBY, GITS_ITT_ALIGN);
dev = kmem_alloc(sizeof(*dev), KM_SLEEP);
dev->dev_id = devid;
gicv3_dma_alloc(its->its_gic, >dev_itt, itt_size, GITS_ITT_ALIGN);
LIST_INSERT_HEAD(>its_devices, dev, dev_list);
- return dev;
+ /*
+ * Map the device to the ITT
+ */
+ gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, id_bits - 1, true);
+ gits_wait(its);
}
static void
@@ -397,7 +401,6 @@ gicv3_its_msi_alloc(struct arm_pci_msi *
{
struct gicv3_its * const its = msi->msi_priv;
struct cpu_info * const ci = cpu_lookup(0);
- struct gicv3_its_device *dev;
pci_intr_handle_t *vectors;
int n, off;
@@ -411,12 +414,7 @@ gicv3_its_msi_alloc(struct arm_pci_msi *
const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
- /*
- * Map device
- */
- dev = gicv3_its_device_lookup(its, devid);
- gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, id_bits - 1, true);
- gits_wait(its);
+ gicv3_its_device_map(its, devid);
vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP);
for (n = 0; n < *count; n++) {
@@ -450,7 +448,6 @@ gicv3_its_msix_alloc(struct arm_pci_msi
{
struct gicv3_its * const its = msi->msi_priv;
struct cpu_info *ci = cpu_lookup(0);
- struct gicv3_its_device *dev;
pci_intr_handle_t *vectors;
bus_space_tag_t bst;
bus_space_handle_t bsh;
@@ -482,12 +479,7 @@ gicv3_its_msix_alloc(struct arm_pci_msi
const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
- /*
- * Map device
- */
- dev = gicv3_its_device_lookup(its, devid);
- gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, id_bits - 1, true);
- gits_wait(its);
+ gicv3_its_device_map(its, devid);
vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP);
for (n = 0; n < *count; n++) {
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jakllsch Date: Thu Nov 22 20:47:38 UTC 2018 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: use correct interrupt index fixes intrctl list from jmcneill@ To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.4 src/sys/arch/arm/cortex/gicv3_its.c:1.5 --- src/sys/arch/arm/cortex/gicv3_its.c:1.4 Wed Nov 21 11:44:26 2018 +++ src/sys/arch/arm/cortex/gicv3_its.c Thu Nov 22 20:47:37 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.4 2018/11/21 11:44:26 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.5 2018/11/22 20:47:37 jakllsch Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.4 2018/11/21 11:44:26 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.5 2018/11/22 20:47:37 jakllsch Exp $"); #include #include @@ -693,7 +693,7 @@ gicv3_its_get_affinity(void *priv, size_ struct cpu_info *ci; kcpuset_zero(affinity); - ci = its->its_targets[irq - its->its_pic->pic_irqbase]; + ci = its->its_targets[irq]; if (ci) kcpuset_set(affinity, cpu_index(ci)); } @@ -709,7 +709,7 @@ gicv3_its_set_affinity(void *priv, size_ if (set != 1) return EINVAL; - pa = its->its_pa[irq - its->its_pic->pic_irqbase]; + pa = its->its_pa[irq]; if (pa == NULL) return EINVAL; @@ -719,7 +719,7 @@ gicv3_its_set_affinity(void *priv, size_ gits_command_movi(its, devid, devid, cpu_index(ci)); gits_command_sync(its, its->its_rdbase[cpu_index(ci)]); - its->its_targets[irq - its->its_pic->pic_irqbase] = ci; + its->its_targets[irq] = ci; return 0; }
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Wed Nov 21 11:44:26 UTC 2018 Modified Files: src/sys/arch/arm/cortex: gicv3.c gicv3_its.c Log Message: kcpuset_ffs returns the cpu number plus one, so make sure to subtract it To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/cortex/gicv3.c cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.11 src/sys/arch/arm/cortex/gicv3.c:1.12 --- src/sys/arch/arm/cortex/gicv3.c:1.11 Sat Nov 17 00:17:54 2018 +++ src/sys/arch/arm/cortex/gicv3.c Wed Nov 21 11:44:26 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.11 2018/11/17 00:17:54 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.12 2018/11/21 11:44:26 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -31,7 +31,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.11 2018/11/17 00:17:54 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.12 2018/11/21 11:44:26 jmcneill Exp $"); #include #include @@ -489,7 +489,7 @@ gicv3_set_affinity(struct pic_softc *pic if (set == ncpu) irouter = GICD_IROUTER_Interrupt_Routing_mode; else if (set == 1) - irouter = sc->sc_irouter[kcpuset_ffs(affinity)]; + irouter = sc->sc_irouter[kcpuset_ffs(affinity) - 1]; else return EINVAL; Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.3 src/sys/arch/arm/cortex/gicv3_its.c:1.4 --- src/sys/arch/arm/cortex/gicv3_its.c:1.3 Fri Nov 16 15:06:21 2018 +++ src/sys/arch/arm/cortex/gicv3_its.c Wed Nov 21 11:44:26 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.3 2018/11/16 15:06:21 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.4 2018/11/21 11:44:26 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.3 2018/11/16 15:06:21 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.4 2018/11/21 11:44:26 jmcneill Exp $"); #include #include @@ -713,7 +713,7 @@ gicv3_its_set_affinity(void *priv, size_ if (pa == NULL) return EINVAL; - ci = cpu_lookup(kcpuset_ffs(affinity)); + ci = cpu_lookup(kcpuset_ffs(affinity) - 1); const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag); gits_command_movi(its, devid, devid, cpu_index(ci));
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sat Nov 17 00:17:54 UTC 2018 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Use intr_establish_xname To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.10 src/sys/arch/arm/cortex/gicv3.c:1.11 --- src/sys/arch/arm/cortex/gicv3.c:1.10 Thu Nov 15 00:01:38 2018 +++ src/sys/arch/arm/cortex/gicv3.c Sat Nov 17 00:17:54 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.10 2018/11/15 00:01:38 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.11 2018/11/17 00:17:54 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -31,7 +31,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.10 2018/11/15 00:01:38 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.11 2018/11/17 00:17:54 jmcneill Exp $"); #include #include @@ -767,23 +767,23 @@ gicv3_init(struct gicv3_softc *sc) gicv3_lpi_cpu_init(>sc_lpi, curcpu()); #ifdef __HAVE_PIC_FAST_SOFTINTS - intr_establish(SOFTINT_BIO, IPL_SOFTBIO, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_BIO); - intr_establish(SOFTINT_CLOCK, IPL_SOFTCLOCK, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_CLOCK); - intr_establish(SOFTINT_NET, IPL_SOFTNET, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_NET); - intr_establish(SOFTINT_SERIAL, IPL_SOFTSERIAL, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_SERIAL); + intr_establish_xname(SOFTINT_BIO, IPL_SOFTBIO, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_BIO, "softint bio"); + intr_establish_xname(SOFTINT_CLOCK, IPL_SOFTCLOCK, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_CLOCK, "softint clock"); + intr_establish_xname(SOFTINT_NET, IPL_SOFTNET, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_NET, "softint net"); + intr_establish_xname(SOFTINT_SERIAL, IPL_SOFTSERIAL, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_SERIAL, "softint serial"); #endif #ifdef MULTIPROCESSOR - intr_establish(IPI_AST, IPL_VM, IST_MPSAFE | IST_EDGE, pic_ipi_ast, (void *)-1); - intr_establish(IPI_XCALL, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_xcall, (void *)-1); - intr_establish(IPI_GENERIC, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_generic, (void *)-1); - intr_establish(IPI_NOP, IPL_VM, IST_MPSAFE | IST_EDGE, pic_ipi_nop, (void *)-1); - intr_establish(IPI_SHOOTDOWN, IPL_SCHED, IST_MPSAFE | IST_EDGE, pic_ipi_shootdown, (void *)-1); + intr_establish_xname(IPI_AST, IPL_VM, IST_MPSAFE | IST_EDGE, pic_ipi_ast, (void *)-1, "IPI ast"); + intr_establish_xname(IPI_XCALL, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_xcall, (void *)-1, "IPI xcall"); + intr_establish_xname(IPI_GENERIC, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_generic, (void *)-1, "IPI generic"); + intr_establish_xname(IPI_NOP, IPL_VM, IST_MPSAFE | IST_EDGE, pic_ipi_nop, (void *)-1, "IPI nop"); + intr_establish_xname(IPI_SHOOTDOWN, IPL_SCHED, IST_MPSAFE | IST_EDGE, pic_ipi_shootdown, (void *)-1, "IPI shootdown"); #ifdef DDB - intr_establish(IPI_DDB, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_ddb, NULL); + intr_establish_xname(IPI_DDB, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_ddb, NULL, "IPI ddb"); #endif #ifdef __HAVE_PREEMPTION - intr_establish(IPI_KPREEMPT, IPL_VM, IST_MPSAFE | IST_EDGE, pic_ipi_kpreempt, (void *)-1); + intr_establish_xname(IPI_KPREEMPT, IPL_VM, IST_MPSAFE | IST_EDGE, pic_ipi_kpreempt, (void *)-1, "IPI kpreempt"); #endif #endif
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Fri Nov 16 23:25:09 UTC 2018 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: Use intr_establish_xname To generate a diff of this commit: cvs rdiff -u -r1.37 -r1.38 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic.c diff -u src/sys/arch/arm/cortex/gic.c:1.37 src/sys/arch/arm/cortex/gic.c:1.38 --- src/sys/arch/arm/cortex/gic.c:1.37 Mon Sep 10 19:43:58 2018 +++ src/sys/arch/arm/cortex/gic.c Fri Nov 16 23:25:09 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gic.c,v 1.37 2018/09/10 19:43:58 jmcneill Exp $ */ +/* $NetBSD: gic.c,v 1.38 2018/11/16 23:25:09 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -34,7 +34,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.37 2018/09/10 19:43:58 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.38 2018/11/16 23:25:09 jmcneill Exp $"); #include #include @@ -677,35 +677,35 @@ armgic_attach(device_t parent, device_t } } #ifdef __HAVE_PIC_FAST_SOFTINTS - intr_establish(SOFTINT_BIO, IPL_SOFTBIO, IST_MPSAFE | IST_EDGE, - pic_handle_softint, (void *)SOFTINT_BIO); - intr_establish(SOFTINT_CLOCK, IPL_SOFTCLOCK, IST_MPSAFE | IST_EDGE, - pic_handle_softint, (void *)SOFTINT_CLOCK); - intr_establish(SOFTINT_NET, IPL_SOFTNET, IST_MPSAFE | IST_EDGE, - pic_handle_softint, (void *)SOFTINT_NET); - intr_establish(SOFTINT_SERIAL, IPL_SOFTSERIAL, IST_MPSAFE | IST_EDGE, - pic_handle_softint, (void *)SOFTINT_SERIAL); + intr_establish_xname(SOFTINT_BIO, IPL_SOFTBIO, IST_MPSAFE | IST_EDGE, + pic_handle_softint, (void *)SOFTINT_BIO, "softint bio"); + intr_establish_xname(SOFTINT_CLOCK, IPL_SOFTCLOCK, IST_MPSAFE | IST_EDGE, + pic_handle_softint, (void *)SOFTINT_CLOCK, "softint clock"); + intr_establish_xname(SOFTINT_NET, IPL_SOFTNET, IST_MPSAFE | IST_EDGE, + pic_handle_softint, (void *)SOFTINT_NET, "softint net"); + intr_establish_xname(SOFTINT_SERIAL, IPL_SOFTSERIAL, IST_MPSAFE | IST_EDGE, + pic_handle_softint, (void *)SOFTINT_SERIAL, "softint serial"); #endif #ifdef MULTIPROCESSOR armgic_cpu_init(>sc_pic, curcpu()); - intr_establish(ARMGIC_SGI_IPIBASE + IPI_AST, IPL_VM, - IST_MPSAFE | IST_EDGE, pic_ipi_ast, (void *)-1); - intr_establish(ARMGIC_SGI_IPIBASE + IPI_XCALL, IPL_HIGH, - IST_MPSAFE | IST_EDGE, pic_ipi_xcall, (void *)-1); - intr_establish(ARMGIC_SGI_IPIBASE + IPI_GENERIC, IPL_HIGH, - IST_MPSAFE | IST_EDGE, pic_ipi_generic, (void *)-1); - intr_establish(ARMGIC_SGI_IPIBASE + IPI_NOP, IPL_VM, - IST_MPSAFE | IST_EDGE, pic_ipi_nop, (void *)-1); - intr_establish(ARMGIC_SGI_IPIBASE + IPI_SHOOTDOWN, IPL_SCHED, - IST_MPSAFE | IST_EDGE, pic_ipi_shootdown, (void *)-1); + intr_establish_xname(ARMGIC_SGI_IPIBASE + IPI_AST, IPL_VM, + IST_MPSAFE | IST_EDGE, pic_ipi_ast, (void *)-1, "IPI ast"); + intr_establish_xname(ARMGIC_SGI_IPIBASE + IPI_XCALL, IPL_HIGH, + IST_MPSAFE | IST_EDGE, pic_ipi_xcall, (void *)-1, "IPI xcall"); + intr_establish_xname(ARMGIC_SGI_IPIBASE + IPI_GENERIC, IPL_HIGH, + IST_MPSAFE | IST_EDGE, pic_ipi_generic, (void *)-1, "IPI generic"); + intr_establish_xname(ARMGIC_SGI_IPIBASE + IPI_NOP, IPL_VM, + IST_MPSAFE | IST_EDGE, pic_ipi_nop, (void *)-1, "IPI nop"); + intr_establish_xname(ARMGIC_SGI_IPIBASE + IPI_SHOOTDOWN, IPL_SCHED, + IST_MPSAFE | IST_EDGE, pic_ipi_shootdown, (void *)-1, "IPI shootdown"); #ifdef DDB - intr_establish(ARMGIC_SGI_IPIBASE + IPI_DDB, IPL_HIGH, - IST_MPSAFE | IST_EDGE, pic_ipi_ddb, NULL); + intr_establish_xname(ARMGIC_SGI_IPIBASE + IPI_DDB, IPL_HIGH, + IST_MPSAFE | IST_EDGE, pic_ipi_ddb, NULL, "IPI ddb"); #endif #ifdef __HAVE_PREEMPTION - intr_establish(ARMGIC_SGI_IPIBASE + IPI_KPREEMPT, IPL_VM, - IST_MPSAFE | IST_EDGE, pic_ipi_kpreempt, (void *)-1); + intr_establish_xname(ARMGIC_SGI_IPIBASE + IPI_KPREEMPT, IPL_VM, + IST_MPSAFE | IST_EDGE, pic_ipi_kpreempt, (void *)-1, "IPI kpreempt"); #endif #endif
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Thu Nov 15 17:15:52 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
A64 timer errata can cause the timer to fire too soon, so skip KASSERT here too.
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.37 src/sys/arch/arm/cortex/gtmr.c:1.38
--- src/sys/arch/arm/cortex/gtmr.c:1.37 Tue Oct 30 10:38:11 2018
+++ src/sys/arch/arm/cortex/gtmr.c Thu Nov 15 17:15:52 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.37 2018/10/30 10:38:11 jmcneill Exp $ */
+/* $NetBSD: gtmr.c,v 1.38 2018/11/15 17:15:52 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.37 2018/10/30 10:38:11 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.38 2018/11/15 17:15:52 jmcneill Exp $");
#include
#include
@@ -282,9 +282,11 @@ gtmr_intr(void *arg)
}
#endif
- KASSERTMSG(delta > sc->sc_autoinc / 100,
- "%s: interrupting too quickly (delta=%"PRIu64") autoinc=%lu",
- ci->ci_data.cpu_name, delta, sc->sc_autoinc);
+ if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) {
+ KASSERTMSG(delta > sc->sc_autoinc / 100,
+ "%s: interrupting too quickly (delta=%"PRIu64") autoinc=%lu",
+ ci->ci_data.cpu_name, delta, sc->sc_autoinc);
+ }
/*
* If we got interrupted too soon (delta < sc->sc_autoinc)
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Thu Nov 15 00:01:38 UTC 2018 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Instead of disabling preemption, set the binary point field to the minimum supported value To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.9 src/sys/arch/arm/cortex/gicv3.c:1.10 --- src/sys/arch/arm/cortex/gicv3.c:1.9 Tue Nov 13 22:25:28 2018 +++ src/sys/arch/arm/cortex/gicv3.c Thu Nov 15 00:01:38 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.9 2018/11/13 22:25:28 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.10 2018/11/15 00:01:38 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -31,7 +31,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.9 2018/11/13 22:25:28 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.10 2018/11/15 00:01:38 jmcneill Exp $"); #include #include @@ -397,9 +397,8 @@ gicv3_cpu_init(struct pic_softc *pic, st /* Set initial priority mask */ gicv3_set_priority(pic, IPL_HIGH); - /* Disable preemption */ - const uint32_t icc_bpr = __SHIFTIN(0x7, ICC_BPR_EL1_BinaryPoint); - icc_bpr1_write(icc_bpr); + /* Set the binary point field to the minimum value */ + icc_bpr1_write(0); /* Enable group 1 interrupt signaling */ icc_igrpen1_write(ICC_IGRPEN_EL1_Enable);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Tue Nov 13 22:25:29 UTC 2018 Modified Files: src/sys/arch/arm/cortex: gic_reg.h gicv3.c Log Message: Update GICD_CTLR reg bit definitions to reflect the layout of the register when either in non-secure state or for a system that only supports a single state. To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/cortex/gic_reg.h \ src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic_reg.h diff -u src/sys/arch/arm/cortex/gic_reg.h:1.8 src/sys/arch/arm/cortex/gic_reg.h:1.9 --- src/sys/arch/arm/cortex/gic_reg.h:1.8 Fri Nov 9 23:36:24 2018 +++ src/sys/arch/arm/cortex/gic_reg.h Tue Nov 13 22:25:28 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gic_reg.h,v 1.8 2018/11/09 23:36:24 jmcneill Exp $ */ +/* $NetBSD: gic_reg.h,v 1.9 2018/11/13 22:25:28 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -143,10 +143,8 @@ #define GICD_CTRL_RWP __BIT(31) // GICv3 #define GICD_CTRL_E1NWF __BIT(7) // GICv3 #define GICD_CTRL_DS __BIT(6) // GICv3 -#define GICD_CTRL_ARE_NS __BIT(5) // GICv3 -#define GICD_CTRL_ARE_S __BIT(4) // GICv3 -#define GICD_CTRL_EnableGrp1S __BIT(2) // GICv3 -#define GICD_CTRL_EnableGrp1NS __BIT(1) // GICv3 +#define GICD_CTRL_ARE_NS __BIT(4) // GICv3 +#define GICD_CTRL_EnableGrp1A __BIT(1) // GICv3 #define GICD_CTRL_Enable __BIT(0) #define GICD_TYPER_No1N __BIT(25) // GICv3 Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.8 src/sys/arch/arm/cortex/gicv3.c:1.9 --- src/sys/arch/arm/cortex/gicv3.c:1.8 Tue Nov 13 10:33:03 2018 +++ src/sys/arch/arm/cortex/gicv3.c Tue Nov 13 22:25:28 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.8 2018/11/13 10:33:03 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.9 2018/11/13 22:25:28 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -31,7 +31,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.8 2018/11/13 10:33:03 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.9 2018/11/13 22:25:28 jmcneill Exp $"); #include #include @@ -245,7 +245,7 @@ gicv3_dist_enable(struct gicv3_softc *sc ; /* Enable Affinity routing and G1NS interrupts */ - gicd_ctrl = GICD_CTRL_EnableGrp1NS | GICD_CTRL_Enable | GICD_CTRL_ARE_NS; + gicd_ctrl = GICD_CTRL_EnableGrp1A | GICD_CTRL_Enable | GICD_CTRL_ARE_NS; gicd_write_4(sc, GICD_CTRL, gicd_ctrl); }
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Tue Nov 13 10:33:03 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Save a few pages by only allocating LPI pending tables for "ncpu" instead of
"MAXCPU" CPUs.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.7 src/sys/arch/arm/cortex/gicv3.c:1.8
--- src/sys/arch/arm/cortex/gicv3.c:1.7 Sat Nov 10 11:46:31 2018
+++ src/sys/arch/arm/cortex/gicv3.c Tue Nov 13 10:33:03 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.7 2018/11/10 11:46:31 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.8 2018/11/13 10:33:03 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.7 2018/11/10 11:46:31 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.8 2018/11/13 10:33:03 jmcneill Exp $");
#include
#include
@@ -673,7 +673,7 @@ gicv3_lpi_init(struct gicv3_softc *sc)
* Allocate LPI pending tables
*/
const bus_size_t lpipend_sz = (sc->sc_lpi.pic_maxsources + sc->sc_lpi.pic_irqbase) / NBBY;
- for (int cpuindex = 0; cpuindex < MAXCPUS; cpuindex++) {
+ for (int cpuindex = 0; cpuindex < ncpu; cpuindex++) {
gicv3_dma_alloc(sc, >sc_lpipend[cpuindex], lpipend_sz, 0x1);
KASSERT((sc->sc_lpipend[cpuindex].segs[0].ds_addr & ~GICR_PENDBASER_Physical_Address) == 0);
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Nov 10 11:46:31 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h gicv3_its.c gicv3_its.h
Log Message:
Implement pic_get_affinity/pic_set_affinity for LPIs via ITS
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/gicv3.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/gicv3_its.c \
src/sys/arch/arm/cortex/gicv3_its.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.6 src/sys/arch/arm/cortex/gicv3.c:1.7
--- src/sys/arch/arm/cortex/gicv3.c:1.6 Sat Nov 10 01:56:28 2018
+++ src/sys/arch/arm/cortex/gicv3.c Sat Nov 10 11:46:31 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.6 2018/11/10 01:56:28 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.7 2018/11/10 11:46:31 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.6 2018/11/10 01:56:28 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.7 2018/11/10 11:46:31 jmcneill Exp $");
#include
#include
@@ -556,7 +556,7 @@ static void
gicv3_lpi_cpu_init(struct pic_softc *pic, struct cpu_info *ci)
{
struct gicv3_softc * const sc = LPITOSOFTC(pic);
- struct gicv3_cpu_init *cpu_init;
+ struct gicv3_lpi_callback *cb;
uint32_t ctlr;
/* If physical LPIs are not supported on this redistributor, just return. */
@@ -594,16 +594,46 @@ gicv3_lpi_cpu_init(struct pic_softc *pic
arm_dsb();
/* Setup ITS if present */
- LIST_FOREACH(cpu_init, >sc_cpu_init, list)
- cpu_init->func(cpu_init->arg, ci);
+ LIST_FOREACH(cb, >sc_lpi_callbacks, list)
+ cb->cpu_init(cb->priv, ci);
}
+#ifdef MULTIPROCESSOR
+static void
+gicv3_lpi_get_affinity(struct pic_softc *pic, size_t irq, kcpuset_t *affinity)
+{
+ struct gicv3_softc * const sc = LPITOSOFTC(pic);
+ struct gicv3_lpi_callback *cb;
+
+ LIST_FOREACH(cb, >sc_lpi_callbacks, list)
+ cb->get_affinity(cb->priv, irq, affinity);
+}
+
+static int
+gicv3_lpi_set_affinity(struct pic_softc *pic, size_t irq, const kcpuset_t *affinity)
+{
+ struct gicv3_softc * const sc = LPITOSOFTC(pic);
+ struct gicv3_lpi_callback *cb;
+ int error = EINVAL;
+
+ LIST_FOREACH(cb, >sc_lpi_callbacks, list) {
+ error = cb->set_affinity(cb->priv, irq, affinity);
+ if (error)
+ return error;
+ }
+
+ return error;
+}
+#endif
+
static const struct pic_ops gicv3_lpiops = {
.pic_unblock_irqs = gicv3_lpi_unblock_irqs,
.pic_block_irqs = gicv3_lpi_block_irqs,
.pic_establish_irq = gicv3_lpi_establish_irq,
#ifdef MULTIPROCESSOR
.pic_cpu_init = gicv3_lpi_cpu_init,
+ .pic_get_affinity = gicv3_lpi_get_affinity,
+ .pic_set_affinity = gicv3_lpi_set_affinity,
#endif
};
@@ -695,7 +725,7 @@ gicv3_init(struct gicv3_softc *sc)
KASSERT(CPU_IS_PRIMARY(curcpu()));
- LIST_INIT(>sc_cpu_init);
+ LIST_INIT(>sc_lpi_callbacks);
for (n = 0; n < MAXCPUS; n++)
sc->sc_irouter[n] = UINT64_MAX;
Index: src/sys/arch/arm/cortex/gicv3.h
diff -u src/sys/arch/arm/cortex/gicv3.h:1.3 src/sys/arch/arm/cortex/gicv3.h:1.4
--- src/sys/arch/arm/cortex/gicv3.h:1.3 Sat Nov 10 01:56:28 2018
+++ src/sys/arch/arm/cortex/gicv3.h Sat Nov 10 11:46:31 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.h,v 1.3 2018/11/10 01:56:28 jmcneill Exp $ */
+/* $NetBSD: gicv3.h,v 1.4 2018/11/10 11:46:31 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -38,11 +38,14 @@ struct gicv3_dma {
bus_size_t len;
};
-struct gicv3_cpu_init {
- void (*func)(void *, struct cpu_info *ci);
- void *arg;
+struct gicv3_lpi_callback {
+ void (*cpu_init)(void *, struct cpu_info *);
+ void (*get_affinity)(void *, size_t, kcpuset_t *);
+ int (*set_affinity)(void *, size_t, const kcpuset_t *);
- LIST_ENTRY(gicv3_cpu_init) list;
+ void *priv;
+
+ LIST_ENTRY(gicv3_lpi_callback) list;
};
struct gicv3_softc {
@@ -69,8 +72,8 @@ struct gicv3_softc {
/* Unique identifier for PEs */
u_int sc_processor_id[MAXCPUS];
- /* CPU init callbacks */
- LIST_HEAD(, gicv3_cpu_init) sc_cpu_init;
+ /* Callbacks */
+ LIST_HEAD(, gicv3_lpi_callback) sc_lpi_callbacks;
};
int gicv3_init(struct gicv3_softc *);
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.1 src/sys/arch/arm/cortex/gicv3_its.c:1.2
--- src/sys/arch/arm/cortex/gicv3_its.c:1.1 Fri Nov 9 23:36:24 2018
+++ src/sys/arch/arm/cortex/gicv3_its.c Sat Nov 10 11:46:31 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.1 2018/11/09 23:36:24 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.2 2018/11/10 11:46:31 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.1 2018/11/09 23:36:24 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD:
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Nov 10 01:56:28 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h
Log Message:
Implement pic_get_affinity/pic_set_affinity for SPIs
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/gicv3.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.5 src/sys/arch/arm/cortex/gicv3.c:1.6
--- src/sys/arch/arm/cortex/gicv3.c:1.5 Fri Nov 9 23:36:24 2018
+++ src/sys/arch/arm/cortex/gicv3.c Sat Nov 10 01:56:28 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.5 2018/11/09 23:36:24 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.6 2018/11/10 01:56:28 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.5 2018/11/09 23:36:24 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.6 2018/11/10 01:56:28 jmcneill Exp $");
#include
#include
@@ -68,6 +68,12 @@ gicd_write_4(struct gicv3_softc *sc, bus
bus_space_write_4(sc->sc_bst, sc->sc_bsh_d, reg, val);
}
+static inline uint64_t
+gicd_read_8(struct gicv3_softc *sc, bus_size_t reg)
+{
+ return bus_space_read_8(sc->sc_bst, sc->sc_bsh_d, reg);
+}
+
static inline void
gicd_write_8(struct gicv3_softc *sc, bus_size_t reg, uint64_t val)
{
@@ -177,7 +183,7 @@ gicv3_establish_irq(struct pic_softc *pi
irouter = GICD_IROUTER_Interrupt_Routing_mode;
} else {
/* Route non-MP-safe interrupts to the primary PE only */
- irouter = sc->sc_default_irouter;
+ irouter = sc->sc_irouter[0];
}
gicd_write_8(sc, GICD_IROUTER(is->is_irq), irouter);
@@ -365,19 +371,17 @@ gicv3_cpu_init(struct pic_softc *pic, st
ci->ci_gic_redist = gicv3_find_redist(sc);
ci->ci_gic_sgir = gicv3_sgir(sc);
- if (CPU_IS_PRIMARY(ci)) {
- /* Store route to primary CPU for non-MPSAFE SPIs */
- const uint64_t cpu_identity = gicv3_cpu_identity();
- const u_int aff0 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff0);
- const u_int aff1 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff1);
- const u_int aff2 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff2);
- const u_int aff3 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff3);
- sc->sc_default_irouter =
- __SHIFTIN(aff0, GICD_IROUTER_Aff0) |
- __SHIFTIN(aff1, GICD_IROUTER_Aff1) |
- __SHIFTIN(aff2, GICD_IROUTER_Aff2) |
- __SHIFTIN(aff3, GICD_IROUTER_Aff3);
- }
+ /* Store route to CPU for SPIs */
+ const uint64_t cpu_identity = gicv3_cpu_identity();
+ const u_int aff0 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff0);
+ const u_int aff1 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff1);
+ const u_int aff2 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff2);
+ const u_int aff3 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff3);
+ sc->sc_irouter[cpu_index(ci)] =
+ __SHIFTIN(aff0, GICD_IROUTER_Aff0) |
+ __SHIFTIN(aff1, GICD_IROUTER_Aff1) |
+ __SHIFTIN(aff2, GICD_IROUTER_Aff2) |
+ __SHIFTIN(aff3, GICD_IROUTER_Aff3);
/* Enable System register access and disable IRQ/FIQ bypass */
icc_sre = ICC_SRE_EL1_SRE | ICC_SRE_EL1_DFB | ICC_SRE_EL1_DIB;
@@ -446,6 +450,54 @@ gicv3_ipi_send(struct pic_softc *pic, co
icc_sgi1r_write(intid | aff | targets);
}
}
+
+static void
+gicv3_get_affinity(struct pic_softc *pic, size_t irq, kcpuset_t *affinity)
+{
+ struct gicv3_softc * const sc = PICTOSOFTC(pic);
+ const size_t group = irq / 32;
+ int n;
+
+ kcpuset_zero(affinity);
+ if (group == 0) {
+ /* All CPUs are targets for group 0 (SGI/PPI) */
+ for (n = 0; n < ncpu; n++) {
+ if (sc->sc_irouter[n] != UINT64_MAX)
+kcpuset_set(affinity, n);
+ }
+ } else {
+ /* Find distributor targets (SPI) */
+ const uint64_t irouter = gicd_read_8(sc, GICD_IROUTER(irq));
+ for (n = 0; n < ncpu; n++) {
+ if (irouter == GICD_IROUTER_Interrupt_Routing_mode ||
+ irouter == sc->sc_irouter[n])
+kcpuset_set(affinity, n);
+ }
+ }
+}
+
+static int
+gicv3_set_affinity(struct pic_softc *pic, size_t irq, const kcpuset_t *affinity)
+{
+ struct gicv3_softc * const sc = PICTOSOFTC(pic);
+ const size_t group = irq / 32;
+ uint64_t irouter;
+
+ if (group == 0)
+ return EINVAL;
+
+ const int set = kcpuset_countset(affinity);
+ if (set == ncpu)
+ irouter = GICD_IROUTER_Interrupt_Routing_mode;
+ else if (set == 1)
+ irouter = sc->sc_irouter[kcpuset_ffs(affinity)];
+ else
+ return EINVAL;
+
+ gicd_write_8(sc, GICD_IROUTER(irq), irouter);
+
+ return 0;
+}
#endif
static const struct pic_ops gicv3_picops = {
@@ -456,6 +508,8 @@ static const struct pic_ops gicv3_picops
#ifdef MULTIPROCESSOR
.pic_cpu_init = gicv3_cpu_init,
.pic_ipi_send = gicv3_ipi_send,
+ .pic_get_affinity = gicv3_get_affinity,
+ .pic_set_affinity
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Fri Nov 9 23:36:24 UTC 2018 Modified Files: src/sys/arch/arm/cortex: files.cortex gic_reg.h gicv3.c gicv3.h Added Files: src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h Log Message: Add support for GICv3 Locality-specific Periphal Interrupts (LPIs) and the Interrupt Translation Service (ITS). To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/files.cortex cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/gic_reg.h cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/cortex/gicv3.c cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/gicv3.h cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/cortex/gicv3_its.c \ src/sys/arch/arm/cortex/gicv3_its.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/files.cortex diff -u src/sys/arch/arm/cortex/files.cortex:1.9 src/sys/arch/arm/cortex/files.cortex:1.10 --- src/sys/arch/arm/cortex/files.cortex:1.9 Sun Oct 21 00:42:05 2018 +++ src/sys/arch/arm/cortex/files.cortex Fri Nov 9 23:36:24 2018 @@ -1,4 +1,4 @@ -# $NetBSD: files.cortex,v 1.9 2018/10/21 00:42:05 jmcneill Exp $ +# $NetBSD: files.cortex,v 1.10 2018/11/09 23:36:24 jmcneill Exp $ defflag opt_cpu_in_cksum.h NEON_IN_CKSUM @@ -20,6 +20,7 @@ file arch/arm/cortex/gic_v2m.c armgic & # ARM Generic Interrupt Controller v3+ device gicvthree: pic, pic_splfuncs file arch/arm/cortex/gicv3.c gicvthree +file arch/arm/cortex/gicv3_its.c gicvthree # ARM PL310 L2 Cache Controller(initially on Cortex-A9) device arml2cc Index: src/sys/arch/arm/cortex/gic_reg.h diff -u src/sys/arch/arm/cortex/gic_reg.h:1.7 src/sys/arch/arm/cortex/gic_reg.h:1.8 --- src/sys/arch/arm/cortex/gic_reg.h:1.7 Wed Aug 8 19:01:54 2018 +++ src/sys/arch/arm/cortex/gic_reg.h Fri Nov 9 23:36:24 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gic_reg.h,v 1.7 2018/08/08 19:01:54 jmcneill Exp $ */ +/* $NetBSD: gic_reg.h,v 1.8 2018/11/09 23:36:24 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -149,6 +149,12 @@ #define GICD_CTRL_EnableGrp1NS __BIT(1) // GICv3 #define GICD_CTRL_Enable __BIT(0) +#define GICD_TYPER_No1N __BIT(25) // GICv3 +#define GICD_TYPER_A3V __BIT(24) // GICv3 +#define GICD_TYPER_IDbits __BITS(23,19) // GICv3 +#define GICD_TYPER_DVIS __BIT(18) // GICv3 +#define GICD_TYPER_LPIS __BIT(17) // GICv3 +#define GICD_TYPER_MBIS __BIT(16) // GICv3 #define GICD_TYPER_LSPI __BITS(15,11) #define GICD_TYPER_SecurityExtn __BIT(10) #define GICD_TYPER_CPUNumber __BITS(7,5) @@ -190,7 +196,7 @@ #define GICD_IROUTER_Aff1 __BITS(15,8) #define GICD_IROUTER_Aff0 __BITS(7,0) -#define GICR_CTRL 0x // Redistributor Control Register +#define GICR_CTLR 0x // Redistributor Control Register #define GICR_IIDR 0x0004 // Implementor Identification Register #define GICR_TYPER 0x0008 // Redistributor Type Register #define GICR_STATUSR 0x0010 // Error Reporting Status Register, optional @@ -215,12 +221,12 @@ #define GICR_IGRPMODR0 0x10D00 // Interrupt Group Modifier Register 0 #define GICR_NSACR 0x10E00 // Non-Secure Access Control Register -#define GICR_CTRL_UWP __BIT(31) -#define GICR_CTRL_DPG1S __BIT(26) -#define GICR_CTRL_DPG1NS __BIT(25) -#define GICR_CTRL_DPG0 __BIT(24) -#define GICR_CTRL_RWP __BIT(3) -#define GICR_CTRL_Enable_LPIs __BIT(0) +#define GICR_CTLR_UWP __BIT(31) +#define GICR_CTLR_DPG1S __BIT(26) +#define GICR_CTLR_DPG1NS __BIT(25) +#define GICR_CTLR_DPG0 __BIT(24) +#define GICR_CTLR_RWP __BIT(3) +#define GICR_CTLR_Enable_LPIs __BIT(0) #define GICR_TYPER_Affinity_Value __BITS(63,32) #define GICR_TYPER_Affinity_Value_Aff3 __BITS(63,56) @@ -238,6 +244,40 @@ #define GICR_WAKER_ChildrenAsleep __BIT(2) #define GICR_WAKER_ProcessorSleep __BIT(1) +#define GICR_PROPBASER_OuterCache __BITS(58,56) +#define GICR_PROPBASER_Physical_Address __BITS(51,12) +#define GICR_PROPBASER_Shareability __BITS(11,10) +#define GICR_PROPBASER_InnerCache __BITS(9,7) +#define GICR_PROPBASER_IDbits __BITS(4,0) + +#define GICR_PENDBASER_PTZ __BIT(62) +#define GICR_PENDBASER_OuterCache __BITS(58,56) +#define GICR_PENDBASER_Physical_Address __BITS(51,16) +#define GICR_PENDBASER_Shareability __BITS(11,10) +#define GICR_PENDBASER_InnerCache __BITS(9,7) + +#define GICR_Shareability_NS 0 // Non-shareable +#define GICR_Shareability_IS 1 // Inner Shareable +#define GICR_Shareability_OS 2 // Outer Shareable + +#define GICR_Cache_DEVICE_nGnRnE 0 // Device-nGnRnE +#define GICR_Cache_NORMAL_NC 1 // Non-cacheable +#define GICR_Cache_NORMAL_RA_WT 2 // Cacheable Read-allocate, Write-through +#define GICR_Cache_NORMAL_RA_WB 3 // Cacheable Read-allocate, Write-back +#define GICR_Cache_NORMAL_WA_WT 4 // Cacheable Write-allocate, Write-through +#define GICR_Cache_NORMAL_WA_WB 5 // Cacheable Write-allocate, Write-back +#define GICR_Cache_NORMAL_RA_WA_WT 6 //
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Mon Nov 5 11:50:15 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
ICC_PMR_EL1 has different encoding than IPRIORITYR. Not 100% sure that this is
correct yet, but it works with both RK3399 and QEMU.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.3 src/sys/arch/arm/cortex/gicv3.c:1.4
--- src/sys/arch/arm/cortex/gicv3.c:1.3 Sun Sep 30 13:53:26 2018
+++ src/sys/arch/arm/cortex/gicv3.c Mon Nov 5 11:50:15 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.3 2018/09/30 13:53:26 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.4 2018/11/05 11:50:15 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.3 2018/09/30 13:53:26 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.4 2018/11/05 11:50:15 jmcneill Exp $");
#include
#include
@@ -50,7 +50,7 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#define PICTOSOFTC(pic) \
((void *)((uintptr_t)(pic) - offsetof(struct gicv3_softc, sc_pic)))
-#define IPL_TO_PRIORITY(ipl) (0x80 | ((IPL_HIGH - (ipl)) << 4))
+#define IPL_TO_PRIORITY(ipl) ((IPL_HIGH - (ipl)) << 4)
static struct gicv3_softc *gicv3_softc;
@@ -147,7 +147,7 @@ gicv3_establish_irq(struct pic_softc *pi
uint64_t irouter;
u_int n;
- const u_int ipriority_val = IPL_TO_PRIORITY(is->is_ipl);
+ const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
const u_int ipriority_shift = (is->is_irq & 0x3) * 8;
const u_int icfg_shift = (is->is_irq & 0xf) * 2;
@@ -198,7 +198,7 @@ gicv3_establish_irq(struct pic_softc *pi
static void
gicv3_set_priority(struct pic_softc *pic, int ipl)
{
- icc_pmr_write(IPL_TO_PRIORITY(ipl));
+ icc_pmr_write(IPL_TO_PRIORITY(ipl) << 1);
}
static void
@@ -389,7 +389,7 @@ gicv3_cpu_init(struct pic_softc *pic, st
;
/* Set initial priority mask */
- icc_pmr_write(IPL_TO_PRIORITY(IPL_HIGH));
+ gicv3_set_priority(pic, IPL_HIGH);
/* Disable preemption */
const uint32_t icc_bpr = __SHIFTIN(0x7, ICC_BPR_EL1_BinaryPoint);
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Wed Oct 31 15:43:19 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c
Log Message:
Add MSI-X support.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/gic_v2m.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_v2m.c
diff -u src/sys/arch/arm/cortex/gic_v2m.c:1.2 src/sys/arch/arm/cortex/gic_v2m.c:1.3
--- src/sys/arch/arm/cortex/gic_v2m.c:1.2 Tue Oct 30 23:59:47 2018
+++ src/sys/arch/arm/cortex/gic_v2m.c Wed Oct 31 15:43:19 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.c,v 1.2 2018/10/30 23:59:47 jmcneill Exp $ */
+/* $NetBSD: gic_v2m.c,v 1.3 2018/10/31 15:43:19 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.2 2018/10/30 23:59:47 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.3 2018/10/31 15:43:19 jmcneill Exp $");
#include
#include
@@ -135,6 +135,48 @@ gic_v2m_msi_disable(struct gic_v2m_frame
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
}
+static void
+gic_v2m_msix_enable(struct gic_v2m_frame *frame, int spi, int msix_vec,
+bus_space_tag_t bst, bus_space_handle_t bsh)
+{
+ const struct pci_attach_args *pa = frame->frame_pa[spi];
+ pci_chipset_tag_t pc = pa->pa_pc;
+ pcitag_t tag = pa->pa_tag;
+ pcireg_t ctl;
+ int off;
+
+ if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, , NULL))
+ panic("gic_v2m_msix_enable: device is not MSI-X-capable");
+
+ const uint64_t addr = frame->frame_reg + GIC_MSI_SETSPI;
+ const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
+ bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);
+ bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32));
+ bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, spi);
+ bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0);
+
+ ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
+ ctl |= PCI_MSIX_CTL_ENABLE;
+ pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
+}
+
+static void
+gic_v2m_msix_disable(struct gic_v2m_frame *frame, int spi)
+{
+ const struct pci_attach_args *pa = frame->frame_pa[spi];
+ pci_chipset_tag_t pc = pa->pa_pc;
+ pcitag_t tag = pa->pa_tag;
+ pcireg_t ctl;
+ int off;
+
+ if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, , NULL))
+ panic("gic_v2m_msix_disable: device is not MSI-X-capable");
+
+ ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
+ ctl &= ~PCI_MSIX_CTL_ENABLE;
+ pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
+}
+
static pci_intr_handle_t *
gic_v2m_msi_alloc(struct arm_pci_msi *msi, int *count,
const struct pci_attach_args *pa, bool exact)
@@ -175,6 +217,69 @@ gic_v2m_msi_alloc(struct arm_pci_msi *ms
return vectors;
}
+static pci_intr_handle_t *
+gic_v2m_msix_alloc(struct arm_pci_msi *msi, u_int *table_indexes, int *count,
+const struct pci_attach_args *pa, bool exact)
+{
+ struct gic_v2m_frame * const frame = msi->msi_priv;
+ pci_intr_handle_t *vectors;
+ bus_space_tag_t bst;
+ bus_space_handle_t bsh;
+ bus_size_t bsz;
+ uint32_t table_offset, table_size;
+ int n, off, bar, error;
+ pcireg_t tbl;
+
+ if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, , NULL))
+ return NULL;
+
+ const int avail = gic_v2m_msi_available_spi(frame);
+ if (exact && *count > avail)
+ return NULL;
+
+ while (*count > avail) {
+ if (avail < *count)
+ (*count) >>= 1;
+ }
+ if (*count == 0)
+ return NULL;
+
+ tbl = pci_conf_read(pa->pa_pc, pa->pa_tag, off + PCI_MSIX_TBLOFFSET);
+ bar = PCI_BAR0 + (4 * (tbl & PCI_MSIX_PBABIR_MASK));
+ table_offset = tbl & PCI_MSIX_TBLOFFSET_MASK;
+ table_size = pci_msix_count(pa->pa_pc, pa->pa_tag) * PCI_MSIX_TABLE_ENTRY_SIZE;
+ if (table_size == 0)
+ return NULL;
+
+ error = pci_mapreg_submap(pa, bar, pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar),
+ BUS_SPACE_MAP_LINEAR, roundup(table_size, PAGE_SIZE), table_offset,
+ , , NULL, );
+ if (error)
+ return NULL;
+
+ const int spi_base = gic_v2m_msi_alloc_spi(frame, *count, pa);
+ if (spi_base == -1) {
+ bus_space_unmap(bst, bsh, bsz);
+ return NULL;
+ }
+
+ vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP);
+ for (n = 0; n < *count; n++) {
+ const int spi = spi_base + n;
+ const int msix_vec = table_indexes ? table_indexes[n] : n;
+ vectors[msix_vec] = ARM_PCI_INTR_MSIX |
+ __SHIFTIN(spi, ARM_PCI_INTR_IRQ) |
+ __SHIFTIN(msix_vec, ARM_PCI_INTR_MSI_VEC) |
+ __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);
+
+ gic_v2m_msix_enable(frame, spi, msix_vec, bst, bsh);
+ }
+
+ bus_space_unmap(bst, bsh, bsz);
+
+ return vectors;
+}
+
static void *
gic_v2m_msi_intr_establish(struct arm_pci_msi *msi,
pci_intr_handle_t ih, int ipl, int (*func)(void *), void *arg)
@@ -197,7 +302,10 @@
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Tue Oct 30 23:59:47 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c
Log Message:
Fail gracefully when an attempt to allocate MSI vectors is made on a device
without MSI capabilities.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/gic_v2m.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_v2m.c
diff -u src/sys/arch/arm/cortex/gic_v2m.c:1.1 src/sys/arch/arm/cortex/gic_v2m.c:1.2
--- src/sys/arch/arm/cortex/gic_v2m.c:1.1 Sun Oct 21 00:42:05 2018
+++ src/sys/arch/arm/cortex/gic_v2m.c Tue Oct 30 23:59:47 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.c,v 1.1 2018/10/21 00:42:05 jmcneill Exp $ */
+/* $NetBSD: gic_v2m.c,v 1.2 2018/10/30 23:59:47 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.1 2018/10/21 00:42:05 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.2 2018/10/30 23:59:47 jmcneill Exp $");
#include
#include
@@ -141,7 +141,10 @@ gic_v2m_msi_alloc(struct arm_pci_msi *ms
{
struct gic_v2m_frame * const frame = msi->msi_priv;
pci_intr_handle_t *vectors;
- int n;
+ int n, off;
+
+ if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, , NULL))
+ return NULL;
const int avail = gic_v2m_msi_available_spi(frame);
if (exact && *count > avail)
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Tue Oct 30 10:38:11 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Disable diagnostic assertions around timer jitter on Allwinner A64. It
seems the instability of CNTVCT can cause issues with the compare value,
and rather than applying a heavy workaround just skip the panics.
To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.36 src/sys/arch/arm/cortex/gtmr.c:1.37
--- src/sys/arch/arm/cortex/gtmr.c:1.36 Sun Sep 30 10:34:38 2018
+++ src/sys/arch/arm/cortex/gtmr.c Tue Oct 30 10:38:11 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.36 2018/09/30 10:34:38 skrll Exp $ */
+/* $NetBSD: gtmr.c,v 1.37 2018/10/30 10:38:11 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.36 2018/09/30 10:34:38 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.37 2018/10/30 10:38:11 jmcneill Exp $");
#include
#include
@@ -272,11 +272,14 @@ gtmr_intr(void *arg)
uint64_t delta = now - ci->ci_lastintr;
#ifdef DIAGNOSTIC
- const uint64_t then = gtmr_cntv_cval_read();
- struct gtmr_percpu * const pc = percpu_getref(sc->sc_percpu);
- KASSERTMSG(then <= now, "%"PRId64, now - then);
- KASSERTMSG(then + pc->pc_delta >= ci->ci_lastintr + sc->sc_autoinc,
- "%"PRId64, then + pc->pc_delta - ci->ci_lastintr - sc->sc_autoinc);
+ struct gtmr_percpu *pc = NULL;
+ if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) {
+ const uint64_t then = gtmr_cntv_cval_read();
+ pc = percpu_getref(sc->sc_percpu);
+ KASSERTMSG(then <= now, "%"PRId64, now - then);
+ KASSERTMSG(then + pc->pc_delta >= ci->ci_lastintr + sc->sc_autoinc,
+ "%"PRId64, then + pc->pc_delta - ci->ci_lastintr - sc->sc_autoinc);
+ }
#endif
KASSERTMSG(delta > sc->sc_autoinc / 100,
@@ -298,9 +301,11 @@ gtmr_intr(void *arg)
ci->ci_lastintr = now;
#ifdef DIAGNOSTIC
- KASSERT(delta == (uint32_t) delta);
- pc->pc_delta = delta;
- percpu_putref(sc->sc_percpu);
+ if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) {
+ KASSERT(delta == (uint32_t) delta);
+ pc->pc_delta = delta;
+ percpu_putref(sc->sc_percpu);
+ }
#endif
hardclock(cf);
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: aymeric
Date: Sun Oct 28 21:08:13 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: a9tmr.c
Log Message:
Enable the global timer at attach time, it ensures that delay() works.
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/cortex/a9tmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9tmr.c
diff -u src/sys/arch/arm/cortex/a9tmr.c:1.17 src/sys/arch/arm/cortex/a9tmr.c:1.18
--- src/sys/arch/arm/cortex/a9tmr.c:1.17 Sun Oct 14 19:01:00 2018
+++ src/sys/arch/arm/cortex/a9tmr.c Sun Oct 28 21:08:13 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: a9tmr.c,v 1.17 2018/10/14 19:01:00 aymeric Exp $ */
+/* $NetBSD: a9tmr.c,v 1.18 2018/10/28 21:08:13 aymeric Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.17 2018/10/14 19:01:00 aymeric Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.18 2018/10/28 21:08:13 aymeric Exp $");
#include
#include
@@ -150,6 +150,9 @@ a9tmr_attach(device_t parent, device_t s
bus_space_subregion(sc->sc_memt, sc->sc_memh,
mpcaa->mpcaa_off1, TMR_GLOBAL_SIZE, >sc_global_memh);
+ /* Enable the timer early for delay(), disable all other features */
+ a9tmr_global_write(sc, TMR_GBL_CTL, TMR_CTL_ENABLE);
+
if (mpcaa->mpcaa_irq != -1) {
sc->sc_global_ih = intr_establish(mpcaa->mpcaa_irq, IPL_CLOCK,
IST_EDGE | IST_MPSAFE, a9tmr_intr, NULL);
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: aymeric
Date: Sun Oct 14 19:01:00 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: a9tmr.c
Log Message:
Remove comment that the peripherals clock should be half of the cpu clock.
NFC
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/cortex/a9tmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9tmr.c
diff -u src/sys/arch/arm/cortex/a9tmr.c:1.16 src/sys/arch/arm/cortex/a9tmr.c:1.17
--- src/sys/arch/arm/cortex/a9tmr.c:1.16 Wed Jun 20 05:01:39 2018
+++ src/sys/arch/arm/cortex/a9tmr.c Sun Oct 14 19:01:00 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: a9tmr.c,v 1.16 2018/06/20 05:01:39 hkenken Exp $ */
+/* $NetBSD: a9tmr.c,v 1.17 2018/10/14 19:01:00 aymeric Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.16 2018/06/20 05:01:39 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.17 2018/10/14 19:01:00 aymeric Exp $");
#include
#include
@@ -121,7 +121,7 @@ a9tmr_attach(device_t parent, device_t s
const char *cpu_type;
/*
- * This runs at the ARM PERIPHCLOCK which should be 1/2 of the CPU clock.
+ * This runs at the ARM PERIPHCLOCK.
* The MD code should have setup our frequency for us.
*/
if (!prop_dictionary_get_uint32(dict, "frequency", >sc_freq)) {
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Sep 30 13:53:26 UTC 2018 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Set NS access bit when writing ICC_PMR_EL1 To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.2 src/sys/arch/arm/cortex/gicv3.c:1.3 --- src/sys/arch/arm/cortex/gicv3.c:1.2 Sat Aug 11 00:32:17 2018 +++ src/sys/arch/arm/cortex/gicv3.c Sun Sep 30 13:53:26 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.2 2018/08/11 00:32:17 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.3 2018/09/30 13:53:26 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -31,7 +31,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.2 2018/08/11 00:32:17 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.3 2018/09/30 13:53:26 jmcneill Exp $"); #include #include @@ -50,7 +50,7 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1. #define PICTOSOFTC(pic) \ ((void *)((uintptr_t)(pic) - offsetof(struct gicv3_softc, sc_pic))) -#define IPL_TO_PRIORITY(ipl) ((IPL_HIGH - (ipl)) << 4) +#define IPL_TO_PRIORITY(ipl) (0x80 | ((IPL_HIGH - (ipl)) << 4)) static struct gicv3_softc *gicv3_softc; @@ -147,7 +147,7 @@ gicv3_establish_irq(struct pic_softc *pi uint64_t irouter; u_int n; - const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl); + const u_int ipriority_val = IPL_TO_PRIORITY(is->is_ipl); const u_int ipriority_shift = (is->is_irq & 0x3) * 8; const u_int icfg_shift = (is->is_irq & 0xf) * 2;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sun Sep 30 10:34:38 UTC 2018 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: If we're going to allow pl0 to access virtual and physical counters then we should allow it from all CPUs. kern/53630 (openssl fallout on arm) To generate a diff of this commit: cvs rdiff -u -r1.35 -r1.36 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gtmr.c diff -u src/sys/arch/arm/cortex/gtmr.c:1.35 src/sys/arch/arm/cortex/gtmr.c:1.36 --- src/sys/arch/arm/cortex/gtmr.c:1.35 Sun Sep 16 13:21:36 2018 +++ src/sys/arch/arm/cortex/gtmr.c Sun Sep 30 10:34:38 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gtmr.c,v 1.35 2018/09/16 13:21:36 jmcneill Exp $ */ +/* $NetBSD: gtmr.c,v 1.36 2018/09/30 10:34:38 skrll Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.35 2018/09/16 13:21:36 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.36 2018/09/30 10:34:38 skrll Exp $"); #include #include @@ -120,12 +120,6 @@ gtmr_attach(device_t parent, device_t se aprint_debug_dev(self, "enabling Allwinner A64 timer workaround\n"); } - /* - * Enable the virtual counter to be accessed from usermode. - */ - gtmr_cntk_ctl_write(gtmr_cntk_ctl_read() | - CNTKCTL_PL0VCTEN | CNTKCTL_PL0PCTEN); - self->dv_private = sc; sc->sc_dev = self; @@ -195,6 +189,13 @@ gtmr_init_cpu_clock(struct cpu_info *ci) int s = splsched(); /* + * Allow the virtual and physical counters to be accessed from + * usermode. (PL0) + */ + gtmr_cntk_ctl_write(gtmr_cntk_ctl_read() | + CNTKCTL_PL0VCTEN | CNTKCTL_PL0PCTEN); + + /* * enable timer and stop masking the timer. */ gtmr_cntv_ctl_write(CNTCTL_ENABLE);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Tue Sep 25 20:55:34 UTC 2018 Modified Files: src/sys/arch/arm/cortex: armperiph.c Log Message: Cortex A5 also uses PPI 27 for timer. ODROID-C1 boots again. To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/armperiph.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/armperiph.c diff -u src/sys/arch/arm/cortex/armperiph.c:1.14 src/sys/arch/arm/cortex/armperiph.c:1.15 --- src/sys/arch/arm/cortex/armperiph.c:1.14 Wed Aug 15 06:00:02 2018 +++ src/sys/arch/arm/cortex/armperiph.c Tue Sep 25 20:55:34 2018 @@ -32,7 +32,7 @@ #include -__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.14 2018/08/15 06:00:02 skrll Exp $"); +__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.15 2018/09/25 20:55:34 skrll Exp $"); #include #include @@ -230,7 +230,7 @@ armperiph_attach(device_t parent, device .mpcaa_off1 = cfg->cfg_devices[i].pi_off1, .mpcaa_off2 = cfg->cfg_devices[i].pi_off2, }; -#if defined(CPU_CORTEXA9) +#if defined(CPU_CORTEXA9) || defined(CPU_CORTEXA5) if (strcmp(mpcaa.mpcaa_name, "arma9tmr") == 0) mpcaa.mpcaa_irq = IRQ_A9TMR_PPI_GTIMER; #endif
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Mon Sep 10 19:43:58 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
armgic_ipi_send: use GIC interface number, not CPU index, when setting
the target(s) for an IPI.
To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.36 src/sys/arch/arm/cortex/gic.c:1.37
--- src/sys/arch/arm/cortex/gic.c:1.36 Mon Sep 10 09:48:57 2018
+++ src/sys/arch/arm/cortex/gic.c Mon Sep 10 19:43:58 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.36 2018/09/10 09:48:57 jmcneill Exp $ */
+/* $NetBSD: gic.c,v 1.37 2018/09/10 19:43:58 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.36 2018/09/10 09:48:57 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.37 2018/09/10 19:43:58 jmcneill Exp $");
#include
#include
@@ -547,9 +547,12 @@ armgic_ipi_send(struct pic_softc *pic, c
uint32_t sgir = __SHIFTIN(ARMGIC_SGI_IPIBASE + ipi, GICD_SGIR_SGIINTID);
if (kcp != NULL) {
- uint32_t targets;
- kcpuset_export_u32(kcp, , sizeof(targets));
- sgir |= __SHIFTIN(targets, GICD_SGIR_TargetList);
+ uint32_t targets_val = 0;
+ for (int n = 0; n < MAXCPUS; n++) {
+ if (kcpuset_isset(kcp, n))
+targets_val |= sc->sc_target[n];
+ }
+ sgir |= __SHIFTIN(targets_val, GICD_SGIR_TargetList);
sgir |= GICD_SGIR_TargetListFilter_List;
} else {
if (ncpu == 1)
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Mon Sep 10 10:55:03 UTC 2018 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: Typo in comment from Joerg's gtmr diff To generate a diff of this commit: cvs rdiff -u -r1.33 -r1.34 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gtmr.c diff -u src/sys/arch/arm/cortex/gtmr.c:1.33 src/sys/arch/arm/cortex/gtmr.c:1.34 --- src/sys/arch/arm/cortex/gtmr.c:1.33 Sat Sep 1 20:54:32 2018 +++ src/sys/arch/arm/cortex/gtmr.c Mon Sep 10 10:55:02 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gtmr.c,v 1.33 2018/09/01 20:54:32 tnn Exp $ */ +/* $NetBSD: gtmr.c,v 1.34 2018/09/10 10:55:02 skrll Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.33 2018/09/01 20:54:32 tnn Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.34 2018/09/10 10:55:02 skrll Exp $"); #include #include @@ -125,7 +125,7 @@ gtmr_match(device_t parent, cfdata_t cf, if (gtmr_sc.sc_dev != NULL) return 0; - /* Genertic Timer is always implemented in ARMv8-A */ + /* Generic Timer is always implemented in ARMv8-A */ if (!cpu_gtmr_exists_p()) return 0;
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Mon Sep 10 09:48:57 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Update sc_mptargets atomically, as PEs will be started up in parallel w/o
locking here
To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.35 src/sys/arch/arm/cortex/gic.c:1.36
--- src/sys/arch/arm/cortex/gic.c:1.35 Sun Jul 15 16:04:07 2018
+++ src/sys/arch/arm/cortex/gic.c Mon Sep 10 09:48:57 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.35 2018/07/15 16:04:07 jmcneill Exp $ */
+/* $NetBSD: gic.c,v 1.36 2018/09/10 09:48:57 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.35 2018/07/15 16:04:07 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.36 2018/09/10 09:48:57 jmcneill Exp $");
#include
#include
@@ -43,6 +43,7 @@ __KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.35
#include
#include
#include
+#include
#include
#include
@@ -514,7 +515,7 @@ armgic_cpu_init(struct pic_softc *pic, s
{
struct armgic_softc * const sc = PICTOSOFTC(pic);
sc->sc_target[cpu_index(ci)] = gicd_find_targets(sc);
- sc->sc_mptargets |= sc->sc_target[cpu_index(ci)];
+ atomic_or_32(>sc_mptargets, sc->sc_target[cpu_index(ci)]);
KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl);
armgic_cpu_init_priorities(sc);
if (!CPU_IS_PRIMARY(ci)) {
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: tnn Date: Sat Sep 1 20:54:32 UTC 2018 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: fix non-DIAGNOSTIC build To generate a diff of this commit: cvs rdiff -u -r1.32 -r1.33 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gtmr.c diff -u src/sys/arch/arm/cortex/gtmr.c:1.32 src/sys/arch/arm/cortex/gtmr.c:1.33 --- src/sys/arch/arm/cortex/gtmr.c:1.32 Sat Jun 30 17:30:37 2018 +++ src/sys/arch/arm/cortex/gtmr.c Sat Sep 1 20:54:32 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gtmr.c,v 1.32 2018/06/30 17:30:37 jmcneill Exp $ */ +/* $NetBSD: gtmr.c,v 1.33 2018/09/01 20:54:32 tnn Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.32 2018/06/30 17:30:37 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.33 2018/09/01 20:54:32 tnn Exp $"); #include #include @@ -87,7 +87,9 @@ reg ## _stable_read(struct gtmr_softc *s return val; \ } +#ifdef DIAGNOSTIC stable_read(gtmr_cntv_cval); +#endif stable_read(gtmr_cntvct); static int gtmr_match(device_t, cfdata_t, void *); @@ -172,8 +174,10 @@ gtmr_attach(device_t parent, device_t se evcnt_attach_dynamic(_cntv_tval_write_ev, EVCNT_TYPE_MISC, NULL, device_xname(self), "CNTV_TVAL write retry max"); +#ifdef DIAGNOSTIC evcnt_attach_dynamic(_cntv_cval_read_ev, EVCNT_TYPE_MISC, NULL, device_xname(self), "CNTV_CVAL read retry max"); +#endif evcnt_attach_dynamic(_cntvct_read_ev, EVCNT_TYPE_MISC, NULL, device_xname(self), "CNTVCT read retry max");
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Aug 11 00:32:17 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
IPI and priority fixes. My RK3399 board boots multiuser now.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.1 src/sys/arch/arm/cortex/gicv3.c:1.2
--- src/sys/arch/arm/cortex/gicv3.c:1.1 Wed Aug 8 19:02:28 2018
+++ src/sys/arch/arm/cortex/gicv3.c Sat Aug 11 00:32:17 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.1 2018/08/08 19:02:28 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.2 2018/08/11 00:32:17 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.1 2018/08/08 19:02:28 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.2 2018/08/11 00:32:17 jmcneill Exp $");
#include
#include
@@ -147,6 +147,7 @@ gicv3_establish_irq(struct pic_softc *pi
uint64_t irouter;
u_int n;
+ const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
const u_int ipriority_shift = (is->is_irq & 0x3) * 8;
const u_int icfg_shift = (is->is_irq & 0xf) * 2;
@@ -165,7 +166,7 @@ gicv3_establish_irq(struct pic_softc *pi
ipriority = gicr_read_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4));
ipriority &= ~(0xff << ipriority_shift);
- ipriority |= (IPL_TO_PRIORITY(is->is_ipl) << ipriority_shift);
+ ipriority |= (ipriority_val << ipriority_shift);
gicr_write_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4), ipriority);
}
} else {
@@ -189,7 +190,7 @@ gicv3_establish_irq(struct pic_softc *pi
/* Update interrupt priority */
ipriority = gicd_read_4(sc, GICD_IPRIORITYRn(is->is_irq / 4));
ipriority &= ~(0xff << ipriority_shift);
- ipriority |= (IPL_TO_PRIORITY(is->is_ipl) << ipriority_shift);
+ ipriority |= (ipriority_val << ipriority_shift);
gicd_write_4(sc, GICD_IPRIORITYRn(is->is_irq / 4), ipriority);
}
}
@@ -261,8 +262,10 @@ gicv3_redist_enable(struct gicv3_softc *
struct intrsource * const is = sc->sc_pic.pic_sources[n + o];
if (is == NULL)
priority |= 0xff << byte_shift;
- else
-priority |= IPL_TO_PRIORITY(is->is_ipl) << byte_shift;
+ else {
+const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
+priority |= ipriority_val << byte_shift;
+ }
}
gicr_write_4(sc, ci->ci_gic_redist, GICR_IPRIORITYRn(n / 4), priority);
}
@@ -426,6 +429,8 @@ gicv3_ipi_send(struct pic_softc *pic, co
aff = 0;
targets = 0;
for (CPU_INFO_FOREACH(cii, ci)) {
+ if (!kcpuset_isset(kcp, cpu_index(ci)))
+continue;
if ((ci->ci_gic_sgir & ICC_SGIR_EL1_Aff) != aff) {
if (targets != 0) {
icc_sgi1r_write(intid | aff | targets);
@@ -474,7 +479,7 @@ gicv3_irq_handler(void *frame)
KASSERT(is != NULL);
const int ipl = is->is_ipl;
- if (ci->ci_cpl != ipl)
+ if (ci->ci_cpl < ipl)
pic_set_priority(ci, ipl);
cpsie(I32_bit);
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Wed Aug 8 19:02:28 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: files.cortex
Added Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h
Log Message:
Add GICv3 support.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/files.cortex
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/cortex/gicv3.c \
src/sys/arch/arm/cortex/gicv3.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/files.cortex
diff -u src/sys/arch/arm/cortex/files.cortex:1.7 src/sys/arch/arm/cortex/files.cortex:1.8
--- src/sys/arch/arm/cortex/files.cortex:1.7 Tue Jun 5 08:03:28 2018
+++ src/sys/arch/arm/cortex/files.cortex Wed Aug 8 19:02:28 2018
@@ -1,4 +1,4 @@
-# $NetBSD: files.cortex,v 1.7 2018/06/05 08:03:28 hkenken Exp $
+# $NetBSD: files.cortex,v 1.8 2018/08/08 19:02:28 jmcneill Exp $
defflag opt_cpu_in_cksum.h NEON_IN_CKSUM
@@ -16,6 +16,10 @@ device armgic: pic, pic_splfuncs
attach armgic at mpcorebus
file arch/arm/cortex/gic.c armgic
+# ARM Generic Interrupt Controller v3+
+device gicvthree: pic, pic_splfuncs
+file arch/arm/cortex/gicv3.c gicvthree
+
# ARM PL310 L2 Cache Controller(initially on Cortex-A9)
device arml2cc
attach arml2cc at mpcorebus
Added files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u /dev/null src/sys/arch/arm/cortex/gicv3.c:1.1
--- /dev/null Wed Aug 8 19:02:28 2018
+++ src/sys/arch/arm/cortex/gicv3.c Wed Aug 8 19:02:28 2018
@@ -0,0 +1,546 @@
+/* $NetBSD: gicv3.c,v 1.1 2018/08/08 19:02:28 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2018 Jared McNeill
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_multiprocessor.h"
+
+#define _INTR_PRIVATE
+
+#include
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.1 2018/08/08 19:02:28 jmcneill Exp $");
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+
+#define PICTOSOFTC(pic) \
+ ((void *)((uintptr_t)(pic) - offsetof(struct gicv3_softc, sc_pic)))
+
+#define IPL_TO_PRIORITY(ipl) ((IPL_HIGH - (ipl)) << 4)
+
+static struct gicv3_softc *gicv3_softc;
+
+static inline uint32_t
+gicd_read_4(struct gicv3_softc *sc, bus_size_t reg)
+{
+ return bus_space_read_4(sc->sc_bst, sc->sc_bsh_d, reg);
+}
+
+static inline void
+gicd_write_4(struct gicv3_softc *sc, bus_size_t reg, uint32_t val)
+{
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh_d, reg, val);
+}
+
+static inline void
+gicd_write_8(struct gicv3_softc *sc, bus_size_t reg, uint64_t val)
+{
+ bus_space_write_8(sc->sc_bst, sc->sc_bsh_d, reg, val);
+}
+
+static inline uint32_t
+gicr_read_4(struct gicv3_softc *sc, u_int index, bus_size_t reg)
+{
+ KASSERT(index < sc->sc_bsh_r_count);
+ return bus_space_read_4(sc->sc_bst, sc->sc_bsh_r[index], reg);
+}
+
+static inline void
+gicr_write_4(struct gicv3_softc *sc, u_int index, bus_size_t reg, uint32_t val)
+{
+ KASSERT(index < sc->sc_bsh_r_count);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh_r[index], reg, val);
+}
+
+static inline uint64_t
+gicr_read_8(struct gicv3_softc *sc, u_int index, bus_size_t reg)
+{
+ KASSERT(index < sc->sc_bsh_r_count);
+ return bus_space_read_8(sc->sc_bst, sc->sc_bsh_r[index], reg);
+}
+
+static inline void
+gicr_write_8(struct gicv3_softc *sc, u_int index, bus_size_t reg, uint64_t val)
+{
+ KASSERT(index < sc->sc_bsh_r_count);
+ bus_space_write_8(sc->sc_bst, sc->sc_bsh_r[index], reg, val);
+}
+
+static void
+gicv3_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask)
+{
+ struct gicv3_softc * const sc = PICTOSOFTC(pic);
+ struct cpu_info * const ci = curcpu();
+ const u_int group = irqbase / 32;
+
+
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Wed Aug 8 19:01:55 UTC 2018 Modified Files: src/sys/arch/arm/cortex: gic_reg.h Log Message: Update for GICv3 To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/gic_reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic_reg.h diff -u src/sys/arch/arm/cortex/gic_reg.h:1.6 src/sys/arch/arm/cortex/gic_reg.h:1.7 --- src/sys/arch/arm/cortex/gic_reg.h:1.6 Thu Jun 22 07:02:14 2017 +++ src/sys/arch/arm/cortex/gic_reg.h Wed Aug 8 19:01:54 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gic_reg.h,v 1.6 2017/06/22 07:02:14 skrll Exp $ */ +/* $NetBSD: gic_reg.h,v 1.7 2018/08/08 19:01:54 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -133,11 +133,20 @@ #define GICD_ITARGETSRn(n) (0x800+4*(n)) // Interrupt Processor Targets Registers #define GICD_ICFGRn(n) (0xC00+4*(n)) // Interrupt Configuration Registers +#define GICD_IGRPMODRn(n) (0xD00+4*(n)) // Interrupt Group Modifier Registers #define GICD_NSACRn(n) (0xE00+4*(n)) // Non-secure Access Control Registers, optional #define GICD_SGIR 0xF00 // Software Generated Interrupt Register #define GICD_CPENDSGIR(n) (0xF10+4*(n)) // SGI Clear-Pending Registers #define GICD_SPENDSGIR(n) (0xF20+4*(n)) // SGI Set-Pending Registers +#define GICD_IROUTER(n) (0x6100+8*(n)) // Interrupt Routing Registers +#define GICD_CTRL_RWP __BIT(31) // GICv3 +#define GICD_CTRL_E1NWF __BIT(7) // GICv3 +#define GICD_CTRL_DS __BIT(6) // GICv3 +#define GICD_CTRL_ARE_NS __BIT(5) // GICv3 +#define GICD_CTRL_ARE_S __BIT(4) // GICv3 +#define GICD_CTRL_EnableGrp1S __BIT(2) // GICv3 +#define GICD_CTRL_EnableGrp1NS __BIT(1) // GICv3 #define GICD_CTRL_Enable __BIT(0) #define GICD_TYPER_LSPI __BITS(15,11) @@ -175,6 +184,61 @@ #define GICD_SGIR_NSATT __BIT(15) #define GICD_SGIR_SGIINTID __BITS(3,0) +#define GICD_IROUTER_Aff3 __BITS(39,32) +#define GICD_IROUTER_Interrupt_Routing_mode __BIT(31) +#define GICD_IROUTER_Aff2 __BITS(23,16) +#define GICD_IROUTER_Aff1 __BITS(15,8) +#define GICD_IROUTER_Aff0 __BITS(7,0) + +#define GICR_CTRL 0x // Redistributor Control Register +#define GICR_IIDR 0x0004 // Implementor Identification Register +#define GICR_TYPER 0x0008 // Redistributor Type Register +#define GICR_STATUSR 0x0010 // Error Reporting Status Register, optional +#define GICR_WAKER 0x0014 // Redistributor Wake Register +#define GICR_SETLPIR 0x0040 // Set LPI Pending Register +#define GICR_CLRLPIR 0x0048 // Clear LPI Pending Register +#define GICR_PROPBASER 0x0070 // Redistributor Properties Base Address Register +#define GICR_PENDBASER 0x0078 // Redistributor LPI Pending Table Base Address Register +#define GICR_INVLPIR 0x00A0 // Redistributor Invalidate LPI Register +#define GICR_INVALLR 0x00B0 // Redistributor Invalidate All Register +#define GICR_SYNCR 0x00C0 // Redistributor Synchronize Register + +#define GICR_IGROUPR0 0x10080 // Interrupt Group Register 0 +#define GICR_ISENABLER0 0x10100 // Interrupt Set-Enable Register 0 +#define GICR_ICENABLER0 0x10180 // Interrupt Clear-Enable Register 0 +#define GICR_ISPENDR0 0x10200 // Interrupt Set-Pend Register 0 +#define GICR_ICPENDR0 0x10280 // Interrupt Clear-Pend Register 0 +#define GICR_ISACTIVER0 0x10300 // Interrupt Set-Active Register 0 +#define GICR_ICACTIVER0 0x10380 // Interrupt Clear-Active Register 0 +#define GICR_IPRIORITYRn(n) (0x10400+4*(n)) // Interrupt Priority Registers +#define GICR_ICFGRn(n) (0x10C00+4*(n)) // SGI (0) / PPI (1) Configuration Register +#define GICR_IGRPMODR0 0x10D00 // Interrupt Group Modifier Register 0 +#define GICR_NSACR 0x10E00 // Non-Secure Access Control Register + +#define GICR_CTRL_UWP __BIT(31) +#define GICR_CTRL_DPG1S __BIT(26) +#define GICR_CTRL_DPG1NS __BIT(25) +#define GICR_CTRL_DPG0 __BIT(24) +#define GICR_CTRL_RWP __BIT(3) +#define GICR_CTRL_Enable_LPIs __BIT(0) + +#define GICR_TYPER_Affinity_Value __BITS(63,32) +#define GICR_TYPER_Affinity_Value_Aff3 __BITS(63,56) +#define GICR_TYPER_Affinity_Value_Aff2 __BITS(55,48) +#define GICR_TYPER_Affinity_Value_Aff1 __BITS(47,40) +#define GICR_TYPER_Affinity_Value_Aff0 __BITS(39,32) +#define GICR_TYPER_CommonLPIAff __BITS(25,24) +#define GICR_TYPER_Processor_Number __BITS(23,8) +#define GICR_TYPER_DPGS __BIT(5) +#define GICR_TYPER_Last __BIT(4) +#define GICR_TYPER_DirectLPI __BIT(3) +#define GICR_TYPER_VLPIS __BIT(1) +#define GICR_TYPER_PLPIS __BIT(0) + +#define GICR_WAKER_ChildrenAsleep __BIT(2) +#define GICR_WAKER_ProcessorSleep __BIT(1) + + /* * GICv1 names */
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Jul 15 16:04:07 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Support pic_set_affinity and pic_get_affinity
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.34 src/sys/arch/arm/cortex/gic.c:1.35
--- src/sys/arch/arm/cortex/gic.c:1.34 Sat Apr 28 18:26:53 2018
+++ src/sys/arch/arm/cortex/gic.c Sun Jul 15 16:04:07 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.34 2018/04/28 18:26:53 jakllsch Exp $ */
+/* $NetBSD: gic.c,v 1.35 2018/07/15 16:04:07 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.34 2018/04/28 18:26:53 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.35 2018/07/15 16:04:07 jmcneill Exp $");
#include
#include
@@ -75,6 +75,8 @@ static void armgic_source_name(struct pi
#ifdef MULTIPROCESSOR
static void armgic_cpu_init(struct pic_softc *, struct cpu_info *);
static void armgic_ipi_send(struct pic_softc *, const kcpuset_t *, u_long);
+static void armgic_get_affinity(struct pic_softc *, size_t, kcpuset_t *);
+static int armgic_set_affinity(struct pic_softc *, size_t, const kcpuset_t *);
#endif
static const struct pic_ops armgic_picops = {
@@ -88,6 +90,8 @@ static const struct pic_ops armgic_picop
#ifdef MULTIPROCESSOR
.pic_cpu_init = armgic_cpu_init,
.pic_ipi_send = armgic_ipi_send,
+ .pic_get_affinity = armgic_get_affinity,
+ .pic_set_affinity = armgic_set_affinity,
#endif
};
@@ -104,6 +108,7 @@ static struct armgic_softc {
uint32_t sc_gic_valid_lines[1024/32];
uint32_t sc_enabled_local;
#ifdef MULTIPROCESSOR
+ uint32_t sc_target[MAXCPUS];
uint32_t sc_mptargets;
#endif
uint32_t sc_bptargets;
@@ -222,6 +227,63 @@ armgic_set_priority(struct pic_softc *pi
gicc_write(sc, GICC_PMR, priority);
}
+#ifdef MULTIPROCESSOR
+static void
+armgic_get_affinity(struct pic_softc *pic, size_t irq, kcpuset_t *affinity)
+{
+ struct armgic_softc * const sc = PICTOSOFTC(pic);
+ const size_t group = irq / 32;
+ int n;
+
+ kcpuset_zero(affinity);
+ if (group == 0) {
+ /* All CPUs are targets for group 0 (SGI/PPI) */
+ for (n = 0; n < MAXCPUS; n++) {
+ if (sc->sc_target[n] != 0)
+kcpuset_set(affinity, n);
+ }
+ } else {
+ /* Find distributor targets (SPI) */
+ const u_int byte_shift = 8 * (irq & 3);
+ const bus_size_t targets_reg = GICD_ITARGETSRn(irq / 4);
+ const uint32_t targets = gicd_read(sc, targets_reg);
+ const uint32_t targets_val = (targets >> byte_shift) & 0xff;
+
+ for (n = 0; n < MAXCPUS; n++) {
+ if (sc->sc_target[n] & targets_val)
+kcpuset_set(affinity, n);
+ }
+ }
+}
+
+static int
+armgic_set_affinity(struct pic_softc *pic, size_t irq,
+const kcpuset_t *affinity)
+{
+ struct armgic_softc * const sc = PICTOSOFTC(pic);
+ const size_t group = irq / 32;
+ if (group == 0)
+ return EINVAL;
+
+ const u_int byte_shift = 8 * (irq & 3);
+ const bus_size_t targets_reg = GICD_ITARGETSRn(irq / 4);
+ uint32_t targets_val = 0;
+ int n;
+
+ for (n = 0; n < MAXCPUS; n++) {
+ if (kcpuset_isset(affinity, n))
+ targets_val |= sc->sc_target[n];
+ }
+
+ uint32_t targets = gicd_read(sc, targets_reg);
+ targets &= ~(0xff << byte_shift);
+ targets |= (targets_val << byte_shift);
+ gicd_write(sc, targets_reg, targets);
+
+ return 0;
+}
+#endif
+
#ifdef __HAVE_PIC_FAST_SOFTINTS
void
softint_init_md(lwp_t *l, u_int level, uintptr_t *machdep_p)
@@ -451,7 +513,8 @@ void
armgic_cpu_init(struct pic_softc *pic, struct cpu_info *ci)
{
struct armgic_softc * const sc = PICTOSOFTC(pic);
- sc->sc_mptargets |= gicd_find_targets(sc);
+ sc->sc_target[cpu_index(ci)] = gicd_find_targets(sc);
+ sc->sc_mptargets |= sc->sc_target[cpu_index(ci)];
KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl);
armgic_cpu_init_priorities(sc);
if (!CPU_IS_PRIMARY(ci)) {
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Jun 30 17:30:37 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
ARM ARM refers to this as "ARM Generic Timer", so adjust printf at attach
to match.
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.31 src/sys/arch/arm/cortex/gtmr.c:1.32
--- src/sys/arch/arm/cortex/gtmr.c:1.31 Sun Jun 24 19:04:30 2018
+++ src/sys/arch/arm/cortex/gtmr.c Sat Jun 30 17:30:37 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.31 2018/06/24 19:04:30 ryo Exp $ */
+/* $NetBSD: gtmr.c,v 1.32 2018/06/30 17:30:37 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.31 2018/06/24 19:04:30 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.32 2018/06/30 17:30:37 jmcneill Exp $");
#include
#include
@@ -152,7 +152,7 @@ gtmr_attach(device_t parent, device_t se
humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000);
aprint_naive("\n");
- aprint_normal(": ARMv7 Generic 64-bit Timer (%s)\n", freqbuf);
+ aprint_normal(": ARM Generic Timer (%s)\n", freqbuf);
/*
* Enable the virtual counter to be accessed from usermode.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: ryo Date: Wed Jun 27 11:05:50 UTC 2018 Modified Files: src/sys/arch/arm/cortex: a9_mpsubr.S Log Message: keep stack pointer even if chainging CPU mode. To generate a diff of this commit: cvs rdiff -u -r1.55 -r1.56 src/sys/arch/arm/cortex/a9_mpsubr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/a9_mpsubr.S diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.55 src/sys/arch/arm/cortex/a9_mpsubr.S:1.56 --- src/sys/arch/arm/cortex/a9_mpsubr.S:1.55 Thu Jan 18 12:49:09 2018 +++ src/sys/arch/arm/cortex/a9_mpsubr.S Wed Jun 27 11:05:50 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: a9_mpsubr.S,v 1.55 2018/01/18 12:49:09 skrll Exp $ */ +/* $NetBSD: a9_mpsubr.S,v 1.56 2018/06/27 11:05:50 ryo Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -351,6 +351,7 @@ xputc: // cortex_init: mov r10, lr// save lr + mov r9, sp// save sp #if defined(CPU_CORTEXVIRT) /* Leave HYP mode and move into supervisor mode with IRQs/FIQs disabled. */ @@ -380,6 +381,8 @@ cortex_init: mov r0, #0 msr spsr_sxc, r0 // set SPSR[23:8] to known value + mov sp, r9// restore sp + #if 0 mrc p14, 0, r0, c0, c0, 0 // MIDR read ufbx r0, r0, #4, #4 // extract cortex part.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: ryo
Date: Sun Jun 24 19:04:30 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
fixed a case of gtmr_cntvct_stable_read() is returning the same value as before.
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.30 src/sys/arch/arm/cortex/gtmr.c:1.31
--- src/sys/arch/arm/cortex/gtmr.c:1.30 Sun Jun 17 22:42:41 2018
+++ src/sys/arch/arm/cortex/gtmr.c Sun Jun 24 19:04:30 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.30 2018/06/17 22:42:41 jmcneill Exp $ */
+/* $NetBSD: gtmr.c,v 1.31 2018/06/24 19:04:30 ryo Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.30 2018/06/17 22:42:41 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.31 2018/06/24 19:04:30 ryo Exp $");
#include
#include
@@ -261,7 +261,7 @@ gtmr_delay(unsigned int n)
while (ticks > 0) {
arm_isb();
uint64_t curr = gtmr_cntvct_stable_read(sc);
- if (curr > last)
+ if (curr >= last)
ticks -= (curr - last);
else
ticks -= (UINT64_MAX - curr + last);
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: hkenken
Date: Wed Jun 20 05:01:40 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: a9tmr.c a9tmr_var.h
Log Message:
Use mpcaa_off1 parameter for mapping subregion.
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/a9tmr.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/a9tmr_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9tmr.c
diff -u src/sys/arch/arm/cortex/a9tmr.c:1.15 src/sys/arch/arm/cortex/a9tmr.c:1.16
--- src/sys/arch/arm/cortex/a9tmr.c:1.15 Tue Jun 5 08:03:28 2018
+++ src/sys/arch/arm/cortex/a9tmr.c Wed Jun 20 05:01:39 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: a9tmr.c,v 1.15 2018/06/05 08:03:28 hkenken Exp $ */
+/* $NetBSD: a9tmr.c,v 1.16 2018/06/20 05:01:39 hkenken Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.15 2018/06/05 08:03:28 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.16 2018/06/20 05:01:39 hkenken Exp $");
#include
#include
@@ -147,12 +147,8 @@ a9tmr_attach(device_t parent, device_t s
evcnt_attach_dynamic(>sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL,
device_xname(self), "missing interrupts");
- bus_space_subregion(sc->sc_memt, sc->sc_memh,
- TMR_GLOBAL_BASE, TMR_GLOBAL_SIZE, >sc_global_memh);
- bus_space_subregion(sc->sc_memt, sc->sc_memh,
- TMR_PRIVATE_BASE, TMR_PRIVATE_SIZE, >sc_private_memh);
- bus_space_subregion(sc->sc_memt, sc->sc_memh,
- TMR_WDOG_BASE, TMR_WDOG_SIZE, >sc_wdog_memh);
+ bus_space_subregion(sc->sc_memt, sc->sc_memh,
+ mpcaa->mpcaa_off1, TMR_GLOBAL_SIZE, >sc_global_memh);
if (mpcaa->mpcaa_irq != -1) {
sc->sc_global_ih = intr_establish(mpcaa->mpcaa_irq, IPL_CLOCK,
Index: src/sys/arch/arm/cortex/a9tmr_var.h
diff -u src/sys/arch/arm/cortex/a9tmr_var.h:1.5 src/sys/arch/arm/cortex/a9tmr_var.h:1.6
--- src/sys/arch/arm/cortex/a9tmr_var.h:1.5 Tue Jun 5 08:03:28 2018
+++ src/sys/arch/arm/cortex/a9tmr_var.h Wed Jun 20 05:01:39 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: a9tmr_var.h,v 1.5 2018/06/05 08:03:28 hkenken Exp $ */
+/* $NetBSD: a9tmr_var.h,v 1.6 2018/06/20 05:01:39 hkenken Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -36,8 +36,6 @@ struct a9tmr_softc {
bus_space_tag_t sc_memt;
bus_space_handle_t sc_memh;
bus_space_handle_t sc_global_memh;
- bus_space_handle_t sc_private_memh;
- bus_space_handle_t sc_wdog_memh;
struct evcnt sc_ev_missing_ticks;
uint32_t sc_freq;
u_long sc_autoinc;
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Jun 17 22:42:41 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Simplify gtmr_delay and don't mix and match usage of the physical and
virtual timers (always use the virtual timer).
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.29 src/sys/arch/arm/cortex/gtmr.c:1.30
--- src/sys/arch/arm/cortex/gtmr.c:1.29 Sat Jun 9 01:17:35 2018
+++ src/sys/arch/arm/cortex/gtmr.c Sun Jun 17 22:42:41 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.29 2018/06/09 01:17:35 jakllsch Exp $ */
+/* $NetBSD: gtmr.c,v 1.30 2018/06/17 22:42:41 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.29 2018/06/09 01:17:35 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.30 2018/06/17 22:42:41 jmcneill Exp $");
#include
#include
@@ -89,7 +89,6 @@ reg ## _stable_read(struct gtmr_softc *s
stable_read(gtmr_cntv_cval);
stable_read(gtmr_cntvct);
-stable_read(gtmr_cntpct);
static int gtmr_match(device_t, cfdata_t, void *);
static void gtmr_attach(device_t, device_t, void *);
@@ -177,8 +176,6 @@ gtmr_attach(device_t parent, device_t se
device_xname(self), "CNTV_CVAL read retry max");
evcnt_attach_dynamic(_cntvct_read_ev, EVCNT_TYPE_MISC, NULL,
device_xname(self), "CNTVCT read retry max");
- evcnt_attach_dynamic(_cntpct_read_ev, EVCNT_TYPE_MISC, NULL,
- device_xname(self), "CNTPCT read retry max");
if (mpcaa->mpcaa_irq != -1) {
sc->sc_global_ih = intr_establish(mpcaa->mpcaa_irq, IPL_CLOCK,
@@ -256,24 +253,19 @@ gtmr_delay(unsigned int n)
KASSERT(freq != 0);
const unsigned int incr_per_us = howmany(freq, 100);
- unsigned int delta = 0, usecs = 0;
+ int64_t ticks = (int64_t)n * incr_per_us;
arm_isb();
- uint64_t last = gtmr_cntpct_stable_read(sc);
+ uint64_t last = gtmr_cntvct_stable_read(sc);
- while (n > usecs) {
+ while (ticks > 0) {
arm_isb();
- uint64_t curr = gtmr_cntpct_stable_read(sc);
- if (curr < last)
- delta += curr + (UINT64_MAX - last);
+ uint64_t curr = gtmr_cntvct_stable_read(sc);
+ if (curr > last)
+ ticks -= (curr - last);
else
- delta += curr - last;
-
+ ticks -= (UINT64_MAX - curr + last);
last = curr;
- if (delta >= incr_per_us) {
- usecs += delta / incr_per_us;
- delta %= incr_per_us;
- }
}
}
@@ -347,5 +339,5 @@ gtmr_get_timecount(struct timecounter *t
{
struct gtmr_softc * const sc = tc->tc_priv;
arm_isb(); // we want the time NOW, not some instructions later.
- return (u_int) gtmr_cntpct_stable_read(sc);
+ return (u_int) gtmr_cntvct_stable_read(sc);
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jakllsch Date: Sat Jun 9 01:17:35 UTC 2018 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: Avoid unnecessarily touching CNTP_CTL. We may not have the privilege of accessing CNTP_CTL if running as a virtualized guest, and we're not using the Physical Timer for interupt generation anyway. To generate a diff of this commit: cvs rdiff -u -r1.28 -r1.29 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gtmr.c diff -u src/sys/arch/arm/cortex/gtmr.c:1.28 src/sys/arch/arm/cortex/gtmr.c:1.29 --- src/sys/arch/arm/cortex/gtmr.c:1.28 Mon May 21 10:28:13 2018 +++ src/sys/arch/arm/cortex/gtmr.c Sat Jun 9 01:17:35 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gtmr.c,v 1.28 2018/05/21 10:28:13 jmcneill Exp $ */ +/* $NetBSD: gtmr.c,v 1.29 2018/06/09 01:17:35 jakllsch Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.28 2018/05/21 10:28:13 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.29 2018/06/09 01:17:35 jakllsch Exp $"); #include #include @@ -206,7 +206,6 @@ gtmr_attach(device_t parent, device_t se /* Disable the timer until we are ready */ gtmr_cntv_ctl_write(0); - gtmr_cntp_ctl_write(0); } void @@ -222,7 +221,6 @@ gtmr_init_cpu_clock(struct cpu_info *ci) * enable timer and stop masking the timer. */ gtmr_cntv_ctl_write(CNTCTL_ENABLE); - gtmr_cntp_ctl_write(CNTCTL_ENABLE); /* * Get now and update the compare timer.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Mon May 21 10:28:13 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Replace stable_read/write debug printfs with event counters
To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.27 src/sys/arch/arm/cortex/gtmr.c:1.28
--- src/sys/arch/arm/cortex/gtmr.c:1.27 Mon May 14 17:15:54 2018
+++ src/sys/arch/arm/cortex/gtmr.c Mon May 21 10:28:13 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.27 2018/05/14 17:15:54 joerg Exp $ */
+/* $NetBSD: gtmr.c,v 1.28 2018/05/21 10:28:13 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.27 2018/05/14 17:15:54 joerg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.28 2018/05/21 10:28:13 jmcneill Exp $");
#include
#include
@@ -51,29 +51,27 @@ __KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.2
#include
#define stable_write(reg) \
+static struct evcnt reg ## _write_ev; \
static void \
reg ## _stable_write(struct gtmr_softc *sc, uint64_t val) \
{ \
- static int max_retry = 0; \
int retry; \
reg ## _write(val); \
retry = 0; \
while (reg ## _read() != (val) && retry++ < 200) \
reg ## _write(val); \
- if (retry > max_retry) { \
- aprint_verbose_dev(sc->sc_dev, #reg "_write max retries %d -> %d\n", \
- max_retry, retry); \
- max_retry = retry; \
+ if (retry > reg ## _write_ev.ev_count) { \
+ reg ## _write_ev.ev_count = retry; \
} \
}
stable_write(gtmr_cntv_tval);
#define stable_read(reg) \
+static struct evcnt reg ## _read_ev; \
static uint64_t \
reg ## _stable_read(struct gtmr_softc *sc) \
{ \
- static int max_retry = 0; \
uint64_t oval, val; \
int retry = 0; \
val = reg ## _read(); \
@@ -83,10 +81,8 @@ reg ## _stable_read(struct gtmr_softc *s
if (val == oval) \
break; \
} \
- if (retry > max_retry) { \
- aprint_verbose_dev(sc->sc_dev, #reg "_read max retries %d -> %d\n", \
- max_retry, retry); \
- max_retry = retry; \
+ if (retry > reg ## _read_ev.ev_count) { \
+ reg ## _read_ev.ev_count = retry; \
} \
return val; \
}
@@ -175,6 +171,15 @@ gtmr_attach(device_t parent, device_t se
evcnt_attach_dynamic(>sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL,
device_xname(self), "missing interrupts");
+ evcnt_attach_dynamic(_cntv_tval_write_ev, EVCNT_TYPE_MISC, NULL,
+ device_xname(self), "CNTV_TVAL write retry max");
+ evcnt_attach_dynamic(_cntv_cval_read_ev, EVCNT_TYPE_MISC, NULL,
+ device_xname(self), "CNTV_CVAL read retry max");
+ evcnt_attach_dynamic(_cntvct_read_ev, EVCNT_TYPE_MISC, NULL,
+ device_xname(self), "CNTVCT read retry max");
+ evcnt_attach_dynamic(_cntpct_read_ev, EVCNT_TYPE_MISC, NULL,
+ device_xname(self), "CNTPCT read retry max");
+
if (mpcaa->mpcaa_irq != -1) {
sc->sc_global_ih = intr_establish(mpcaa->mpcaa_irq, IPL_CLOCK,
IST_LEVEL | IST_MPSAFE, gtmr_intr, NULL);
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: joerg
Date: Mon May 14 17:11:38 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Remove a number of debug #if 0s.
To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.25 src/sys/arch/arm/cortex/gtmr.c:1.26
--- src/sys/arch/arm/cortex/gtmr.c:1.25 Mon May 14 17:09:41 2018
+++ src/sys/arch/arm/cortex/gtmr.c Mon May 14 17:11:38 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.25 2018/05/14 17:09:41 joerg Exp $ */
+/* $NetBSD: gtmr.c,v 1.26 2018/05/14 17:11:38 joerg Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.25 2018/05/14 17:09:41 joerg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.26 2018/05/14 17:11:38 joerg Exp $");
#include
#include
@@ -172,9 +172,6 @@ gtmr_init_cpu_clock(struct cpu_info *ci)
*/
gtmr_cntv_ctl_write(CNTCTL_ENABLE);
gtmr_cntp_ctl_write(CNTCTL_ENABLE);
-#if 0
- printf("%s: cntctl=%#x\n", __func__, gtmr_cntv_ctl_read());
-#endif
/*
* Get now and update the compare timer.
@@ -182,47 +179,8 @@ gtmr_init_cpu_clock(struct cpu_info *ci)
arm_isb();
ci->ci_lastintr = gtmr_cntvct_read();
gtmr_cntv_tval_write(sc->sc_autoinc);
-#if 0
- printf("%s: %s: delta cval = %"PRIu64"\n",
- __func__, ci->ci_data.cpu_name,
- gtmr_cntv_cval_read() - ci->ci_lastintr);
-#endif
splx(s);
KASSERT(gtmr_cntvct_read() != 0);
-#if 0
- printf("%s: %s: ctl %#x cmp %#"PRIx64" now %#"PRIx64"\n",
- __func__, ci->ci_data.cpu_name, gtmr_cntv_ctl_read(),
- gtmr_cntv_cval_read(), gtmr_cntvct_read());
-
- s = splsched();
-
- arm_isb();
- uint64_t now64;
- uint64_t start64 = gtmr_cntvct_read();
- do {
- arm_isb();
- now64 = gtmr_cntvct_read();
- } while (start64 == now64);
- start64 = now64;
- uint64_t end64 = start64 + 64;
- uint32_t start32 = arm_pmccntr_read();
- do {
- arm_isb();
- now64 = gtmr_cntvct_read();
- } while (end64 != now64);
- uint32_t end32 = arm_pmccntr_read();
-
- uint32_t diff32 = end64 - start64;
- printf("%s: %s: %u cycles per tick\n",
- __func__, ci->ci_data.cpu_name, (end32 - start32) / diff32);
-
- printf("%s: %s: status %#x cmp %#"PRIx64" now %#"PRIx64"\n",
- __func__, ci->ci_data.cpu_name, gtmr_cntv_ctl_read(),
- gtmr_cntv_cval_read(), gtmr_cntvct_read());
- splx(s);
-#elif 0
- delay(100 / hz + 1000);
-#endif
}
void
@@ -299,10 +257,6 @@ gtmr_intr(void *arg)
"%"PRId64, then + pc->pc_delta - ci->ci_lastintr - sc->sc_autoinc);
#endif
-#if 0
- printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n",
- __func__, cf, ci->ci_data.cpu_name, now, delta);
-#endif
KASSERTMSG(delta > sc->sc_autoinc / 100,
"%s: interrupting too quickly (delta=%"PRIu64") autoinc=%lu",
ci->ci_data.cpu_name, delta, sc->sc_autoinc);
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: joerg
Date: Mon May 14 17:09:41 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gtmr.c gtmr_var.h
Log Message:
Remove unused gtmr_bootdelay.
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/cortex/gtmr.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gtmr_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.24 src/sys/arch/arm/cortex/gtmr.c:1.25
--- src/sys/arch/arm/cortex/gtmr.c:1.24 Sun Apr 1 04:35:04 2018
+++ src/sys/arch/arm/cortex/gtmr.c Mon May 14 17:09:41 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.24 2018/04/01 04:35:04 ryo Exp $ */
+/* $NetBSD: gtmr.c,v 1.25 2018/05/14 17:09:41 joerg Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.24 2018/04/01 04:35:04 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.25 2018/05/14 17:09:41 joerg Exp $");
#include
#include
@@ -270,23 +270,6 @@ gtmr_delay(unsigned int n)
}
}
-void
-gtmr_bootdelay(unsigned int ticks)
-{
- const uint32_t ctl = gtmr_cntv_ctl_read();
- gtmr_cntv_ctl_write(ctl | CNTCTL_ENABLE | CNTCTL_IMASK);
-
- /* Write Timer/Value to set new compare time */
- gtmr_cntv_tval_write(ticks);
-
- /* Spin until compare time is hit */
- while ((gtmr_cntv_ctl_read() & CNTCTL_ISTATUS) == 0) {
- /* spin */
- }
-
- gtmr_cntv_ctl_write(ctl);
-}
-
/*
* gtmr_intr:
*
Index: src/sys/arch/arm/cortex/gtmr_var.h
diff -u src/sys/arch/arm/cortex/gtmr_var.h:1.9 src/sys/arch/arm/cortex/gtmr_var.h:1.10
--- src/sys/arch/arm/cortex/gtmr_var.h:1.9 Thu Nov 30 14:50:34 2017
+++ src/sys/arch/arm/cortex/gtmr_var.h Mon May 14 17:09:41 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr_var.h,v 1.9 2017/11/30 14:50:34 skrll Exp $ */
+/* $NetBSD: gtmr_var.h,v 1.10 2018/05/14 17:09:41 joerg Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -51,7 +51,6 @@ void gtmr_init(device_t);
int gtmr_intr(void *);
void gtmr_init_cpu_clock(struct cpu_info *);
void gtmr_delay(unsigned int n);
-void gtmr_bootdelay(unsigned int n);
#ifdef __HAVE_GENERIC_CPU_INITCLOCKS
void gtmr_cpu_initclocks(void);
#else
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jakllsch
Date: Sat Apr 28 18:26:53 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Cover all pic_maxsources lines for armgic_cpu_init_priorities() and
armgic_cpu_update_priorities().
Previously only the first 32 lines were covered, which is significantly
less than the 1000-some interrupt lines possible.
Only relevant to MULTIPROCESSOR configurations.
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.33 src/sys/arch/arm/cortex/gic.c:1.34
--- src/sys/arch/arm/cortex/gic.c:1.33 Sun Apr 1 04:35:04 2018
+++ src/sys/arch/arm/cortex/gic.c Sat Apr 28 18:26:53 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.33 2018/04/01 04:35:04 ryo Exp $ */
+/* $NetBSD: gic.c,v 1.34 2018/04/28 18:26:53 jakllsch Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.33 2018/04/01 04:35:04 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.34 2018/04/28 18:26:53 jakllsch Exp $");
#include
#include
@@ -402,7 +402,7 @@ static void
armgic_cpu_init_priorities(struct armgic_softc *sc)
{
/* Set lowest priority, i.e. disable interrupts */
- for (size_t i = 0; i < 32; i += 4) {
+ for (size_t i = 0; i < sc->sc_pic.pic_maxsources; i += 4) {
const bus_size_t priority_reg = GICD_IPRIORITYRn(i / 4);
gicd_write(sc, priority_reg, ~0);
}
@@ -412,7 +412,7 @@ static void
armgic_cpu_update_priorities(struct armgic_softc *sc)
{
uint32_t enabled = sc->sc_enabled_local;
- for (size_t i = 0; i < 32; i += 4, enabled >>= 4) {
+ for (size_t i = 0; i < sc->sc_pic.pic_maxsources; i += 4, enabled >>= 4) {
const bus_size_t priority_reg = GICD_IPRIORITYRn(i / 4);
uint32_t priority = gicd_read(sc, priority_reg);
uint32_t byte_mask = 0xff;
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Wed Feb 7 20:42:17 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC
The priority level is changed by writing to GICC_PMR with interrupts
disabled. However, interrupts are enabled/disabled downstream of the GICC
at the CPU. When raising priority level, there is a window between the time
that interrupts are disabled and the GICC_PMR register is written. If an
interrupt occurs at a previously allowed priority before GICC_PMR is
changed, the CPU will receive the signal when interrupts are re-enabled.
At this time, GICC_PMR is now the new priority level, so reads of
GICC_IAR will report a spurious IRQ.
Move the "old_ipl != IPL_HIGH" test until after we have confirmed that
there is at least one pending IRQ.
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.31 src/sys/arch/arm/cortex/gic.c:1.32
--- src/sys/arch/arm/cortex/gic.c:1.31 Fri Jul 14 06:33:26 2017
+++ src/sys/arch/arm/cortex/gic.c Wed Feb 7 20:42:17 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.31 2017/07/14 06:33:26 skrll Exp $ */
+/* $NetBSD: gic.c,v 1.32 2018/02/07 20:42:17 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.31 2017/07/14 06:33:26 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.32 2018/02/07 20:42:17 jmcneill Exp $");
#include
#include
@@ -259,9 +259,6 @@ armgic_irq_handler(void *tf)
ci->ci_data.cpu_nintr++;
- KASSERTMSG(old_ipl != IPL_HIGH, "old_ipl %d pmr %#x hppir %#x",
- old_ipl, gicc_read(sc, GICC_PMR), gicc_read(sc, GICC_HPPIR));
-
for (;;) {
uint32_t iar = gicc_read(sc, GICC_IAR);
uint32_t irq = __SHIFTOUT(iar, GICC_IAR_IRQ);
@@ -277,6 +274,9 @@ armgic_irq_handler(void *tf)
}
}
+ KASSERTMSG(old_ipl != IPL_HIGH, "old_ipl %d pmr %#x hppir %#x",
+ old_ipl, gicc_read(sc, GICC_PMR), gicc_read(sc, GICC_HPPIR));
+
//const uint32_t cpuid = __SHIFTOUT(iar, GICC_IAR_CPUID_MASK);
struct intrsource * const is = sc->sc_pic.pic_sources[irq];
KASSERT(is != _dummy_source);
@@ -318,7 +318,6 @@ armgic_irq_handler(void *tf)
/*
* Now handle any pending ints.
*/
- KASSERT(old_ipl != IPL_HIGH);
pic_do_pending_ints(I32_bit, old_ipl, tf);
KASSERTMSG(ci->ci_cpl == old_ipl, "ci_cpl %d old_ipl %d", ci->ci_cpl, old_ipl);
KASSERT(old_mtx_count == ci->ci_mtx_count);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Thu Jan 18 12:49:09 UTC 2018 Modified Files: src/sys/arch/arm/cortex: a9_mpsubr.S Log Message: Use r0 in the tlbiall instruction to avoid confusion. >From Ramakrishna Rao Desetti To generate a diff of this commit: cvs rdiff -u -r1.54 -r1.55 src/sys/arch/arm/cortex/a9_mpsubr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/a9_mpsubr.S diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.54 src/sys/arch/arm/cortex/a9_mpsubr.S:1.55 --- src/sys/arch/arm/cortex/a9_mpsubr.S:1.54 Sun Dec 10 21:38:26 2017 +++ src/sys/arch/arm/cortex/a9_mpsubr.S Thu Jan 18 12:49:09 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: a9_mpsubr.S,v 1.54 2017/12/10 21:38:26 skrll Exp $ */ +/* $NetBSD: a9_mpsubr.S,v 1.55 2018/01/18 12:49:09 skrll Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -506,7 +506,7 @@ cortex_init: // turning on SMP. // mov r0, #0 - mcr p15, 0, r1, c8, c7, 0 // TLBIALL (just this core) + mcr p15, 0, r0, c8, c7, 0 // TLBIALL (just this core) #endif // For the A7, SMP must be on ldrex/strex to work.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Fri Dec 29 11:07:03 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: a9wdt.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/a9wdt.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9wdt.c
diff -u src/sys/arch/arm/cortex/a9wdt.c:1.6 src/sys/arch/arm/cortex/a9wdt.c:1.7
--- src/sys/arch/arm/cortex/a9wdt.c:1.6 Fri Dec 29 11:06:26 2017
+++ src/sys/arch/arm/cortex/a9wdt.c Fri Dec 29 11:07:03 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: a9wdt.c,v 1.6 2017/12/29 11:06:26 skrll Exp $ */
+/* $NetBSD: a9wdt.c,v 1.7 2017/12/29 11:07:03 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.6 2017/12/29 11:06:26 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.7 2017/12/29 11:07:03 skrll Exp $");
#include
#include
@@ -191,7 +191,7 @@ a9wdt_attach(device_t parent, device_t s
sc->sc_dev = self;
sc->sc_memt = mpcaa->mpcaa_memt;
- bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh,
+ bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh,
TMR_WDOG_BASE, TMR_WDOG_SIZE, >sc_wdog_memh);
/*
@@ -203,7 +203,7 @@ a9wdt_attach(device_t parent, device_t s
sc->sc_wdog_ctl = a9wdt_wdog_read(sc, TMR_CTL);
sc->sc_wdog_armed = (sc->sc_wdog_ctl & TMR_CTL_WDOG_MODE) != 0;
if (sc->sc_wdog_armed) {
- sc->sc_wdog_prescaler =
+ sc->sc_wdog_prescaler =
__SHIFTOUT(sc->sc_wdog_ctl, TMR_CTL_PRESCALER) + 1;
sc->sc_freq /= sc->sc_wdog_prescaler;
sc->sc_wdog_load = a9wdt_wdog_read(sc, TMR_LOAD);
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Fri Dec 29 11:06:27 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: a9wdt.c armperiph.c
Log Message:
Set attached to true when attach completes.
Reported by Ramakrishna Rao Desetti on port-arm
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/a9wdt.c
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/cortex/armperiph.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9wdt.c
diff -u src/sys/arch/arm/cortex/a9wdt.c:1.5 src/sys/arch/arm/cortex/a9wdt.c:1.6
--- src/sys/arch/arm/cortex/a9wdt.c:1.5 Tue Oct 4 15:12:29 2016
+++ src/sys/arch/arm/cortex/a9wdt.c Fri Dec 29 11:06:26 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: a9wdt.c,v 1.5 2016/10/04 15:12:29 kiyohara Exp $ */
+/* $NetBSD: a9wdt.c,v 1.6 2017/12/29 11:06:26 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.5 2016/10/04 15:12:29 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.6 2017/12/29 11:06:26 skrll Exp $");
#include
#include
@@ -257,4 +257,6 @@ a9wdt_attach(device_t parent, device_t s
if (sysmon_wdog_register(>sc_smw) != 0)
aprint_error("%s: unable to register with sysmon\n",
device_xname(sc->sc_dev));
+
+ attached = true;
}
Index: src/sys/arch/arm/cortex/armperiph.c
diff -u src/sys/arch/arm/cortex/armperiph.c:1.11 src/sys/arch/arm/cortex/armperiph.c:1.12
--- src/sys/arch/arm/cortex/armperiph.c:1.11 Fri May 26 21:17:46 2017
+++ src/sys/arch/arm/cortex/armperiph.c Fri Dec 29 11:06:26 2017
@@ -31,7 +31,7 @@
#include
-__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.11 2017/05/26 21:17:46 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.12 2017/12/29 11:06:26 skrll Exp $");
#include
#include
@@ -237,4 +237,5 @@ armperiph_attach(device_t parent, device
config_found(self, , NULL);
}
+ attached = true;
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: matt Date: Fri Nov 10 22:54:20 UTC 2017 Modified Files: src/sys/arch/arm/cortex: a9_mpsubr.S Log Message: Add #define CPU_CORTEDVIRT to reduce copied complex ifdef. Shrink HYP test To generate a diff of this commit: cvs rdiff -u -r1.52 -r1.53 src/sys/arch/arm/cortex/a9_mpsubr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/a9_mpsubr.S diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.52 src/sys/arch/arm/cortex/a9_mpsubr.S:1.53 --- src/sys/arch/arm/cortex/a9_mpsubr.S:1.52 Sat Nov 4 17:09:55 2017 +++ src/sys/arch/arm/cortex/a9_mpsubr.S Fri Nov 10 22:54:20 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: a9_mpsubr.S,v 1.52 2017/11/04 17:09:55 skrll Exp $ */ +/* $NetBSD: a9_mpsubr.S,v 1.53 2017/11/10 22:54:20 matt Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -50,9 +50,11 @@ blx ip #endif -#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17) +#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17) \ +|| defined(CPU_CORTEXA35) .arch armv7a - .arch_extension virt + .arch_extension virt +#define CPU_CORTEXVIRT #endif // We'll modify va and pa at run time so we can use relocatable addresses. @@ -350,21 +352,19 @@ xputc: cortex_init: mov r10, lr// save lr -#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17) +#if defined(CPU_CORTEXVIRT) /* Leave HYP mode and move into supervisor mode with IRQs/FIQs disabled. */ mrs r0, cpsr - and r0, r0, #(PSR_MODE) /* Mode is in the low 5 bits of CPSR */ - teq r0, #(PSR_HYP32_MODE) /* Hyp Mode? */ + and r1, r0, #(PSR_MODE) /* Mode is in the low 5 bits of CPSR */ + teq r1, #(PSR_HYP32_MODE) /* Hyp Mode? */ bne 1f /* Set CNTVOFF to 0 */ - mov r0, #0 - mcrr p15, 4, r0, r0, c14 + mov r1, #0 + mcrr p15, 4, r1, r1, c14 /* Ensure that IRQ, and FIQ will be disabled after eret */ - mrs r0, cpsr - bic r0, r0, #(PSR_MODE) - orr r0, r0, #(PSR_SVC32_MODE) + eor r0, r0, #(PSR_SVC32_MODE^PSR_HYP32_MODE) orr r0, r0, #(I32_bit | F32_bit) msr spsr_cxsf, r0 /* Exit hypervisor mode */
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Thu Nov 9 21:38:25 UTC 2017 Modified Files: src/sys/arch/arm/cortex: gtmr_var.h Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/gtmr_var.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gtmr_var.h diff -u src/sys/arch/arm/cortex/gtmr_var.h:1.7 src/sys/arch/arm/cortex/gtmr_var.h:1.8 --- src/sys/arch/arm/cortex/gtmr_var.h:1.7 Thu Aug 24 13:06:23 2017 +++ src/sys/arch/arm/cortex/gtmr_var.h Thu Nov 9 21:38:25 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: gtmr_var.h,v 1.7 2017/08/24 13:06:23 jmcneill Exp $ */ +/* $NetBSD: gtmr_var.h,v 1.8 2017/11/09 21:38:25 skrll Exp $ */ /*- * Copyright (c) 2013 The NetBSD Foundation, Inc. * All rights reserved. @@ -53,7 +53,7 @@ void gtmr_delay(unsigned int n); void gtmr_bootdelay(unsigned int n); #ifdef __HAVE_GENERIC_CPU_INITCLOCKS void gtmr_cpu_initclocks(void); -#else +#else #define gtmr_cpu_initclocks cpu_initclocks #endif #endif
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sat Nov 4 17:09:55 UTC 2017 Modified Files: src/sys/arch/arm/cortex: a9_mpsubr.S Log Message: Ensure CNTVOFF is 0 before dropping out of Hyp mode CVS -- To generate a diff of this commit: cvs rdiff -u -r1.51 -r1.52 src/sys/arch/arm/cortex/a9_mpsubr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/a9_mpsubr.S diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.51 src/sys/arch/arm/cortex/a9_mpsubr.S:1.52 --- src/sys/arch/arm/cortex/a9_mpsubr.S:1.51 Fri Sep 22 06:31:02 2017 +++ src/sys/arch/arm/cortex/a9_mpsubr.S Sat Nov 4 17:09:55 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: a9_mpsubr.S,v 1.51 2017/09/22 06:31:02 skrll Exp $ */ +/* $NetBSD: a9_mpsubr.S,v 1.52 2017/11/04 17:09:55 skrll Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -357,6 +357,10 @@ cortex_init: teq r0, #(PSR_HYP32_MODE) /* Hyp Mode? */ bne 1f + /* Set CNTVOFF to 0 */ + mov r0, #0 + mcrr p15, 4, r0, r0, c14 + /* Ensure that IRQ, and FIQ will be disabled after eret */ mrs r0, cpsr bic r0, r0, #(PSR_MODE)
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Wed Oct 25 16:09:46 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Improve delay to be better than 1.3 innaccurate by default and handle the
unlikely wrap
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.21 src/sys/arch/arm/cortex/gtmr.c:1.22
--- src/sys/arch/arm/cortex/gtmr.c:1.21 Wed Oct 25 16:08:09 2017
+++ src/sys/arch/arm/cortex/gtmr.c Wed Oct 25 16:09:46 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.21 2017/10/25 16:08:09 skrll Exp $ */
+/* $NetBSD: gtmr.c,v 1.22 2017/10/25 16:09:46 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.21 2017/10/25 16:08:09 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.22 2017/10/25 16:09:46 skrll Exp $");
#include
#include
@@ -245,19 +245,25 @@ gtmr_delay(unsigned int n)
uint32_t freq = sc->sc_freq ? sc->sc_freq : armreg_cnt_frq_read();
KASSERT(freq != 0);
- /*
- * not quite divide by 100 but close enough
- * (higher by 1.3% which means we wait 1.3% longer).
- */
- const uint64_t incr_per_us = (freq >> 20) + (freq >> 24);
+ const unsigned int incr_per_us = howmany(freq, 100);
+ unsigned int delta = 0, usecs = 0;
arm_isb();
- const uint64_t base = armreg_cntp_ct_read();
- const uint64_t delta = n * incr_per_us;
- const uint64_t finish = base + delta;
+ uint64_t last = armreg_cntp_ct_read();
- while (armreg_cntp_ct_read() < finish) {
- arm_isb(); /* spin */
+ while (n > usecs) {
+ arm_isb();
+ uint64_t curr = armreg_cntp_ct_read();
+ if (curr < last)
+ delta += curr + (UINT64_MAX - last);
+ else
+ delta += curr - last;
+
+ last = curr;
+ if (delta >= incr_per_us) {
+ usecs += delta / incr_per_us;
+ delta %= incr_per_us;
+ }
}
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Wed Oct 25 16:08:09 UTC 2017
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.20 src/sys/arch/arm/cortex/gtmr.c:1.21
--- src/sys/arch/arm/cortex/gtmr.c:1.20 Sat Sep 9 13:14:30 2017
+++ src/sys/arch/arm/cortex/gtmr.c Wed Oct 25 16:08:09 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.20 2017/09/09 13:14:30 jmcneill Exp $ */
+/* $NetBSD: gtmr.c,v 1.21 2017/10/25 16:08:09 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.20 2017/09/09 13:14:30 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.21 2017/10/25 16:08:09 skrll Exp $");
#include
#include
@@ -308,7 +308,7 @@ gtmr_intr(void *arg)
#endif
#if 0
- printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n",
+ printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n",
__func__, cf, ci->ci_data.cpu_name, now, delta);
#endif
KASSERTMSG(delta > sc->sc_autoinc / 100,
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Fri Sep 22 06:31:02 UTC 2017 Modified Files: src/sys/arch/arm/cortex: a9_mpsubr.S Log Message: Typo To generate a diff of this commit: cvs rdiff -u -r1.50 -r1.51 src/sys/arch/arm/cortex/a9_mpsubr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/a9_mpsubr.S diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.50 src/sys/arch/arm/cortex/a9_mpsubr.S:1.51 --- src/sys/arch/arm/cortex/a9_mpsubr.S:1.50 Wed Sep 6 18:08:35 2017 +++ src/sys/arch/arm/cortex/a9_mpsubr.S Fri Sep 22 06:31:02 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: a9_mpsubr.S,v 1.50 2017/09/06 18:08:35 jmcneill Exp $ */ +/* $NetBSD: a9_mpsubr.S,v 1.51 2017/09/22 06:31:02 skrll Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -39,7 +39,7 @@ //#define MPDEBUG -// Marco to call routines in .text +// Macro to call routines in .text #if defined(KERNEL_BASES_EQUAL) #define CALL(f) bl _C_LABEL(f) #else
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sat Sep 9 13:14:30 UTC 2017 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: gtmr_intr: If the ISTATUS bit is 0, timer condition is not met. In this case, just return 0. To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gtmr.c diff -u src/sys/arch/arm/cortex/gtmr.c:1.19 src/sys/arch/arm/cortex/gtmr.c:1.20 --- src/sys/arch/arm/cortex/gtmr.c:1.19 Thu Aug 24 13:06:23 2017 +++ src/sys/arch/arm/cortex/gtmr.c Sat Sep 9 13:14:30 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: gtmr.c,v 1.19 2017/08/24 13:06:23 jmcneill Exp $ */ +/* $NetBSD: gtmr.c,v 1.20 2017/09/09 13:14:30 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.19 2017/08/24 13:06:23 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.20 2017/09/09 13:14:30 jmcneill Exp $"); #include #include @@ -292,6 +292,10 @@ gtmr_intr(void *arg) arm_isb(); + const uint32_t ctl = armreg_cntv_ctl_read(); + if ((ctl & ARM_CNTCTL_ISTATUS) == 0) + return 0; + const uint64_t now = armreg_cntv_ct_read(); uint64_t delta = now - ci->ci_lastintr;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Wed Sep 6 18:08:35 UTC 2017 Modified Files: src/sys/arch/arm/cortex: a9_mpsubr.S Log Message: Clear TEX Remap Enable in SCTLR. U-Boot with CONFIG_ARMV8_SWITCH_TO_EL1 sets it since it is RES1 when TTBCR.EAE=1, but we are still using the short descriptor format and don't currently support TEX remap. ok skrll@ To generate a diff of this commit: cvs rdiff -u -r1.49 -r1.50 src/sys/arch/arm/cortex/a9_mpsubr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/a9_mpsubr.S diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.49 src/sys/arch/arm/cortex/a9_mpsubr.S:1.50 --- src/sys/arch/arm/cortex/a9_mpsubr.S:1.49 Mon Jul 24 19:37:41 2017 +++ src/sys/arch/arm/cortex/a9_mpsubr.S Wed Sep 6 18:08:35 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: a9_mpsubr.S,v 1.49 2017/07/24 19:37:41 joerg Exp $ */ +/* $NetBSD: a9_mpsubr.S,v 1.50 2017/09/06 18:08:35 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -166,7 +166,8 @@ arm_boot_l1pt_init: // bits to clear in the Control Register // #define CPU_CONTROL_CLR \ - (CPU_CONTROL_AFLT_ENABLE_CLR) + (CPU_CONTROL_AFLT_ENABLE_CLR | \ + CPU_CONTROL_TR_ENABLE) arm_cpuinit: // Because the MMU may already be on do a typical sequence to set @@ -253,9 +254,7 @@ arm_cpuinit: movt r3, #:upper16:CPU_CONTROL_SET #endif orr r0, r1, r3 -#if defined(CPU_CONTROL_CLR) && (CPU_CONTROL_CLR != 0) bic r0, r0, #CPU_CONTROL_CLR -#endif //cmp r0, r1 // any changes to SCTLR? //bxeq ip //no, then return.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Fri Jul 14 06:33:26 UTC 2017 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: KNF To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic.c diff -u src/sys/arch/arm/cortex/gic.c:1.30 src/sys/arch/arm/cortex/gic.c:1.31 --- src/sys/arch/arm/cortex/gic.c:1.30 Thu Jun 29 00:11:28 2017 +++ src/sys/arch/arm/cortex/gic.c Fri Jul 14 06:33:26 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: gic.c,v 1.30 2017/06/29 00:11:28 jmcneill Exp $ */ +/* $NetBSD: gic.c,v 1.31 2017/07/14 06:33:26 skrll Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -34,14 +34,14 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.30 2017/06/29 00:11:28 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.31 2017/07/14 06:33:26 skrll Exp $"); #include #include +#include #include #include #include -#include #include #include
