[PATCH v2 02/37] clk: rockchip: pll: Fix automatic PLL fractional parameter calculation

[Jonas Karlman]

Use 64-bit arithmetic for f_frac << 24 to prevent truncation before
division when automatically configuring fractional PLLs.

This closely matches the vendor kernel implementation.

Fixes: bbda2ed5840c ("rockchip: clk: pll: add common pll setting funcs")
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
---
v2: New patch
---
 drivers/clk/rockchip/clk_pll.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c
index 74b7ff5faa03..5cb0e954ba4a 100644
--- a/drivers/clk/rockchip/clk_pll.c
+++ b/drivers/clk/rockchip/clk_pll.c
@@ -114,7 +114,7 @@ rockchip_pll_clk_set_by_auto(ulong fin_hz,
        struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table;
        /* FIXME set postdiv1/2 always 1*/
        u32 foutvco = fout_hz;
-       ulong fin_64, frac_64;
+       u64 fin_64, frac_64;
        u32 f_frac, postdiv1, postdiv2;
        ulong clk_gcd = 0;
 
@@ -156,10 +156,10 @@ rockchip_pll_clk_set_by_auto(ulong fin_hz,
 
                f_frac = (foutvco % MHZ);
                fin_64 = fin_hz;
-               fin_64 = fin_64 / rate_table->refdiv;
-               frac_64 = f_frac << 24;
-               frac_64 = frac_64 / fin_64;
-               rate_table->frac = frac_64;
+               do_div(fin_64, (u64)rate_table->refdiv);
+               frac_64 = (u64)f_frac << 24;
+               do_div(frac_64, fin_64);
+               rate_table->frac = (u32)frac_64;
                if (rate_table->frac > 0)
                        rate_table->dsmpd = 0;
                debug("frac = %x\n", rate_table->frac);
-- 
2.55.0