[PATCH v2 20/37] clk: rockchip: rk3576: Fix ACLK_TOP_MID parent selection

[Jonas Karlman]

Write the intended parent clock for the calculated divisor instead of
forcing it to GPLL when ACLK_TOP_MID rate is changed.

Fixes: 3919310b37ec ("clk: rockchip: Add rk3576 clk support")
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
---
Changes in v2:
- Split from "rk3576: Fix trivial clock configuration errors"
- Add fixes tag
---
 drivers/clk/rockchip/clk_rk3576.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3576.c 
b/drivers/clk/rockchip/clk_rk3576.c
index abfd57e2447e..b4a5a145bab0 100644
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -320,8 +320,7 @@ static ulong rk3576_top_set_clk(struct rk3576_clk_priv 
*priv,
                rk_clrsetreg(&cru->clksel_con[10],
                             ACLK_TOP_MID_DIV_MASK |
                             ACLK_TOP_MID_SEL_MASK,
-                            (ACLK_TOP_MID_SEL_GPLL <<
-                             ACLK_TOP_MID_SEL_SHIFT) |
+                            (src_clk << ACLK_TOP_MID_SEL_SHIFT) |
                             (src_clk_div - 1) << ACLK_TOP_MID_DIV_SHIFT);
                break;
        case PCLK_TOP_ROOT:
-- 
2.55.0