[PATCH v2 12/37] clk: rockchip: rk3588: Use correct PLL rate for SCLK_UARTx divider

[Jonas Karlman]

Calculate the divider from the CPLL rate instead of the GPLL rate when
CPLL is selected as the SCLK_UARTx parent.

Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
---
Changes in v2:
- Split from "rk3588: Fix trivial clock configuration errors"
- Add fixes tag
---
 drivers/clk/rockchip/clk_rk3588.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3588.c 
b/drivers/clk/rockchip/clk_rk3588.c
index a4fd3a57ad7f..dbb4cd57e250 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -1343,7 +1343,7 @@ static ulong rk3588_uart_set_rate(struct rk3588_clk_priv 
*priv,
        } else if (priv->cpll_hz % rate == 0) {
                clk_src = CLK_UART_SRC_SEL_CPLL;
                uart_src = CLK_UART_SEL_SRC;
-               div = DIV_ROUND_UP(priv->gpll_hz, rate);
+               div = DIV_ROUND_UP(priv->cpll_hz, rate);
        } else if (rate == OSC_HZ) {
                clk_src = CLK_UART_SRC_SEL_GPLL;
                uart_src = CLK_UART_SEL_XIN24M;
-- 
2.55.0