The RK3528 CLK_SARADC divider field stores the divisor minus one.
Its three bits encode divisors 1-8, allowing rates of 24, 12, 8, 6,
4.8, 4, ~3.43 or 3 MHz from the 24 MHz oscillator.
When the driver requests 1 MHz rate, the required divisor of 24 is
encoded as 23. This value is truncated to 7 in the three-bit field,
selecting a divisor of 8 and producing a 3 MHz clock.
Request 3 MHz explicitly to match the rate already used after value
truncation.
Fixes: 6ef723af18b9 ("adc: rockchip-saradc: Add support for RK3528")
Signed-off-by: Jonas Karlman <[email protected]>
---
v2: New patch
---
drivers/adc/rockchip-saradc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c
index 1515951403c9..15fd6b66d304 100644
--- a/drivers/adc/rockchip-saradc.c
+++ b/drivers/adc/rockchip-saradc.c
@@ -342,7 +342,7 @@ static const struct rockchip_saradc_data rk3399_saradc_data
= {
static const struct rockchip_saradc_data rk3528_saradc_data = {
.num_bits = 10,
.num_channels = 4,
- .clk_rate = 1000000,
+ .clk_rate = 3000000,
.channel_data = rockchip_saradc_channel_data_v2,
.start_channel = rockchip_saradc_start_channel_v2,
};
--
2.55.0
