The dsmpd flag controls whether an rk3036-style PLL uses fractional
mode. When changing from a fractional rate to an integer rate, the
dsmpd field is left cleared, keeping fractional mode active.
Always write dsmpd to the register so integer rates disable fractional
mode. This also matches how Linux configures these PLLs.
Fixes: bbda2ed5840c ("rockchip: clk: pll: add common pll setting funcs")
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
---
Changes in v2:
- Update commit message
- Add fixes tag
- Collect r-b tag
---
drivers/clk/rockchip/clk_pll.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c
index 5cb0e954ba4a..5de930e41dce 100644
--- a/drivers/clk/rockchip/clk_pll.c
+++ b/drivers/clk/rockchip/clk_pll.c
@@ -331,13 +331,12 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock
*pll,
rate->fbdiv);
rk_clrsetreg(base + pll->con_offset + 0x4,
(RK3036_PLLCON1_POSTDIV2_MASK |
- RK3036_PLLCON1_REFDIV_MASK),
+ RK3036_PLLCON1_REFDIV_MASK |
+ RK3036_PLLCON1_DSMPD_MASK),
(rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT |
- rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT));
+ rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT |
+ rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT));
if (!rate->dsmpd) {
- rk_clrsetreg(base + pll->con_offset + 0x4,
- RK3036_PLLCON1_DSMPD_MASK,
- rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT);
writel((readl(base + pll->con_offset + 0x8) &
(~RK3036_PLLCON2_FRAC_MASK)) |
(rate->frac << RK3036_PLLCON2_FRAC_SHIFT),
--
2.55.0
