The PWM clock getter overwrites the 100 MHz rate with the oscillator
rate because the 50 MHz parent test starts a separate if-else statement.
Change to use else-if so the getter returns 100 MHz when the 100 MHz
parent is selected.
Fixes: 5a7a856b132f ("clk: rockchip: Add support for RK3528")
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
---
Changes in v2:
- Split from "rk3528: Fix trivial clock configuration errors"
- Add fixes tag
- Collect r-b tag
---
drivers/clk/rockchip/clk_rk3528.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk3528.c
b/drivers/clk/rockchip/clk_rk3528.c
index cf8c3a623495..812710872729 100644
--- a/drivers/clk/rockchip/clk_rk3528.c
+++ b/drivers/clk/rockchip/clk_rk3528.c
@@ -770,7 +770,7 @@ static ulong rk3528_pwm_get_clk(struct rk3528_clk_priv
*priv, ulong clk_id)
sel = (con & mask) >> shift;
if (sel == CLK_PWM0_SEL_CLK_MATRIX_100M_SRC)
rate = 100 * MHz;
- if (sel == CLK_PWM0_SEL_CLK_MATRIX_50M_SRC)
+ else if (sel == CLK_PWM0_SEL_CLK_MATRIX_50M_SRC)
rate = 50 * MHz;
else
rate = OSC_HZ;
--
2.55.0
