Keep the B0PLL and B1PLL entries formatted in a similar way matching the other PLL entries for consistency.
Signed-off-by: Jonas Karlman <[email protected]> --- v2: Split from "rk3588: Fix trivial clock configuration errors" --- drivers/clk/rockchip/clk_rk3588.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 3b21c7f8465d..aba200ad2390 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -44,11 +44,9 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { static struct rockchip_pll_clock rk3588_pll_clks[] = { [B0PLL] = PLL(pll_rk3588, PLL_B0PLL, RK3588_B0_PLL_CON(0), - RK3588_B0_PLL_MODE_CON, 0, 15, 0, - rk3588_pll_rates), + RK3588_B0_PLL_MODE_CON, 0, 15, 0, rk3588_pll_rates), [B1PLL] = PLL(pll_rk3588, PLL_B1PLL, RK3588_B1_PLL_CON(8), - RK3588_B1_PLL_MODE_CON, 0, 15, 0, - rk3588_pll_rates), + RK3588_B1_PLL_MODE_CON, 0, 15, 0, rk3588_pll_rates), [LPLL] = PLL(pll_rk3588, PLL_LPLL, RK3588_LPLL_CON(16), RK3588_LPLL_MODE_CON, 0, 15, 0, rk3588_pll_rates), [V0PLL] = PLL(pll_rk3588, PLL_V0PLL, RK3588_PLL_CON(88), -- 2.55.0
