[PATCH v2 25/37] clk: rockchip: rk3576: Use correct PLL rate for UART fractional clocks

[Jonas Karlman]

Use the GPLL rate instead of the CPLL rate when GPLL is selected as the
UART fractional clock parent.

Fixes: 3919310b37ec ("clk: rockchip: Add rk3576 clk support")
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
---
Changes in v2:
- Split from "rk3576: Fix trivial clock configuration errors"
- Add fixes tag
---
 drivers/clk/rockchip/clk_rk3576.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3576.c 
b/drivers/clk/rockchip/clk_rk3576.c
index e66368b01b5e..7908a3c95765 100644
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -1715,7 +1715,7 @@ static ulong rk3576_uart_frac_set_rate(struct 
rk3576_clk_priv *priv,
                p_rate = OSC_HZ;
        } else {
                clk_src = CLK_UART_SRC_SEL_GPLL;
-               p_rate = priv->cpll_hz;
+               p_rate = priv->gpll_hz;
        }
 
        rational_best_approximation(rate, p_rate, GENMASK(16 - 1, 0),
-- 
2.55.0