Quoting Salvador Eduardo Tropea <[EMAIL PROTECTED]>:
> Hi Tristan:
>
> On 26/04/08 12:46, Tristan Gingold wrote:
> > On Fri, Apr 25, 2008 at 08:58:39AM -0300, Salvador Eduardo Tropea wrote:
> >
> >> On 25/04/08 00:38, Tristan Gingold wrote:
> >>
> >>> also note that Level2 will delay phy_clk by 1 delta.
> >>>
> >>>
> >> Of course, but it shouldn't change the final result, no?
> >>
> >
> > It can.
> >
>
> For a full synchronous circuit?
Not for a full synchronous circuit. But yours is not fully synchronous.
> The problem isn't here, the problem I'm experimenting is at 666.667 ns
> (666666656fs)
> I think the circuit have just 1 clock. I'm attaching the output
> I'getting from:
> Now is 666666656fs
> delta 0:
> level4.ena_i=1
> level4.tx_clk_i=1
> delta 1:
> clocker.clk=1 ev
>
> From my point of view that's enough: We have a rising_edge and the
> signals are both 1, they will change in the future, not now.
> No logic is in the clock path, but ...
There is logic in the clock path. See level2.vhdl:
l3 : Level3
port map(
clk_i => phy_clk,
--clk_i => clk_i,
ena_i => ena_i);
phy_clk <= clk_i;
> delta 2:
> clocker.clk_o=clk=level1.clk_i=level2.clk_i=1 ev
> clocker.clk6=0 ev
> delta 3:
>
> clocker.clk6_o=clk6=level1.ena_i=level2.ena_i=level3.ena_i=level_4.ena_i=0
> ev
> level2.phy_clk=level3.clk_i=level4.clk_i=1 ev
>
> Here the clock arrives later than the enable.
Right, because of level2.phy_clk.
> delta 4:
> level3.tx_clk=level4.tx_clk_i=0 ev
>
> I guess the condition is evaluated during delta 4 where ena_i is already
> 0 and that's the problem.
Yes, but this is correct IMHO.
> I'm trying to simulate a core for an FPGA and I think the above sequence
> doesn't match the reality. The clock will hit the FFs "instantaneously"
> and the signals will start to slowly change to be stable well before the
> next rising edge, but won't change before the clock arrives. IMHO the
> above sequence should be more like this
>
> delta 0:
> level4.ena_i=1
> level4.tx_clk_i=1
> delta 1:
>
>
clocker.clk=clocker.clk_o=clk=level1.clk_i=level2.clk_i=level2.phy_clk=level3.clk_i=level4.clk_i=1
> ev
>
> <---- The clock doesn't have any logic in its path, just connections.
No, phy_clk is a kind of logic.
> delta 2:
>
> <---- The condition gets evaluated at the beginning of this delta and is
> true.
> <---- signals start to change.
>
> clocker.clk6=0 ev
> delta 3:
>
> clocker.clk6_o=clk6=level1.ena_i=level2.ena_i=level3.ena_i=level_4.ena_i=0
> ev
> delta 4:
> level3.tx_clk=level4.tx_clk_i=0 ev
>
>
> Where is my mistake? How can I solve the problem?
The mistake is in level2. You are adding a delta to clk by
assigning through phy_clk. This assignment may look safe but it isn't: it is
adding a delay.
The clock should be routed only through ports, not through assignments!
Tristan.
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