On Mon, Apr 28, 2008 at 06:15:30PM +0200, Walter F.J. Mueller wrote: > Dear all, > > I fully agree with Tristan "The clock should be routed only through > ports, not through assignments!". The canonical behavioural model of > synchronous logic simply assumes that each process implementing an > edge-triggered element is activated in the same delta cycle. Any > signal assignment of a clock will break this, and imho the compiler > can't possibly optimize this away without breaking the semantics of > the simulation cycle.
Yes. A synchronous design must really be synchronous! Tristan. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
