On 28/04/08 12:13, [EMAIL PROTECTED] wrote: > The mistake is in level2. You are adding a delta to clk by > assigning through phy_clk. This assignment may look safe but it isn't: it is > adding a delay. > IMHO it isn't and GHDL should optimize it at compilation time. This assigment is inside an "if generate" to allow choosing between 2 special clocks (generated using a DLL and hence perfectly coherent). > The clock should be routed only through ports, not through assignments! > Even when they can be solved at compilation time? (if generate, generics, etc.).
Thanks! -- _______________________________________________________________ Ing. Salvador Eduardo Tropea http://utic.inti.gov.ar/ INTI-Electrónica e Informática Tel: (+54 11) 4724 6315 Colectora de Av. General Paz 5445 San Martín - B1650KNA Casilla de Correo 157 FAX: (+54 11) 4754 5194 Buenos Aires * Argentina http://www.inti.gov.ar/ _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
