Salvador Eduardo Tropea wrote:
> On 28/04/08 12:13, [EMAIL PROTECTED] wrote:
>
>>The mistake is in level2. You are adding a delta to clk by
>>assigning through phy_clk. This assignment may look safe but it isn't: it is
>>adding a delay.
>>
>
> IMHO it isn't and GHDL should optimize it at compilation time.
> This assigment is inside an "if generate" to allow choosing between 2
> special clocks (generated using a DLL and hence perfectly coherent).
>
>>The clock should be routed only through ports, not through assignments!
>>
>
> Even when they can be solved at compilation time? (if generate,
> generics, etc.).
>
> Thanks!
>
Dear all,
I fully agree with Tristan "The clock should be routed only through
ports, not through assignments!". The canonical behavioural model of
synchronous logic simply assumes that each process implementing an
edge-triggered element is activated in the same delta cycle. Any
signal assignment of a clock will break this, and imho the compiler
can't possibly optimize this away without breaking the semantics of
the simulation cycle.
Processes sensitive on such a 'derived' clock will execute one delta
cycle after the processes sensitive on the 'original' clock, and
thus see already the updated values of the state registers clocked
with the 'original' clock, which is at variance with the expected
behaviour. A real circuit of course will work due to clock-to-output
delays, but as said, this isn't part of the model here.
With best regards, Walter
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