On Mon, Apr 28, 2008 at 12:55:43PM -0300, Salvador Eduardo Tropea wrote: > On 28/04/08 12:13, [EMAIL PROTECTED] wrote: > > The mistake is in level2. You are adding a delta to clk by > > assigning through phy_clk. This assignment may look safe but it isn't: it > > is > > adding a delay. > > > IMHO it isn't and GHDL should optimize it at compilation time. > This assigment is inside an "if generate" to allow choosing between 2 > special clocks (generated using a DLL and hence perfectly coherent).
There is no such requirement to optimize this case. And such optimization will change the semantic! But with an if-generate statement, you can still select between two clock models using instantiation. > > The clock should be routed only through ports, not through assignments! > > > Even when they can be solved at compilation time? (if generate, > generics, etc.). Even when this is obvious. The basic rule is do not play with the clock signal. Or if you want to play with it, use delay (after xx) to simulate propagation. But using delta delay is asking for troubles. I don't think the behaviour has changed between ghdl 0.25 and 0.26 but I didn't checked. Tristan. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
