On Fri, Apr 25, 2008 at 08:58:39AM -0300, Salvador Eduardo Tropea wrote: > On 25/04/08 00:38, Tristan Gingold wrote: > > also note that Level2 will delay phy_clk by 1 delta. > > > > Of course, but it shouldn't change the final result, no?
It can. Here is my analysis: First, in bug_tb.vhdl, we can replace level1 by level2 without changing anything. To debug, I use --trace-signals --disp-time. At 58333324fs, at beginning of delta 1: clocker.clk = 1 ev delta 2: clocker.clk_o = level2.clk_i = 1 ev clocker.clk6 = 1 ev delta 3: clocker.clk6_o = level4.ena_i = 1 ev level2.phy_clk = 1 ev level3.clk_i = level4.clk_i = 1 ev rising_edge(clk_i) is true but tx_clk_i is not 1. delta 4: level3.tx_clk_1 = 1 ev delta 5: level3.tx_clk = level4.tx_clk_i = 1 ev I don't see any bug. You are simply trying to play with clocks and delta! Tristan. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
